CN114895743A - Low starting current circuit for dynamic bias current LDO - Google Patents
Low starting current circuit for dynamic bias current LDO Download PDFInfo
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- CN114895743A CN114895743A CN202210575238.1A CN202210575238A CN114895743A CN 114895743 A CN114895743 A CN 114895743A CN 202210575238 A CN202210575238 A CN 202210575238A CN 114895743 A CN114895743 A CN 114895743A
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- 230000003044 adaptive effect Effects 0.000 claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000003068 static effect Effects 0.000 abstract description 12
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Abstract
The invention relates to a linear voltage regulator chip, in particular to a low starting current circuit for a dynamic bias current LDO. It includes a power circuit and a control circuit. The input end of the power circuit is connected with VIN, and the output end of the power circuit outputs VOUT. The control circuit comprises an operational amplifier and a MOS tube N3, wherein the non-inverting input end of the operational amplifier is connected with a reference voltage VREF, the inverting input end of the operational amplifier is in adaptive connection with the control circuit, the inverting input end of the operational amplifier is used for receiving voltage feedback VFB of the control circuit, the output end of the operational amplifier is connected with the grid electrode of the MOS tube N3, and the drain electrode of the MOS tube N3 is in adaptive connection with the power circuit. It is characterized by also comprising a comparator. The source of the MOS transistor N3 is connected with one end of a resistor R3, and the other end of the resistor R3 is grounded. The output end of the power circuit is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is connected with VIN, and the output end of the comparator is connected with the source electrode of the MOS transistor N3. The LDO adopting the circuit has small static power consumption and small static current during starting.
Description
Technical Field
The invention relates to a linear voltage regulator chip, in particular to a low starting current circuit for a dynamic bias current LDO.
Background
Along with the development of science and technology, more and more linear power chips are needed in the power supply field at present, and the LDO with low output voltage and large current is widely applied to various MCUs and mainboards. As is known, the LDO has two types, namely a P-type differential pair transport amplifier and an N-type differential pair transport amplifier, and when the LDO is used for a low output voltage, the FB voltage is very low, and the N-type differential pair needs a higher working voltage, generally >1V, because of the G terminal, under this condition, the LDO using the N-type differential pair cannot normally work, but the LDO of the P-type differential pair transport amplifier does not have this problem, and the LDO of the P-type differential pair transport amplifier usually adopts a dynamic bias current manner in order to improve the load carrying capacity and the dynamic characteristic, as shown in fig. 1. However, the drawback of excessive quiescent current at startup is caused by the fact that the output does not reach the set value at low input voltage, the high voltage pulled by the G terminal of the output terminal N3 of the transport amplifier controls the power P transistor to give more current to make the output reach the set value, and the quiescent power consumption of this path is very large, as shown in the path of the MOS transistor P5 and the MOS transistor N3 in fig. 1.
Disclosure of Invention
The invention aims to solve the technical problem of improving a low-starting-current circuit for a dynamic bias current LDO (low dropout regulator), wherein the LDO adopting the circuit has small static power consumption and small static current during starting. The problems of large static power consumption and overlarge static current during starting in the background technology are solved.
In order to solve the problems, the following technical scheme is provided:
the low-starting-current circuit for the dynamic bias current LDO comprises a power circuit and a control circuit. The input end of the power circuit is connected with VIN, and the output end of the power circuit outputs VOUT. The control circuit comprises an operational amplifier and a MOS tube N3, wherein the non-inverting input end of the operational amplifier is connected with a reference voltage VREF, the inverting input end of the operational amplifier is in adaptive connection with the control circuit, the inverting input end of the operational amplifier is used for receiving a voltage feedback VFB of the control circuit, the output end of the operational amplifier is connected with the grid electrode of the MOS tube N3, and the drain electrode of the MOS tube N3 is in adaptive connection with the power circuit. It is characterized by also comprising a comparator. The source electrode of the MOS transistor N3 is connected with one end of a resistor R3, and the other end of the resistor R3 is grounded. The output end of the power circuit is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is connected with VIN, and the output end of the comparator is connected with the source electrode of the MOS transistor N3.
The output end of the power circuit is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the output end of the transport amplifier and one end of a resistor R2 respectively, and the other end of the resistor R2 is grounded.
The power circuit comprises a first current mirror, wherein the first current mirror comprises a MOS transistor P5 and a MOS transistor P6. The source electrode of the MOS tube P5 and the source electrode of the MOS tube P6 are both connected with VIN, the grid electrode of the MOS tube P5 is respectively connected with the drain electrode of the MOS tube P5 and the grid electrode of the MOS tube P6, the drain electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube N3, and the drain electrode of the MOS tube P6 is the output end of the power circuit.
The operational amplifier comprises a MOS transistor P1, a MOS transistor P2 and a second current mirror, wherein the second current mirror comprises a MOS transistor N1 and a MOS transistor N2. The grid electrode of the MOS tube P1 is the non-inverting input end of the operational amplifier, the grid electrode of the MOS tube P2 is the inverting input end of the operational amplifier, and the source electrode of the MOS tube P1 is connected with the source electrode of the MOS tube P2 to form a power supply current end of the operational amplifier. The drain electrode of the MOS tube P1 is respectively connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are grounded. The drain of the MOS transistor P2 is the output terminal of the operational amplifier, and is connected to the drain of the MOS transistor P2 and the drain of the MOS transistor N2.
The comparator comprises a differential pair, a resistor R4, a resistor R5, a MOS transistor N4, a MOS transistor N5 and a MOS transistor N6; the differential pair comprises a MOS transistor P7 and a MOS transistor P8. The source electrode of the MOS tube P7 is the non-inverting input end of the comparator, the source electrode of the MOS tube P8 is the inverting input end of the comparator, and the drain electrode of the MOS tube N6 is the output end of the comparator. The grid of the MOS tube P7 is connected with the drain of the MOS tube P7 and the grid of the MOS tube P8 respectively, the drain of the MOS tube P7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the drain of the MOS tube N4, the source of the MOS tube N4 is grounded, and the grid of the MOS tube N4 is connected with the grid of the MOS tube N5 and the grid of the MOS tube N1 respectively. The drain electrode of the MOS tube P8 is connected with one end of a resistor R5, the other end of the resistor R5 is respectively connected with the grid electrode of the MOS tube N6 and the drain electrode of the MOS tube N5, and the source electrodes of the MOS tube N5 and the MOS tube N6 are both grounded.
The power supply current end of the operational amplifier is connected with a current mirror IV in an adaptive mode, the current mirror IV comprises an MOS tube P3 and an MOS tube P4, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are both connected with a power supply VDD, the grid electrode of the MOS tube P3 is connected with the drain electrode of the MOS tube P4 and the grid electrode of the MOS tube P3, the drain electrode of the MOS tube P3 is connected with a basic current IB, and the drain electrode of the MOS tube P4 is connected with the power supply current end of the operational amplifier.
By adopting the scheme, the method has the following advantages:
the source electrode of the MOS transistor N3 of the low starting current circuit for the dynamic bias current LDO is connected with one end of the resistor R3, the other end of the resistor R3 is grounded, the output end of the power circuit is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is connected with VIN, and the output end of the comparator is connected with the source electrode of the MOS transistor N3. During operation, when the input voltage is low, the MOS transistor N6 is in a turn-off state, the resistor R3 has a large resistance, and in a static state, because the resistance of the R3 is large, when a small current flows, the source end of the N3 is pulled high to enter a semi-conducting state, and the R3 plays a role in stopping, so that the static power consumption of the circuit is reduced. When the input voltage is larger than the output voltage certain value, the output end of the comparator is pulled high, N6 is conducted, the resistor R3 is short-circuited by N6, and large current can flow between the source and the drain of the MOS transistor N3, so that the power circuit obtains driving voltage, the whole chip works normally, the problem that static current flows through the large current when the chip is started is solved, when the input voltage is larger than the output voltage certain value, the light load output can be ensured to be normal only by small current flowing through paths P5 and N3, and the problem is solved.
Drawings
FIG. 1 is a circuit diagram of a prior art LDO of a P-type differential pair transport amplifier;
FIG. 2 is a circuit schematic of the low start-up current circuit for a dynamic bias current LDO of the present invention;
FIG. 3 is a graph of the quiescent current waveform and output voltage waveform of an LDO without the circuit of the present invention DC-swept at VIN from 0V to 5V;
FIG. 4 is a graph of the quiescent current waveform and output voltage waveform of an LDO incorporating the circuit of the present invention with a DC sweep at VIN from 0V to 5V;
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 2, the low-start-up current circuit for a dynamic bias current LDO of the present invention includes a power circuit, a control circuit, and a comparator 4. The input end of the power circuit is connected with VIN, and the output end of the power circuit outputs VOUT. The control circuit comprises an operational amplifier 2 and an MOS tube N3, the non-inverting input end of the operational amplifier 2 is connected with a reference voltage VREF, the inverting input end of the operational amplifier 2 is connected with the control circuit in an adaptive mode, the inverting input end of the operational amplifier 2 is used for receiving a voltage feedback VFB of the control circuit, the output end of the operational amplifier 2 is connected with the grid electrode of the MOS tube N3, and the drain electrode of the MOS tube N3 is connected with the power circuit in an adaptive mode. The source electrode of the MOS transistor N3 is connected with one end of a resistor R3, and the other end of the resistor R3 is grounded. The output end of the power circuit is connected with the non-inverting input end of the comparator 4, the inverting input end of the comparator 4 is connected with VIN, and the output end of the comparator 4 is connected with the source electrode of the MOS transistor N3. The output end of the power circuit is connected with one end of a resistor R1, the other end of a resistor R1 is respectively connected with the output end of the transport amplifier and one end of a resistor R2, and the other end of the resistor R2 is grounded.
The resistor R2 plays a role of a large resistor, and may be replaced by other electrical components capable of realizing the function of the large resistor.
The power circuit comprises a first current mirror 3, wherein the first current mirror 3 comprises a MOS transistor P5 and a MOS transistor P6. The source electrode of the MOS tube P5 and the source electrode of the MOS tube P6 are both connected with VIN, the grid electrode of the MOS tube P5 is respectively connected with the drain electrode of the MOS tube P5 and the grid electrode of the MOS tube P6, the drain electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube N3, and the drain electrode of the MOS tube P6 is the output end of the power circuit.
The operational amplifier 2 comprises a MOS transistor P1, a MOS transistor P2 and a second current mirror 6, wherein the second current mirror 6 comprises a MOS transistor N1 and a MOS transistor N2. The gate of the MOS transistor P1 is the non-inverting input terminal of the operational amplifier 2, the gate of the MOS transistor P2 is the inverting input terminal of the operational amplifier 2, and the source of the MOS transistor P1 is connected to the source of the MOS transistor P2 to form the power supply current terminal of the operational amplifier 2. The drain electrode of the MOS tube P1 is respectively connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are grounded. The drain of the MOS transistor P2 is the output terminal of the operational amplifier 2, and is connected to the drain of the MOS transistor P2 and the drain of the MOS transistor N2.
The comparator 4 comprises a differential pair 5, a resistor R4, a resistor R5, a MOS transistor N4, a MOS transistor N5 and a MOS transistor N6. The differential pair 5 is a differential pair of a current comparator. The differential pair 5 comprises a MOS transistor P7 and a MOS transistor P8. The source electrode of the MOS transistor P7 is the non-inverting input terminal of the comparator 4, the source electrode of the MOS transistor P8 is the inverting input terminal of the comparator 4, and the drain electrode of the MOS transistor N6 is the output terminal of the comparator 4. The grid of the MOS tube P7 is connected with the drain of the MOS tube P7 and the grid of the MOS tube P8 respectively, the drain of the MOS tube P7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the drain of the MOS tube N4, the source of the MOS tube N4 is grounded, and the grid of the MOS tube N4 is connected with the grid of the MOS tube N5 and the grid of the MOS tube N1 respectively. The drain electrode of the MOS tube P8 is connected with one end of a resistor R5, the other end of the resistor R5 is respectively connected with the grid electrode of the MOS tube N6 and the drain electrode of the MOS tube N5, and the source electrodes of the MOS tube N5 and the MOS tube N6 are both grounded.
The power supply current end of the operational amplifier 2 is connected with a current mirror four 1 in an adaptive mode, the current mirror four 1 comprises an MOS tube P3 and an MOS tube P4, a source electrode of the MOS tube P3 and a source electrode of the MOS tube P4 are both connected with a power supply VDD, a grid electrode of the MOS tube P3 is connected with a drain electrode of the MOS tube P3 and a grid electrode of the MOS tube P4 respectively, a drain electrode of the MOS tube P3 is connected with a basic current IB, and a drain electrode of the MOS tube P4 is connected with the power supply current end of the operational amplifier 2.
The low-starting current circuit of the dynamic bias current LDO utilizes the resistor R3 to limit the excessive static power consumption, the comparator 4 consisting of R4, R5, P7, P8, N4, N5 and N6 is added, when the input voltage is greater than the output voltage by a certain value, the N6 is conducted, the chip works normally, and the value is determined by adjusting the proportion of P7 and P8 and the resistance values of R4 and R5.
In this embodiment, the resistance of the resistor R3 is greater than 1 megaohm, and in a static state, because the resistance of R3 is large, when a small current flows, the source end of the N3 is pulled high to enter a semi-conducting state, and the R3 plays a role in stopping, so that the static power consumption of the circuit is reduced.
When VIN is larger than a certain value of VOUT, the value is determined by adjusting the proportion of the MOS transistor P7 and the MOS transistor P8 and the resistance values of the resistor R4 and the resistor R5, the output end of the operational amplifier 2 sends a signal, the MOS transistor N3 is conducted, the output end of the comparator 4 is pulled high, the signal is used as the basic current of the current mirror I3 through the MOS transistor N3 and is input into the current mirror I3, and the LDO works normally.
Fig. 3 and 4 show the LDO simulation waveforms with VIN scanned from 0V to 5V, the upper half of fig. 3 and 4 shows the quiescent current waveform, and the lower half shows the output voltage waveform, as shown in fig. 3, the quiescent power consumption before LDO without the circuit of the present invention is at most about 2 Ma. As shown in FIG. 4, the quiescent power consumption of the LDO after the circuit of the invention is added is about 2uA at most, thereby greatly reducing the quiescent power consumption of the LDO and perfectly solving the problem of overlarge quiescent current during starting.
Claims (6)
1. A low start-up current circuit for a dynamic bias current LDO comprises a power circuit and a control circuit; the input end of the power circuit is connected with VIN, and the output end of the power circuit outputs VOUT; the control circuit comprises an operational amplifier (2) and a MOS (metal oxide semiconductor) tube N3, wherein the non-inverting input end of the operational amplifier (2) is connected with a reference voltage VREF, the inverting input end of the operational amplifier (2) is connected with the control circuit in an adaptive manner, the inverting input end of the operational amplifier (2) is used for receiving the voltage feedback VFB of the control circuit, the output end of the operational amplifier (2) is connected with the grid electrode of the MOS tube N3, and the drain electrode of the MOS tube N3 is connected with the power circuit in an adaptive manner; it is characterized by also comprising a comparator (4); the source electrode of the MOS transistor N3 is connected with one end of a resistor R3, and the other end of the resistor R3 is grounded; the output end of the power circuit is connected with the non-inverting input end of the comparator (4), the inverting input end of the comparator (4) is connected with VIN, and the output end of the comparator (4) is connected with the source electrode of the MOS transistor N3.
2. The low on-current circuit of claim 1, wherein the output terminal of the power circuit is connected to one terminal of a resistor R1, the other terminal of the resistor R1 is connected to the output terminal of the transport amplifier and one terminal of a resistor R2, and the other terminal of the resistor R2 is connected to ground.
3. The low on-current circuit for the dynamic bias current LDO according to claim 1, wherein the power circuit comprises a current mirror one (3), the current mirror one (3) comprising a MOS transistor P5 and a MOS transistor P6; the source electrode of the MOS tube P5 and the source electrode of the MOS tube P6 are both connected with VIN, the grid electrode of the MOS tube P5 is respectively connected with the drain electrode of the MOS tube P5 and the grid electrode of the MOS tube P6, the drain electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube N3, and the drain electrode of the MOS tube P6 is the output end of the power circuit.
4. The low on-current circuit for the dynamic bias current LDO according to claim 1, wherein the operational amplifier (2) comprises a MOS transistor P1, a MOS transistor P2, and a current mirror two (6), the current mirror two (6) comprising a MOS transistor N1 and a MOS transistor N2; the grid electrode of the MOS tube P1 is the non-inverting input end of the operational amplifier (2), the grid electrode of the MOS tube P2 is the inverting input end of the operational amplifier (2), and the source electrode of the MOS tube P1 is connected with the source electrode of the MOS tube P2 to form a power supply current end of the operational amplifier (2); the drain electrode of the MOS tube P1 is respectively connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are grounded; the drain of the MOS transistor P2 is the output end of the operational amplifier (2), and is connected with the drain of the MOS transistor P2 and the drain of the MOS transistor N2.
5. The low on-current circuit for the dynamic bias current LDO according to claim 4, wherein said comparator (4) comprises a differential pair (5), a resistor R4, a resistor R5, a MOS transistor N4, a MOS transistor N5 and a MOS transistor N6; the differential pair (5) comprises an MOS transistor P7 and an MOS transistor P8; the source electrode of the MOS tube P7 is the non-inverting input end of the comparator (4), the source electrode of the MOS tube P8 is the inverting input end of the comparator (4), and the drain electrode of the MOS tube N6 is the output end of the comparator (4); the grid of the MOS tube P7 is connected with the drain of the MOS tube P7 and the grid of the MOS tube P8 respectively, the drain of the MOS tube P7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the drain of the MOS tube N4, the source of the MOS tube N4 is grounded, and the grid of the MOS tube N4 is connected with the grid of the MOS tube N5 and the grid of the MOS tube N1 respectively; the drain electrode of the MOS tube P8 is connected with one end of a resistor R5, the other end of the resistor R5 is respectively connected with the grid electrode of the MOS tube N6 and the drain electrode of the MOS tube N5, and the source electrodes of the MOS tube N5 and the MOS tube N6 are both grounded.
6. The low start-up current circuit for the dynamic bias current LDO according to any of claims 1-5, wherein the current mirror four (1) is adaptively connected to the power current terminal of the operational amplifier (2), the current mirror four (1) comprises a MOS transistor P3 and a MOS transistor P4, the source of the MOS transistor P3 and the source of the MOS transistor P4 are both connected to the power supply VDD, the gate of the MOS transistor P3 is connected to the drain thereof and the gate of the MOS transistor P4, the drain of the MOS transistor P3 is connected to the basic current IB, and the drain of the MOS transistor P4 is connected to the power current terminal of the operational amplifier (2).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210575238.1A CN114895743A (en) | 2022-05-25 | 2022-05-25 | Low starting current circuit for dynamic bias current LDO |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210575238.1A CN114895743A (en) | 2022-05-25 | 2022-05-25 | Low starting current circuit for dynamic bias current LDO |
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| CN202210575238.1A Pending CN114895743A (en) | 2022-05-25 | 2022-05-25 | Low starting current circuit for dynamic bias current LDO |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117032378A (en) * | 2023-08-24 | 2023-11-10 | 无锡迈尔斯通集成电路有限公司 | Low-power consumption LDO circuit based on depletion type MOS tube |
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| CN215642444U (en) * | 2021-09-13 | 2022-01-25 | 苏州大学 | Low quiescent current NMOS type fully integrated LDO circuit |
| US20220066493A1 (en) * | 2020-09-11 | 2022-03-03 | Hangzhou Vango Technologies, Inc. | Voltage regulator |
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| CN117032378A (en) * | 2023-08-24 | 2023-11-10 | 无锡迈尔斯通集成电路有限公司 | Low-power consumption LDO circuit based on depletion type MOS tube |
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