CN215117306U - Apply to soft start circuit of power saving province area of LDO - Google Patents
Apply to soft start circuit of power saving province area of LDO Download PDFInfo
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- CN215117306U CN215117306U CN202023231265.2U CN202023231265U CN215117306U CN 215117306 U CN215117306 U CN 215117306U CN 202023231265 U CN202023231265 U CN 202023231265U CN 215117306 U CN215117306 U CN 215117306U
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- 239000003990 capacitor Substances 0.000 claims abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 3
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 230000005611 electricity Effects 0.000 abstract 1
- 208000031266 Microcystic stromal tumor Diseases 0.000 description 6
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Abstract
The utility model discloses a soft start circuit applied to LDO and saving electricity and area, which comprises a first current source, a second current source, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube and a capacitor; one end of the first current source, the drain electrode of the first MOS tube and the grid electrode of the second MOS tube are connected to the first node; one end of a second current source, the drain electrode of the second MOS tube, the grid electrode of the third MOS tube and one end of the capacitor are electrically connected to a second node; the other end of the capacitor and the source electrodes of the first MOS tube and the second MOS tube are all grounded; a grid electrode of the first MOS tube receives a starting signal EA _ ST; the source electrode and the drain electrode of the third MOS tube are respectively and electrically connected with the source electrode and the drain electrode of the fourth MOS tube; the fourth MOS tube is positioned in an error amplifier of the LDO, and a grid electrode of the fourth MOS tube is led out to be used as a positive input end of the error amplifier to receive a reference voltage signal. The utility model can achieve the function of soft start output by using fewer components without using a complex control circuit.
Description
Technical Field
The utility model relates to an electronic circuit especially relates to an apply to soft start circuit of the power saving area of LDO (Low drop out regulator).
Background
An LDO is a linear regulator that uses a transistor or Field Effect Transistor (FET) operating in its saturation region to subtract excess voltage from the applied input voltage to produce a regulated output voltage. A conventional LDO regulator generates a large current in the initial stage of external power supply, and a so-called Peak current (Peak current) is generated by adding an instantaneous output to a load, which may cause damage due to a reduction in the tolerance of components, and cause a start-up overshoot, where the voltage at the output end of the LDO varies with time as shown in fig. 1.
Disclosure of Invention
The purpose of the invention is as follows: for overcoming the problem among the prior art, the utility model discloses an aspect aims at providing one kind and applies to the soft start circuit of the power saving province area of LDO. On the other hand, the utility model provides an LDO including above-mentioned soft start circuit.
The technical scheme is as follows: on the one hand, the utility model discloses an apply to soft start circuit of the power saving province area of LDO. The soft start circuit includes: the device comprises a first current source, a second current source, a first MOS (metal oxide semiconductor) transistor, a second MOS transistor, a third MOS transistor and a capacitor; one end of the first current source, the drain electrode of the first MOS tube and the grid electrode of the second MOS tube are connected to the first node; one end of a second current source, the drain electrode of the second MOS tube, the grid electrode of the third MOS tube and one end of the capacitor are electrically connected to a second node; the other end of the capacitor and the source electrodes of the first MOS tube and the second MOS tube are all grounded; a grid electrode of the first MOS tube receives a starting signal EA _ ST; the source electrode and the drain electrode of the third MOS tube are respectively and electrically connected with the source electrode and the drain electrode of the fourth MOS tube; the fourth MOS tube is positioned in an error amplifier of the LDO, and a grid electrode of the fourth MOS tube is led out to be used as a positive input end of the error amplifier to receive a reference voltage signal.
Furthermore, the first MOS tube and the second MOS tube are both NMOS tubes; and the third MOS tube and the fourth MOS tube are both PMOS tubes.
Further, the first current source and the second current source respectively comprise two PMOS tubes connected in series, and the gates of the two PMOS tubes connected in series receive the first bias voltage and the second bias voltage respectively; and in two PMOS tubes which are connected in series and respectively comprise the first current source and the second current source, the source electrodes of the PMOS tubes far away from the first MOS tube and the second MOS tube are electrically connected with an external power supply.
Further, the start signal and the reference voltage signal are both from a bandgap reference voltage circuit.
On the other hand, the utility model discloses an LDO including above-mentioned soft start circuit. The LDO also comprises an error amplifier, a frequency compensation circuit, a power tube, a first feedback resistor and a second feedback resistor; the output end of the error amplifier is electrically connected with the grid electrode of the power tube through the frequency compensation circuit; the source electrode of the power tube is connected with an external power supply, and the drain electrode of the power tube is grounded through a first feedback resistor and a second feedback resistor which are connected in series; and the negative input end of the error amplifier is electrically connected with the connection point of the first feedback resistor and the second feedback resistor.
Further, the error amplifier includes: the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the third current source; the source electrodes of the fourth MOS tube and the fifth MOS tube are electrically connected with the third current source; the drain electrode of the fourth MOS tube is electrically connected with the drain electrode and the grid electrode of the sixth MOS tube and the grid electrode of the seventh MOS tube; the drain electrode of the fifth MOS is electrically connected with the drain electrode of the seventh MOS tube; the source electrodes of the sixth MOS tube and the seventh MOS tube are grounded; and the grid electrode of the fifth MOS tube is led out to be used as the negative input end of the error amplifier.
Furthermore, the fourth MOS transistor and the fifth MOS transistor are both PMOS transistors; the sixth MOS tube and the seventh MOS tube are both NMOS tubes; the power tube is a P-type power tube.
Has the advantages that: compared with the prior art, the invention has the following advantages:
(1) the function of soft start output (i.e. restraining the start overshoot) can be achieved by using three MOS transistors M1-M3, two current sources I1 and I2 and a capacitor MCST without using a complex control circuit, so that the used circuit elements are few, the area of the whole chip can be saved, and the power consumption can be reduced;
(2) the method is suitable for various LDO circuits and has good compatibility.
Drawings
FIG. 1 is a diagram of the variation of the output voltage of an LDO with time when a starting overshoot occurs in the conventional LDO;
fig. 2 is a schematic structural diagram of an LDO including a soft start circuit according to an embodiment of the present invention;
fig. 3 is a graph showing the variation of the output voltage of the LDO with time according to an embodiment of the present invention.
Detailed Description
The embodiment will describe an LDO including a soft start circuit with power saving and area saving, and a specific circuit diagram thereof is shown in fig. 2.
Referring to fig. 2, the LDO includes a soft start circuit, an error amplifier, a frequency compensation circuit, a power transistor MPO, a first feedback resistor RF1 and a second feedback resistor RF 2. Wherein the soft start circuit is connected with the error amplifier. The output end of the error amplifier is electrically connected with the grid electrode of the power tube MPO through the frequency compensation circuit. The source of the power tube MPO is connected with an external power supply VCC, and the drain is connected with the ground GND through a first feedback resistor RF1 and a second feedback resistor RF2 which are connected in series. The negative input terminal of the error amplifier is electrically connected to the junction of the first feedback resistor RF1 and the second feedback resistor RF 2. The power tube is a P-type power tube.
The soft start circuit will be described in detail below.
The soft start circuit includes: the circuit comprises a first current source I1, a second current source I2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a capacitor MCST. One end of the first current source I1, the drain of the first MOS transistor M1, and the gate of the second MOS transistor M2 are connected to the first node. One end of the second current source I2, the drain of the second MOS transistor M2, the gate of the third MOS transistor M3, and one end of the capacitor MCST are electrically connected to the second node. The other end of the capacitor MCST, the sources of the first MOS transistor M1 and the second MOS transistor M2 are all grounded GND. The gate of the first MOS transistor M1 receives the enable signal EA _ ST. The first MOS tube and the second MOS tube are both PMOS tubes; the third MOS tube and the fourth MOS tube are both NMOS tubes.
The first current source I1 includes two PMOS transistors P11 and P12 connected in series, and the second current source I2 includes two PMOS transistors P21 and P22 connected in series. The gates of P11 and P21 receive the first bias voltage VB1, respectively, and the gates of P12 and P22 receive the second bias voltage VB2, respectively. The sources of the P11 far away from the first MOS transistor M1 and the P21 far away from the second MOS transistor M2 are electrically connected to an external power source VCC.
The error amplifier includes: a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, and a third current source I3. The sources of the fourth MOS transistor M4 and the fifth MOS transistor M5 are electrically connected to the third current source I3. The drain of the fourth MOS transistor M4 is electrically connected to the drain and the gate of the sixth MOS transistor M6 and the gate of the seventh MOS transistor M7. The drain of the fifth MOS transistor M5 is electrically connected to the drain of the seventh MOS transistor M7. The sources of the sixth MOS transistor M6 and the seventh MOS transistor M7 are both grounded. The grid of the fourth MOS transistor M4 is led out as the positive input end of the error amplifier to receive the reference voltage signal Vref. The grid electrode of the fifth MOS tube M5 is led out to be used as the negative input end of the error amplifier so as to be electrically connected with the connection point of the first feedback resistor RF1 and the second feedback resistor RF 2. The fourth MOS transistor M4 and the fifth MOS transistor M5 are both PMOS transistors. The sixth MOS transistor M6 and the seventh MOS transistor M7 are both NMOS transistors. The third current source I3, like the first and second current sources, also comprises two PMOS transistors P31 and P32 in series. The gates of P31 and P32 are respectively connected to the first bias voltage VB1 and the second bias voltage VB 2.
When the soft start circuit is connected with the error amplifier, the source and the drain of the third MOS transistor M3 in the soft start circuit are electrically connected with the source and the drain of the fourth MOS transistor M4, respectively. The starting signal EA _ ST received by the soft starting circuit and the reference voltage signal Vref received by the error amplifier are both from a band-gap reference voltage circuit. The bandgap reference voltage circuit is a conventional circuit, which can be roughly simplified into a current source and a plurality of resistors connected in series with the current source, EA _ ST and Vref are respectively led out from different resistor connection points, and the voltage corresponding to EA _ ST is usually greater than the voltage corresponding to Vref, because in this embodiment, EA _ ST is connected to the gate of the NMOS transistor M1, and Vref is connected to the gate of the PMOS transistor M4.
The frequency compensation circuit can be implemented by the prior art, which is commonly available in LDO and will not be described in detail herein.
The working principle is as follows: when the external power supply VCC is initially and rapidly powered on, the start signal EA _ ST is initially 0, the potential of the EA _ SD point at the gate of the second MOS transistor M2 is 1, and the M2 is turned on, so that the gate potential of the third MOS transistor M3 is 0, and it can be known that when the external power supply VCC is rapidly powered on, the M3 is in a complete conduction state, and the fourth MOS transistor M4 is short-circuited, so that the gate of the power transistor MPO inputs a high level, which results in complete shutdown of the MPO. Therefore, when the external initial power VCC is rapidly powered up, the output VOUT of the LDO is 0. After a short time, EA _ ST is changed to 1, so that the potential of EA _ SD point at the gate of M2 becomes 0, M2 is turned off, at this time, the MOS capacitor MCST is slowly charged by a small current generated by the second current source I2, so that the gate voltage of the third MOS transistor M3 slowly reaches VCC potential to completely turn off M3, the gate potential of the power transistor MPO also slowly decreases from VCC to a normal potential of actual operation, so that the power transistor MPO is slowly turned on, and the output VOUT of the LDO slowly rises to reach the function of soft start of the output voltage, as shown in fig. 3.
As can be seen from comparing fig. 1 and fig. 3, the above embodiment of the present invention can realize the function of outputting soft start (i.e. suppressing start overshoot). Meanwhile, since the above embodiment only needs to use three MOS transistors M1-M3, two current sources I1 and I2, and one capacitor MCST, and does not need to use a complicated control circuit, the number of circuit elements used is small, the area of the whole chip can be saved, and the power consumption can be reduced.
In addition to the above embodiments, the present invention can also have other embodiments, and all technical solutions formed by equivalent replacement or equivalent transformation fall within the protection scope of the present invention.
Claims (7)
1. The utility model provides an apply to soft start circuit of power saving province area of LDO which characterized in that includes: the device comprises a first current source, a second current source, a first MOS (metal oxide semiconductor) transistor, a second MOS transistor, a third MOS transistor and a capacitor; one end of the first current source, the drain electrode of the first MOS tube and the grid electrode of the second MOS tube are connected to the first node; one end of a second current source, the drain electrode of the second MOS tube, the grid electrode of the third MOS tube and one end of the capacitor are electrically connected to a second node; the other end of the capacitor and the source electrodes of the first MOS tube and the second MOS tube are all grounded; a grid electrode of the first MOS tube receives a starting signal EA _ ST; the source electrode and the drain electrode of the third MOS tube are respectively and electrically connected with the source electrode and the drain electrode of the fourth MOS tube; the fourth MOS tube is located in an error amplifier of the LDO, and a grid electrode of the fourth MOS tube is led out to serve as a positive input end of the error amplifier to receive a reference voltage signal Vref.
2. The power-saving and area-saving soft-start circuit for an LDO of claim 1, wherein the first MOS transistor and the second MOS transistor are both NMOS transistors; and the third MOS tube and the fourth MOS tube are both PMOS tubes.
3. The power and area saving soft start circuit for use in an LDO of claim 2, wherein the first and second current sources each comprise two PMOS transistors connected in series, and the gates of the two PMOS transistors connected in series receive the first and second bias voltages, respectively; and in two PMOS tubes which are connected in series and respectively comprise the first current source and the second current source, the source electrodes of the PMOS tubes far away from the first MOS tube and the second MOS tube are electrically connected with an external power supply.
4. The area efficient soft-start circuit for LDO according to claim 1, wherein said enable signal EA _ ST and said reference voltage signal Vref are both from a bandgap reference voltage circuit.
5. A power-saving and area-saving soft start circuit for LDO according to any of claims 1-3, further comprising an error amplifier, a frequency compensation circuit, a power transistor, a first feedback resistor and a second feedback resistor; the output end of the error amplifier is electrically connected with the grid electrode of the power tube through the frequency compensation circuit; the source electrode of the power tube is connected with an external power supply, and the drain electrode of the power tube is grounded through a first feedback resistor and a second feedback resistor which are connected in series; and the negative input end of the error amplifier is electrically connected with the connection point of the first feedback resistor and the second feedback resistor.
6. The area efficient soft-start circuit for an LDO according to claim 5, wherein said error amplifier comprises: the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the third current source; the source electrodes of the fourth MOS tube and the fifth MOS tube are electrically connected with the third current source; the drain electrode of the fourth MOS tube is electrically connected with the drain electrode and the grid electrode of the sixth MOS tube and the grid electrode of the seventh MOS tube; the drain electrode of the fifth MOS is electrically connected with the drain electrode of the seventh MOS tube; the source electrodes of the sixth MOS tube and the seventh MOS tube are grounded; and the grid electrode of the fifth MOS tube is led out to be used as the negative input end of the error amplifier.
7. The power-saving and area-saving soft-start circuit for an LDO according to claim 5, wherein the fourth MOS transistor and the fifth MOS transistor are both PMOS transistors; the sixth MOS tube and the seventh MOS tube are both NMOS tubes; the power tube is a P-type power tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023231265.2U CN215117306U (en) | 2020-12-28 | 2020-12-28 | Apply to soft start circuit of power saving province area of LDO |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023231265.2U CN215117306U (en) | 2020-12-28 | 2020-12-28 | Apply to soft start circuit of power saving province area of LDO |
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| Publication Number | Publication Date |
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| CN215117306U true CN215117306U (en) | 2021-12-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202023231265.2U Active CN215117306U (en) | 2020-12-28 | 2020-12-28 | Apply to soft start circuit of power saving province area of LDO |
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Address after: Building 63, Jinghui Science and Technology Innovation Park, 123 Jinghui West Road, Xinwu District, Wuxi City, Jiangsu Province, 214000 Patentee after: Jiangsu Yangheyang Microelectronics Technology Co.,Ltd. Country or region after: China Address before: Room 905, Xinpu science and technology innovation center, 20 Yuhe Road, Pukou District, Nanjing City, Jiangsu Province, 210000 Patentee before: NANJING HEYANGTEK Co.,Ltd. Country or region before: China |