CN212586761U - Easy-to-integrate voltage stabilizing circuit based on low-voltage amplifier - Google Patents
Easy-to-integrate voltage stabilizing circuit based on low-voltage amplifier Download PDFInfo
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- CN212586761U CN212586761U CN202021592848.5U CN202021592848U CN212586761U CN 212586761 U CN212586761 U CN 212586761U CN 202021592848 U CN202021592848 U CN 202021592848U CN 212586761 U CN212586761 U CN 212586761U
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Abstract
The utility model discloses an easily integrated voltage stabilizing circuit based on low-voltage amplifier, which comprises an adjusting branch and an output branch, wherein the adjusting branch comprises a first NMOS pipe and a feedback adjusting circuit connected with the source electrode of the first NMOS pipe, the output branch comprises a second NMOS pipe, and the output of the voltage stabilizing circuit is taken from the source electrode of the second NMOS pipe; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the high-voltage power supply voltage is connected with the drain electrode and the grid electrode of the first NMOS tube through a bias current source; the feedback adjusting circuit comprises a low-voltage amplifier and a voltage lifting circuit, the positive input end and the negative input end of the low-voltage amplifier are respectively connected with a reference voltage VREF and a feedback signal, and the output of the low-voltage amplifier is connected with the source electrode of the first NMOS tube through the voltage lifting circuit. The utility model does not need high-voltage resistant capacitance to compensate; the method can be realized by increasing the number of MOS tubes without increasing the types of devices in the process; the device is fully integrated without external components.
Description
Technical Field
The utility model belongs to the technical field of voltage stabilizing circuit technique and specifically relates to an easily integrated voltage stabilizing circuit based on low-voltage amplifier.
Background
When the conventional amplifier is used for designing the LDO, high-voltage-resistant capacitors are needed for phase compensation. However, a high withstand voltage capacitor is not easily realized in an integrated IC, and even if a process supports a high withstand voltage compensation capacitor, a poor matching degree of a high voltage tube may cause an increase in the area of the LD O or deterioration in performance.
SUMMERY OF THE UTILITY MODEL
To the technical problem, the utility model provides an easily integrated voltage stabilizing circuit based on low-voltage amplifier.
An easily-integrated voltage stabilizing circuit based on a low-voltage amplifier is composed of a regulating branch circuit and an output branch circuit, wherein the regulating branch circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube and a feedback regulating circuit connected to a source electrode of the first NMOS tube, the output branch circuit comprises a second NMOS tube, and the output of the voltage stabilizing circuit is taken from the source electrode of the second NMOS tube; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the high-voltage power supply voltage is connected with the drain electrode and the grid electrode of the first NMOS tube through a bias current source; the feedback adjusting circuit comprises a low-voltage amplifier and a voltage lifting circuit, the positive input end and the negative input end of the low-voltage amplifier are respectively connected with a reference voltage VREF and a feedback signal, and the output of the low-voltage amplifier is connected with the source electrode of the first NMOS tube through the voltage lifting circuit.
Furthermore, the feedback signal is taken from the output branch, the source electrode of the second NMOS tube is grounded through a first adjusting resistor and a second adjusting resistor in sequence, and the positive input end and the negative input end of the low-voltage amplifier are respectively connected with a reference voltage VREF and a second adjusting resistor voltage.
Or the feedback signal is taken from the regulating branch, the source electrode of the first NMOS tube is grounded through a first regulating resistor and a second regulating resistor in sequence, and the positive and negative input ends of the low-voltage amplifier are respectively connected with a reference voltage VREF and a second regulating resistor voltage; and the source electrode of the second NMOS tube is grounded through a grounding resistor.
Or, the grid electrode of the first NMOS tube is grounded through a first adjusting resistor and a second adjusting resistor in sequence, and the positive and negative input ends of the low-voltage amplifier are respectively connected with a reference voltage VREF and a second adjusting resistor voltage; and the source electrode of the second NMOS tube is grounded through a grounding resistor.
Furthermore, the voltage lifting circuit is composed of a plurality of PMOS tubes connected in sequence in a grid-drain mode, the output of the low-voltage amplifier is connected with a grid electrode of the first PMOS tube, and a source electrode of the last PMOS tube is connected with a source electrode of the first NMOS tube.
Furthermore, the voltage lifting circuit is composed of a PMOS tube and a voltage stabilizing diode, the output of the low-voltage amplifier is connected with the grid electrode of the PMOS tube, and the source electrode of the PMOS tube is connected with the source electrode of the first NMOS tube through the voltage stabilizing diode.
The utility model has the advantages that: 1. high-voltage-resistant capacitors are not needed for compensation, and the output of the LDO is not influenced by the matching degree of the high-voltage tube; 2. the method can be realized by increasing the number of MOS tubes without increasing the types of devices in the process; 3. the device is fully integrated without external components.
Drawings
FIG. 1 is a schematic diagram of a voltage regulator circuit according to embodiment 1;
FIG. 2 is a schematic diagram of a voltage regulator circuit according to embodiment 2;
FIG. 3 is a schematic diagram of a voltage regulator circuit according to embodiment 3;
FIG. 4 is a schematic diagram of a voltage boost circuit;
FIG. 5 is a schematic diagram of another voltage boost circuit.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The embodiments of the present invention have been presented for purposes of illustration and description, and are not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Example 1
The voltage stabilizing circuit is composed of an adjusting branch circuit and an output branch circuit, the adjusting branch circuit comprises a first NMOS tube NM1 and a feedback adjusting circuit connected to a source electrode of the first NMOS tube, the output branch circuit comprises a second NMOS tube NM2, and the output of the voltage stabilizing circuit is taken from the source electrode of the second NMOS tube. The grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the high-voltage power supply voltage is connected with the drain electrode and the grid electrode of the first NMOS tube through a bias current source I1; the feedback adjusting circuit comprises a low-voltage amplifier and a voltage lifting circuit, the positive input end and the negative input end of the low-voltage amplifier are respectively connected with a reference voltage VREF and a feedback signal, and the output of the low-voltage amplifier is connected with the source electrode of the first NMOS tube through the voltage lifting circuit.
In this embodiment, the feedback signal is obtained from the output branch, as shown in fig. 1, the source of the second NMOS transistor is grounded through a first adjusting resistor R1 and a second adjusting resistor R2 in sequence, and the positive and negative input terminals of the low-voltage amplifier are respectively connected to a reference voltage VREF and a second adjusting resistor voltage.
The low-voltage amplifier works normally, and the voltages of the positive input end and the negative input end of the low-voltage amplifier are approximately equal, namely VREF and the voltage at the point A are approximately equal. The output LDO _ OUT is higher than VDD and has driving capability by the ratio of the first trimming resistor R1 and the second trimming resistor R2. The normal work of the low-voltage amplifier is ensured by adjusting the lifting voltage of the voltage lifting circuit. Due to the process angle deviation and the temperature deviation of device parameters, the lifting voltage deviation of the voltage lifting circuit is large, but the maximum tolerable lifting voltage deviation range of the voltage lifting circuit is 0V-VDD in combination with the low-voltage amplifier. In this embodiment, the output LDO _ OUT is in the feedback loop, so that the output voltage value is more accurate.
The bias current I1 is used to provide a dc operating point for the first NMOS transistor NM 1. Two voltage domains, namely low voltage VDD and high voltage HVDD, exist inside the chip. The input voltage of the low-voltage amplifier is VDD, namely the low-voltage amplifier works in a low-voltage domain, and the output range of the low-voltage amplifier is 0V-VDD; the first NMOS tube and the second NMOS tube work in a high-voltage domain. The bias current I1 can be replaced by a common resistor, and is preferably a constant current source made of PMOS.
The voltage boost circuit in the feedback regulation circuit may have various implementation manners, for example, the voltage boost circuit is composed of a plurality of PMOS transistors connected in sequence with gate and drain, as shown in fig. 4, the output of the low-voltage amplifier is connected to the gate of a first PMOS transistor, the source of the last PMOS transistor is connected to the source of a first NMOS transistor, the specific number of the PMOS transistors is set according to actual needs, and is 3 in fig. 4; the low-voltage amplifier can also be composed of a PMOS transistor and a zener diode, as shown in fig. 5, the output of the low-voltage amplifier is connected to the gate of the PMOS transistor, and the source of the PMOS transistor is connected to the source of the first NMOS transistor through the zener diode.
Example 2
Different from embodiment 1, the feedback signal is obtained from the adjusting branch, the source of the first NMOS transistor NM1 is grounded through a first adjusting resistor R1 and a second adjusting resistor R2 in sequence, and the positive and negative input ends of the low-voltage amplifier are respectively connected to a reference voltage VREF and a second adjusting resistor voltage; the second NMOS transistor NM2 is grounded via a grounding resistor R3, as shown in fig. 2.
The embodiment is suitable for an application with a less precise requirement on the output LDO _ OUT, and the LDO _ OUT is not in a loop, so that the stability of the circuit is easier to ensure, but the LDO _ OUT voltage slightly changes with the change of the load current and the ambient temperature.
Example 3
Different from embodiment 1, the feedback signal is obtained from the adjusting branch, the gate of the first NMOS transistor NM1 is grounded through a first adjusting resistor R1 and a second adjusting resistor R2 in sequence, and the positive and negative input ends of the low-voltage amplifier are respectively connected to a reference voltage VREF and a second adjusting resistor voltage; the second NMOS transistor NM2 is grounded via a grounding resistor R3, as shown in fig. 3.
The embodiment is also suitable for the application that the output LDO _ OUT is not in the loop, which makes it easier to ensure the stability of the circuit, but the LDO _ OUT voltage may have slight change along with the change of the load current and the ambient temperature.
It is obvious that the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art and related fields without creative efforts shall fall within the protection scope of the present disclosure.
Claims (6)
1. An easily-integrated voltage stabilizing circuit based on a low-voltage amplifier is characterized by comprising an adjusting branch circuit and an output branch circuit, wherein the adjusting branch circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube and a feedback adjusting circuit connected to a source electrode of the first NMOS tube, the output branch circuit comprises a second NMOS tube, and the output of the voltage stabilizing circuit is taken from the source electrode of the second NMOS tube;
the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the high-voltage power supply voltage is connected with the drain electrode and the grid electrode of the first NMOS tube through a bias current source; the feedback adjusting circuit comprises a low-voltage amplifier and a voltage lifting circuit, the positive input end and the negative input end of the low-voltage amplifier are respectively connected with a reference voltage VREF and a feedback signal, and the output of the low-voltage amplifier is connected with the source electrode of the first NMOS tube through the voltage lifting circuit.
2. The easy-to-integrate voltage regulator circuit of claim 1, wherein the feedback signal is taken from the output branch, the source of the second NMOS transistor is grounded through a first adjusting resistor and a second adjusting resistor in sequence, and the positive and negative input terminals of the low voltage amplifier are respectively connected to a reference voltage VREF and a second adjusting resistor voltage.
3. The easy-to-integrate voltage stabilizing circuit of claim 1, wherein the feedback signal is taken from the regulating branch, the source of the first NMOS transistor is grounded through a first regulating resistor and a second regulating resistor in sequence, and the positive and negative input ends of the low-voltage amplifier are respectively connected to a reference voltage VREF and a second regulating resistor voltage; and the source electrode of the second NMOS tube is grounded through a grounding resistor.
4. The easy-to-integrate voltage stabilizing circuit of claim 1, wherein the feedback signal is taken from the regulating branch, the grid of the first NMOS tube is grounded through a first regulating resistor and a second regulating resistor in sequence, and the positive and negative input ends of the low-voltage amplifier are respectively connected with a reference voltage VREF and a second regulating resistor voltage; and the source electrode tube of the second NMOS is grounded through a grounding resistor.
5. The voltage regulator circuit of any one of claims 2 to 4, wherein the voltage boost circuit is formed by a plurality of PMOS transistors connected in sequence with gates and drains, the output of the low voltage amplifier is connected with the gate of a first PMOS transistor, and the source of the last PMOS transistor is connected with the source of a first NMOS transistor.
6. The easy-to-integrate voltage stabilizing circuit according to any one of claims 2 to 4, wherein the voltage boost circuit is composed of a PMOS transistor and a voltage stabilizing diode, the output of the low voltage amplifier is connected with the grid electrode of the PMOS transistor, and the source electrode of the PMOS transistor is connected with the source electrode of the first NMOS transistor through the voltage stabilizing diode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021592848.5U CN212586761U (en) | 2020-08-04 | 2020-08-04 | Easy-to-integrate voltage stabilizing circuit based on low-voltage amplifier |
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| CN202021592848.5U CN212586761U (en) | 2020-08-04 | 2020-08-04 | Easy-to-integrate voltage stabilizing circuit based on low-voltage amplifier |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115202427A (en) * | 2021-04-09 | 2022-10-18 | 上海艾为电子技术股份有限公司 | Voltage stabilizing circuit and power management chip |
| CN117478139A (en) * | 2023-12-21 | 2024-01-30 | 上海芯炽科技集团有限公司 | Multiplication analog-to-digital converter of high-speed low-voltage ADC |
-
2020
- 2020-08-04 CN CN202021592848.5U patent/CN212586761U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115202427A (en) * | 2021-04-09 | 2022-10-18 | 上海艾为电子技术股份有限公司 | Voltage stabilizing circuit and power management chip |
| CN115202427B (en) * | 2021-04-09 | 2023-12-12 | 上海艾为电子技术股份有限公司 | Voltage stabilizing circuit and power management chip |
| CN117478139A (en) * | 2023-12-21 | 2024-01-30 | 上海芯炽科技集团有限公司 | Multiplication analog-to-digital converter of high-speed low-voltage ADC |
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