CN107024958B - A kind of linear voltage-stabilizing circuit with fast load transient response - Google Patents
A kind of linear voltage-stabilizing circuit with fast load transient response Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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Abstract
A kind of linear voltage-stabilizing circuit with fast load transient response, belongs to technical field of power management.Buffer output level circuit including clamper operational amplifier circuit and containing adaptive adjustment circuit, it can be applied to digital load, clamper operational amplifier circuit input reference voltage, obtain obtaining final required voltage as a reference voltage, then by the Buffer output level with certain load capacity with the equal-sized voltage of required voltage；The present invention adds adaptive adjustment circuit so that variable quantity of the output voltage in full-load range reduces very much, its load capacity has also strengthened.The present invention effectively realizes quick load transient response and less output voltage variation delta V while circuit structure complexity is simplifiedout。
Description
Technical field
The invention belongs to technical field of power management, and in particular to a kind of linear voltage stabilization with fast load transient response
Circuit.
Background technology
With the fast development of electronic technology, Switching Power Supply develops towards low-voltage and high-current direction, low-tension supply conversion
The research of device becomes the developing direction to become more and more important with application.Turn the design of the converter of 3V for 5V, due to no longer pressure difference
The limitation of (Dropout Voltage), therefore low pressure difference linear voltage regulator (LDO) of the N pipes as power tube can be used, relatively
In P pipes as the smaller of low pressure difference linear voltage regulator LDO, N the pipe needs of power tube, and since N pipes are as power tube
The output resistance of low pressure difference linear voltage regulator is 1/gm,n, (wherein gm,nFor the mutual conductance of N-type power tube) loop bandwidth is larger, transient state
Response speed compared with P pipes as power tube low pressure difference linear voltage regulator faster.In the application of low-voltage high speed digital circuit, when opening
When pass frequency is very high, i.e. the di/dt of load current conversion is very big, in order to ensure the reliability Work of digital circuit, it is desirable to supply
Electric module has response speed and load capacity quickly.
The loop bandwidth of traditional on-chip capacitance low pressure difference linear voltage regulator LDO limited configurations limits its peak response
Speed, is quickly switched into when overloaded, the variation delta V of output voltage when loading from underloadingoutIt may make digital circuit can not when big
Normal work, and the low pressure difference linear voltage regulator LDO of the outer bulky capacitor of strap is due to the presence of bulky capacitor outside piece so that the collection of circuit
It is difficult lifting into degree, and in order to ensure the stability of loop, the selection to capacitance outside piece has certain requirement, therefore traditional low
Pressure difference linear voltage regulator LDO is difficult to apply to this kind of high-speed digital circuit.
The content of the invention
In order to solve conventional low difference linear constant voltage regulator LDO since limited loop bandwidth is difficult to meet low-voltage high speed numeral
The power demands of circuit, the present invention propose a kind of linear voltage-stabilizing circuit with fast load transient response, which has fast
The transient response speed of speed, can meet big di/dt load change slopes, and the variation delta with less output voltage
Vout, it is easily integrated.
The technical scheme is that：
A kind of linear voltage-stabilizing circuit with fast load transient response, including clamper operational amplifier circuit and buffering output stage electricity
Road, the input terminal input reference voltage Vref of the clamper operational amplifier circuit,
The Buffer output level circuit include the second capacitance C3,3rd resistor R3, the 6th resistance R6, the 3rd PMOS tube MP3,
First PNP triode PNP1, the 3rd NPN triode NPN3, output capacitance COUTWith adaptive adjustment circuit,
The base stage of first PNP triode PNP1 is followed by the output terminal of the clamper operational amplifier circuit by 3rd resistor R3, its
Emitter connects drain electrode and the base stage of the 3rd NPN triode NPN3 of the 3rd PMOS tube MP3, its grounded collector；3rd PMOS tube
The grid of MP3 meets the first bias voltage Vb1, its source electrode connects supply voltage；Second capacitance C3 is connected to the 3rd NPN triode NPN3
Base stage and ground between, the emitter of the 3rd NPN triode NPN3 passes through the 6th resistance R6 and output capacitance COUTParallel-connection structure
After be grounded, its collector connects supply voltage；
The adaptive adjustment circuit include the 4th resistance R4, the 5th resistance R5, the first capacitance C2, the 4th NMOS tube MN4,
4th PMOS tube MP4, the first NPN triode NPN1, the second NPN triode NPN2 and the second PNP triode PNP2,
4th resistance R4 and the 5th resistance R5 series connection, its series connection point connect the drain electrode of the 4th NMOS tube MN4, the 4th NMOS tube
The grid of MN4 connects the second bias voltage Vb2, its source electrode ground connection；Another termination clamper operational amplifier circuit of 5th resistance R5
Output terminal, the base stage of the second PNP triode of another termination PNP2 of the 4th resistance R4, the emitter of the second PNP triode PNP2
Connect the emitter of the first NPN triode NPN1, its grounded collector；
The base stage sum aggregate electrode interconnection of first NPN triode NPN1 and drain electrode and the 2nd NPN for connecting the 4th PMOS tube MP4
The base stage of triode NPN2；The grid of 4th PMOS tube MP4 meets the first bias voltage Vb1, its source electrode connects supply voltage；Second
The collector of NPN triode NPN2 connects supply voltage, its emitter connects the base stage of the 3rd NPN triode NPN3；First capacitance
C2 is connected between base stage and the ground of the second NPN triode NPN2.
Specifically, the clamper operational amplifier circuit include the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3,
Source with NMOS tube MN, the first PMOS tube MP1, the second PMOS tube MP2, compensating electric capacity C1, first resistor R1 and second resistance R2,
The source electrode of first NMOS tube MN1 and the second NMOS tube MN2 interconnect and connect the drain electrode of the 3rd NMOS tube MN3, and first
Input terminal of the grid of NMOS tube MN1 as the clamper operational amplifier circuit, the grid of the 3rd NMOS tube MN3 connect the second biased electrical
Press Vb2；
The grid leak short circuit of first PMOS tube MP1 and drain electrode and the grid of the second PMOS tube MP2 for connecting the first NMOS tube MN1
Pole, source connect the drain electrode of the second NMOS tube MN2 and the second PMOS tube MP2 with the grid of NMOS tube MN and are followed by by compensating electric capacity C1
Ground；
First resistor R1 and second resistance R2 series connection, its series connection point connect the grid of the second NMOS tube MN2, first resistor R1
Another termination source with NMOS tube MN source electrode and as the output terminal of the clamper operational amplifier circuit, the other end of second resistance R2
It is grounded with the source electrode of the 3rd NMOS tube MN3, the source electrode and source of the first PMOS tube MP1 and the second PMOS tube MP2 are with NMOS tube MN
Drain electrode connect supply voltage.
Specifically, the output capacitance COUTFor 100pF.
Beneficial effects of the present invention are：The linear voltage-stabilizing circuit of the present invention obtains the electricity with needing using clamper operational amplifier circuit
Equal-sized voltage is pressed finally to be needed as a reference voltage, then by the Buffer output level with certain load capacity
The voltage wanted, while circuit structure complexity is simplified, effectively realizes quick load transient response and less
Output voltage variation delta Vout；The output voltage of linear voltage-stabilizing circuit provided by the invention does not feed back to clamper amplifier
Adjustment loop is not present in input, system, and bandwidth is no longer restricted, therefore the speed of transient response is very fast；Add adaptive adjust
Whole circuit so that variable quantity of the output voltage in full-load range reduces very much, its load capacity has also strengthened.
Brief description of the drawings
Fig. 1 is linear voltage-stabilizing circuit equivalent architectures figure proposed by the present invention；
Fig. 2 is a kind of practical circuit diagram of linear voltage-stabilizing circuit with fast load transient response proposed by the present invention；
Fig. 3 contrasts for circuit of the present invention and conventional low difference linear constant voltage regulator LDO transient response waveforms figure；
Fig. 4 (a) be when having adaptive adjustment circuit and without adaptive adjustment circuit output voltage with load current change
Change curve；
Fig. 4 (b) is output voltage V in the case of circuit load transient state 100ns saltus steps of the present inventionoutChange curve；
Fig. 5 is the variable quantity △ V of output voltage in the range of full load (Io=0~10mA)outAnd underloading (Io=
0.5mA, 1mA, 1.5mA) under circuit consume total current IINWith the relation curve of the 5th resistance R5 values.
Embodiment
The present invention is described in detail with reference to the accompanying drawings and detailed description.
It is linear voltage-stabilizing circuit equivalent architectures figure proposed by the present invention as shown in Figure 1, linear voltage stabilization electricity provided by the invention
Road can be applied to digital load, be powered using clamper amplifier combining buffer (buffer) to digital load, due to system not
It is the system of an open loop in the presence of feedback loop is adjusted, transient response speed is no longer limited by loop bandwidth, substantially increased negative
Carry the speed of transient response.In order to ensure the variation delta V of output voltageoutIt is as far as possible small, meet that the power supply of digital load circuit will
Ask, it is particularly important that the design of buffer buffer circuits.
It is proposed by the present invention that there is the linear voltage-stabilizing circuit of fast load transient response as shown in Fig. 2, being made of two parts,
Clamper operational amplifier circuit and buffering output-stage circuit, the input terminal input reference voltage Vref of clamper operational amplifier circuit, Buffer output level
Circuit includes the second capacitance C3,3rd resistor R3, the 6th resistance R6, the 3rd PMOS tube MP3, the first PNP triode PNP1, the 3rd
NPN triode NPN3, output capacitance COUTWith adaptive adjustment circuit, the base stage of the first PNP triode PNP1 passes through 3rd resistor
R3 is followed by the output terminal of clamper operational amplifier circuit, its emitter connects the drain electrode of the 3rd PMOS tube MP3 with the 3rd NPN triode NPN3's
Base stage, its grounded collector；The grid of 3rd PMOS tube MP3 meets the first bias voltage Vb1, its source electrode connects supply voltage；Second
Capacitance C3 is connected between base stage and the ground of the 3rd NPN triode NPN3, and the emitter of the 3rd NPN triode NPN3 passes through the 6th
Resistance R6 and output capacitance COUTParallel-connection structure after be grounded, its collector connects supply voltage；Adaptive adjustment circuit includes the 4th
Resistance R4, the 5th resistance R5, the first capacitance C2, the 4th NMOS tube MN4, the 4th PMOS tube MP4, the first NPN triode NPN1,
Two NPN triode NPN2 and the second PNP triode PNP2, the 4th resistance R4 and the 5th resistance R5 series connection, its series connection point connect the 4th
The drain electrode of NMOS tube MN4, the grid of the 4th NMOS tube MN4 meet the second bias voltage Vb2, its source electrode ground connection；5th resistance R5's
The output terminal of another termination clamper operational amplifier circuit, the base stage of the second PNP triode of another termination PNP2 of the 4th resistance R4, second
The emitter of PNP triode PNP2 connects the emitter of the first NPN triode NPN1, its grounded collector；First NPN triode
The base stage sum aggregate electrode interconnection of NPN1 and drain electrode and the base stage of the second NPN triode NPN2 for connecting the 4th PMOS tube MP4；4th
The grid of PMOS tube MP4 meets the first bias voltage Vb1, its source electrode connects supply voltage；The collector of second NPN triode NPN2 connects
Supply voltage, its emitter connect the base stage of the 3rd NPN triode NPN3；First capacitance C2 is connected to the second NPN triode
Between the base stage and ground of NPN2.
Clamper operational amplifier circuit includes the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, source with NMOS tube
MN, the first PMOS tube MP1, the second PMOS tube MP2, compensating electric capacity C1, first resistor R1 and second resistance R2, the first NMOS tube
The source electrode of MN1 and the second NMOS tube MN2 interconnect and connect the drain electrode of the 3rd NMOS tube MN3, the grid conduct of the first NMOS tube MN1
The input terminal of clamper operational amplifier circuit, the grid of the 3rd NMOS tube MN3 connect the second bias voltage Vb2；The grid of first PMOS tube MP1
Leak short circuit and connect drain electrode and the grid of the second PMOS tube MP2 of the first NMOS tube MN1, source connects second with the grid of NMOS tube MN
The drain electrode of NMOS tube MN2 and the second PMOS tube MP2 and by being grounded after compensating electric capacity C1；First resistor R1 and second resistance R2 strings
Connection, its series connection point connect the grid of the second NMOS tube MN2, another termination source of first resistor R1 with NMOS tube MN source electrode and work
For the output terminal of clamper operational amplifier circuit, the source electrode ground connection of the other end of second resistance R2 and the 3rd NMOS tube MN3, the first PMOS tube
The source electrode and source of MP1 and the second PMOS tube MP2 connect supply voltage with the drain electrode of NMOS tube MN.
Output level C in some embodimentsOUTFor 100pF, it is possible to achieve the on piece of circuit integrates, it is not necessary to plug-in electricity again
Hold.
Clamper amplifier part is made of difference amplifier, follower and resistance-feedback network, can according to negative-feedback principle
Obtain Vb=Vref(R1+R2)/R2, wherein VbFor b points voltage, the i.e. output voltage of clamper operational amplifier circuit in Fig. 2.Due to VbNeed not
Big current loading is driven, source can be made small with the size of NMOS tube MN, need to only provide in rear class Buffer output level circuit
Drain current enough the 4th NMOS tube MN4 of bias current sources.The difference amplifier includes the first NMOS tube MN1, the 2nd NMOS
Pipe MN2, the 3rd NMOS tube MN3, the first PMOS tube MP1 and the second PMOS tube MP2, the advantage is that and be easy to compensate.Capacitance C1 is
Compensating electric capacity, two limit are
P1=1/ (ro,MP2//ro,MN2)C1
P2=gm,MN/CL
Wherein CLFor the equivalent capacity of clamper amplifier output over the ground, ro,MP2For the impedance of the second PMOS tube MP2, ro,MN2For
The impedance of two NMOS tube MN2, due to P2An only limit, meets loop phase nargin in high frequency, unit gain frequency>
45°.In addition there is more preferable power supply rejection ratio (PSRR) with output stages of the NMOS tube MN as clamper operational amplifier circuit using source.
In loop bandwidth, high loop gain inhibits influence of the electric source disturbance to output, and high frequency treatment, is limited to loop bandwidth, source
The influence disturbed with the grid end of NMOS tube MN from supply voltage, at the same MN pipe for source with structure, its source voltage terminal is from power supply
The influence of voltage, therefore there is the clamper amplifier higher high frequency electric source to suppress to compare PSRR.
Buffer output level includes the first PNP triode PNP1 and the 3rd NPN triode NPN3, due to the 3rd NPN triode
NPN3 needs to provide big load current, and the size of the 3rd NPN triode NPN3 must be sufficiently large, its optimal size is according to load
Electric current, current amplification factor β and current density relation curve make choice.3rd NPN triode NPN3 at work, its base stage
Electric current is provided by the 3rd PMOS tube MP3, and the 3rd PMOS tube MP3 pipes play bias current sources, while conduct in circuit
The load of first PNP triode PNP1, circuit can obtain according to Fig. 2
WhereinFor load current, α is the first NPN triode NPN3 and the first PNP triode PNP1 saturation collector currents
The ratio between Is,NPN3/Is,PNP1, VTFor thermal voltage, id,MP3For the leakage current of the 3rd PMOS tube MP3 pipes.Order
When the load electric current is small, Δ V=>0, then Vout=Vb+ΔV>Vb；When load current is larger, Δ V<0, Vout=Vb+ΔV
<Vb.The electric current that 3rd PMOS tube MP3 can be provided is limited, is jumped to when overloaded when loading from underloading, output voltage Vout
The variation delta V of declineoutChange is very big, in order to ensure output voltage VoutThe Δ V in full-load rangeoutIt is smaller, it is desirable to provide
The bias current of bigger, this will cause the increase of quiescent dissipation.Therefore adaptive adjustment circuit is added herein, by the 4th
PMOS tube MP4, the first NPN triode NPN1, the second NPN triode NPN2, the second PNP triode PNP2, the 4th resistance R4,
Five resistance R5 and the 4th NMOS tube MN4 compositions, wherein the 4th PMOS tube MP4 and the 4th NMOS tube MN4 are bias current sources, when
When load transient does big saltus step, the effect of transient state enhancing is played, the key of transient state enhancing is the second NPN triode NPN2
Pipe, the pressure drop ignored on 3rd resistor R3 and the 4th resistance R4 can obtain
WhereinWithFor the emitter current of PNP2 and PNP1 pipes, id,MP4For the leakage current of MP4 pipes.It is negative
When load electric current is smaller, the 3rd PMOS tube MP3 pipes are capable of providing the base current enough to the 3rd NPN triode NPN3, in order to carry
Power-efficient under high underloading, the second NPN triode NPN2, which need not be opened, provides unnecessary electric current.In order to ensure under underloading
The current density of one PNP triode PNP1 and the second PNP triode PNP2 are equal, selectionWherein SPNP1And SPNP2The emitter area of respectively PNP1 and PNP2,
WithThe respectively breadth length ratio of MP3 and MP4 pipes, then Δ VBe, PNP2-PNP1≈ 0, at this time Vbe,NPN2=VBe, NPN1-R5id,MN4<
Vbe.When load current increases,Reduce, Δ VBe, PNP2-PNP1Increase, Vbe,NPN2Increase with the increase of load current,
Second NPN triode NPN2, which is gradually opened, provides more electric currents, relative to without adaptive adjustment circuit, the 3rd PMOS tube MP3
The base current of offer reduces, more the first PNP triode of current direction PNP1, therefore the hair of the first PNP triode PNP1
Emitter voltage Vc is slowed by with the speed that load current increases and reduces, the variation delta V of output voltageoutDiminish.
Under heavy duty：
In full-load range, it can be obtained by formula (1) and (4)
WhereinFor load current under underloading,For load current under heavy duty, as can be seen from the above equation, output voltage
Variation delta VoutWithIncrease and reduce, there are Δ V at this timeoutWith the compromise problem of quiescent current.
Assuming that the lower load current of heavy dutyThe maximum variable quantity of corresponding output voltage Vout isAccording to upper
Formula can solve the emitter current I of the second NPN triode NPN2 at this timeE, NPN2, then by IE, NPN2With the relational expression of the 5th resistance R5
Solve corresponding R5max, then load current under heavy loadsUnder conditions of meet Δ Vout≤Δ Voutmax, then the 5th resistance
The selection of R5 should meet R5≤R5max.In addition, the second NPN triode NPN2 and the 3rd NPN triode NPN3 as can be seen from Figure 2
Darlington structure is formed, its Current amplifier ability is effectively strengthened.
Fig. 3 is circuit of the present invention and conventional low difference linear constant voltage regulator LDO transient response waveform figures, with traditional low voltage difference
Linear voltage regulator LDO transient responses are otherwise varied, and reason is that traditional low pressure difference linear voltage regulator LDO is that closed loop is
System, output voltage feed back to the output terminal of error amplifier, and output voltage can return to original by pincers after system, which responds, to be completed
The value come, and the low pressure difference linear voltage regulator LDO output voltages of said structure do not have the input for feeding back to clamper amplifier, system
There is no adjustment loop, bandwidth is no longer restricted, therefore the speed of transient response is very fast, and adjustment of load depends primarily upon the 3rd
The I-V relations of NPN triode NPN3.Therefore output voltage VoutExchange variation delta VACWith its direct current variation delta VDCPhase
Deng the generally speaking variation delta V of the output voltage of the linear voltage-stabilizing circuit of low pressure difference linear voltage regulator LDO proposed in this paperout
Less than the variation delta V of output voltage in traditional LDO circuitoutValue.Fig. 4 (a) is to have adaptive adjustment circuit and without adaptive
The output voltage of adjustment circuit with load current change curve, it can be seen that add after adaptive adjustment circuit, output electricity
The variable quantity being pressed in full-load range reduces very much, its load capacity has also strengthened.Fig. 4 (b) jumps for load transient 100ns
Output voltage V in the case of changeoutChange curve, Fig. 5 is △ V in the range of full load (Io=0~10mA)out, underloading (Io=
0.5mA, 1mA, 1.5mA) under circuit consume total current IINWith the relation curve of the 5th resistance R5 values.
Those of ordinary skill in the art these disclosed technical inspirations can make various do not depart from originally according to the present invention
The other various specific deformations and combination, these deformations and combination of invention essence are still within the scope of the present invention.
Claims (3)
1. a kind of linear voltage-stabilizing circuit with fast load transient response, including clamper operational amplifier circuit and buffering output stage electricity
Road, the input terminal input reference voltage (Vref) of the clamper operational amplifier circuit, it is characterised in that
The Buffer output level circuit includes the second capacitance (C3), 3rd resistor (R3), the 6th resistance (R6), the 3rd PMOS tube
(MP3), the first PNP triode (PNP1), the 3rd NPN triode (NPN3), output capacitance (COUT) and adaptive adjustment circuit,
The base stage of first PNP triode (PNP1) is followed by the output terminal of the clamper operational amplifier circuit by 3rd resistor (R3), its
Emitter connects the drain electrode of the 3rd PMOS tube (MP3) and the base stage of the 3rd NPN triode (NPN3), its grounded collector；3rd
The grid of PMOS tube (MP3) connects the first bias voltage (Vb1), its source electrode connects supply voltage；Second capacitance (C3) is connected to the 3rd
Between the base stage and ground of NPN triode (NPN3), the emitter of the 3rd NPN triode (NPN3) passes through the 6th resistance (R6) and defeated
Go out capacitance (COUT) parallel-connection structure after be grounded, its collector connects supply voltage；
The adaptive adjustment circuit includes the 4th resistance (R4), the 5th resistance (R5), the first capacitance (C2), the 4th NMOS tube
(MN4), the 4th PMOS tube (MP4), the first NPN triode (NPN1), the second NPN triode (NPN2) and the second PNP triode
(PNP2),
4th resistance (R4) and the series connection of the 5th resistance (R5), its series connection point connect the drain electrode of the 4th NMOS tube (MN4), the 4th NMOS tube
(MN4) grid connects the second bias voltage (Vb2), its source electrode ground connection；Another termination clamper amplifier of 5th resistance (R5)
The output terminal of circuit, the base stage of the second PNP triode of another termination (PNP2) of the 4th resistance (R4), the second PNP triode
(PNP2) emitter connects the emitter of the first NPN triode (NPN1), its grounded collector；
The base stage sum aggregate electrode interconnection of first NPN triode (NPN1) and drain electrode and the 2nd NPN for connecting the 4th PMOS tube (MP4)
The base stage of triode (NPN2)；The grid of 4th PMOS tube (MP4) connects the first bias voltage (Vb1), its source electrode connects supply voltage；
The collector of second NPN triode (NPN2) connects supply voltage, its emitter connects the base stage of the 3rd NPN triode (NPN3)；
First capacitance (C2) is connected between base stage and the ground of the second NPN triode (NPN2).
2. the linear voltage-stabilizing circuit according to claim 1 with fast load transient response, it is characterised in that the pincers
Position operational amplifier circuit include the first NMOS tube (MN1), the second NMOS tube (MN2), the 3rd NMOS tube (MN3), source with NMOS tube (MN),
First PMOS tube (MP1), the second PMOS tube (MP2), compensating electric capacity (C1), first resistor (R1) and second resistance (R2),
The source electrode of first NMOS tube (MN1) and the second NMOS tube (MN2) interconnects and connects the drain electrode of the 3rd NMOS tube (MN3), the
Input terminal of the grid of one NMOS tube (MN1) as the clamper operational amplifier circuit, the grid connection second of the 3rd NMOS tube (MN3)
Bias voltage (Vb2)；
The grid leak short circuit of first PMOS tube (MP1) simultaneously connects the drain electrode of the first NMOS tube (MN1) and the grid of the second PMOS tube (MP2)
Pole, source connect the drain electrode of the second NMOS tube (MN2) and the second PMOS tube (MP2) with the grid of NMOS tube (MN) and pass through compensating electric capacity
(C1) it is grounded afterwards；
First resistor (R1) and second resistance (R2) series connection, its series connection point connect the grid of the second NMOS tube (MN2), first resistor
(R1) another termination source with NMOS tube (MN) source electrode and as the output terminal of the clamper operational amplifier circuit, second resistance (R2)
The other end and the 3rd NMOS tube (MN3) source electrode ground connection, the source electrode of the first PMOS tube (MP1) and the second PMOS tube (MP2) with
And source connects supply voltage with the drain electrode of NMOS tube (MN).
3. the linear voltage-stabilizing circuit according to claim 1 with fast load transient response, it is characterised in that described defeated
Go out capacitance (COUT) it is 100pF.
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| CN109116901B (en) * | 2018-10-31 | 2023-09-15 | 上海艾为电子技术股份有限公司 | Linear voltage stabilizing circuit and integrated circuit |
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| CN113970949B (en) * | 2021-12-27 | 2022-03-29 | 江苏长晶科技股份有限公司 | High-speed linear voltage stabilizer with quick response |
| CN114489213B (en) * | 2022-02-09 | 2023-03-10 | 广芯电子技术（上海）股份有限公司 | Linear voltage stabilizing circuit |
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| US8237418B1 (en) * | 2007-09-28 | 2012-08-07 | Cypress Semiconductor Corporation | Voltage regulator using front and back gate biasing voltages to output stage transistor |
| CN102789257A (en) * | 2012-08-31 | 2012-11-21 | 电子科技大学 | Low dropout regulator |
| CN202771296U (en) * | 2012-08-16 | 2013-03-06 | 成都锐成芯微科技有限责任公司 | Low static power consumption rapid transient response no- output capacitance low dropout regulator (LDO) circuit |
| CN103592989A (en) * | 2012-08-16 | 2014-02-19 | 成都锐成芯微科技有限责任公司 | Low quiescent dissipation rapid transient response non-output capacitance LDO (low drop out regulator) circuit |
| CN105630058A (en) * | 2016-03-23 | 2016-06-01 | 江南大学 | Improved on-chip linear voltage regulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7282902B2 (en) * | 2004-03-07 | 2007-10-16 | Faraday Technology Corp. | Voltage regulator apparatus |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8237418B1 (en) * | 2007-09-28 | 2012-08-07 | Cypress Semiconductor Corporation | Voltage regulator using front and back gate biasing voltages to output stage transistor |
| CN202771296U (en) * | 2012-08-16 | 2013-03-06 | 成都锐成芯微科技有限责任公司 | Low static power consumption rapid transient response no- output capacitance low dropout regulator (LDO) circuit |
| CN103592989A (en) * | 2012-08-16 | 2014-02-19 | 成都锐成芯微科技有限责任公司 | Low quiescent dissipation rapid transient response non-output capacitance LDO (low drop out regulator) circuit |
| CN102789257A (en) * | 2012-08-31 | 2012-11-21 | 电子科技大学 | Low dropout regulator |
| CN105630058A (en) * | 2016-03-23 | 2016-06-01 | 江南大学 | Improved on-chip linear voltage regulator |
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