CN104679088A - Low dropout linear regulator and frequency compensating circuit thereof - Google Patents
Low dropout linear regulator and frequency compensating circuit thereof Download PDFInfo
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- CN104679088A CN104679088A CN201310641528.2A CN201310641528A CN104679088A CN 104679088 A CN104679088 A CN 104679088A CN 201310641528 A CN201310641528 A CN 201310641528A CN 104679088 A CN104679088 A CN 104679088A
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Abstract
The invention belongs to the field of low dropout linear regulators, and provides a low dropout linear regulator and a frequency compensating circuit thereof. The low dropout linear regulator comprises an error amplifier with a folded cascode structure or a sleeve structure, wherein the frequency compensating circuit, based on a current buffer stage circuit and a cascode Miller's compensating circuit, further comprises a transconductance boosting circuit. The frequency compensating circuit takes advantage of the positive correlation property of a damping coefficient and common gate transistor transconductance, boosts the equivalent transconductance of a common gate transistor in the error amplifier via the feedback of the transconductance boosting circuit, increases the damping coefficient further, eliminates the complex poles that are possible to appear in the system, and then enhances the stability of the system.
Description
Technical field
The invention belongs to low pressure difference linear voltage regulator field, particularly relate to a kind of low pressure difference linear voltage regulator and frequency compensated circuit thereof.
Background technology
The low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) of low speed paper tape reader static power disspation is a kind of electric power management circuit be widely used in electronic product.As shown in Figure 1, the main circuit of LDO comprises error amplifier EA, Correctional tube, resistance-feedback network.The output voltage of LDO feeds back to the input end of error amplifier EA through resistance-feedback network, compared with reference voltage V ref by error amplifier EA, thus change the control signal of error amplifier EA output, and then the pressure drop of regulation output Correctional tube (or equiva lent impedance), make the output voltage that LDO keeps stable.
For the characteristic making LDO keep low voltage difference under large current load, Correctional tube generally adopts the PMOS of enormous size, and the large stray capacitance that large PMOS is brought significantly can reduce the stability of system.In addition, the output impedance of LDO changes with load current change, makes the stability of system also by the variable effect of load current.Like this, for meeting the stability requirement of LDO in full-load range, need to carry out frequency compensation to LDO.
Be directed to this, prior art provides a kind of cascade miller compensation mode with buffer stage, as shown in Figure 1.Under this kind of mode, between error amplifier EA and Correctional tube, add a buffer stage circuit, the low-frequency pole formed between error amplifier EA and the grid of Correctional tube to be isolated into the high frequency poles of two frequencies higher than unit gain frequency; Meanwhile, error amplifier EA adopts folded cascode configuration or tube-in-tube structure.Under folded cascode configuration, between the source node of the cascade device of error amplifier EA and LDO output node, connect cascade Miller's compensating circuit, utilize the limit splitting effect that the more traditional Miller effect of cascade miller compensation significantly promotes, realize improvement to frequency characteristic, particularly for the LDO system with bulky capacitor load.
But under the cascade miller compensation mode of this kind of band buffer stage, circuit can be too small and produce complex pole due to damping (Damping) coefficient in loop gain transition function denominator, thus cause system unstable.
Summary of the invention
The object of the embodiment of the present invention is the frequency compensated circuit providing a kind of low pressure difference linear voltage regulator, under being intended to solve the cascade miller compensation mode of existing band buffer stage, circuit due to ratio of damping too small and produce complex pole, cause the problem of system instability.
The embodiment of the present invention realizes like this, a kind of frequency compensated circuit of low pressure difference linear voltage regulator, the frequency compensated circuit of described low pressure difference linear voltage regulator comprises buffer stage circuit and cascade Miller's compensating circuit, the frequency compensated circuit of described low pressure difference linear voltage regulator also comprises: connect the mutual conductance in low pressure difference linear voltage regulator with common gate transistor in the error amplifier of folded cascode configuration and promote circuit, described mutual conductance promotes circuit and comprises: the tenth metal-oxide-semiconductor of N-type, 11 metal-oxide-semiconductor of N-type, 12 metal-oxide-semiconductor of P type, 3rd resistance and the 4th resistance,
The grid of described 12 metal-oxide-semiconductor connects a bias voltage, the source electrode of described 12 metal-oxide-semiconductor connects input voltage, the drain electrode of described 12 metal-oxide-semiconductor connects the drain electrode of described tenth metal-oxide-semiconductor by described 3rd resistance, and the drain electrode of described 11 metal-oxide-semiconductor is connected by described 4th resistance, the source ground of described tenth metal-oxide-semiconductor, the source ground of described 11 metal-oxide-semiconductor, the drain and gate of described tenth metal-oxide-semiconductor and the drain and gate of described 11 metal-oxide-semiconductor connect the described common gate transistor of described error amplifier.
Another object of the embodiment of the present invention is to provide a kind of low pressure difference linear voltage regulator, comprise error amplifier, Correctional tube, resistance-feedback network, described low pressure difference linear voltage regulator also comprises frequency compensated circuit, and described frequency compensated circuit is the frequency compensated circuit of low pressure difference linear voltage regulator as above.
The frequency compensated circuit of low pressure difference linear voltage regulator provided by the invention is the positive correlation utilizing ratio of damping gridistor mutual conductance together, the equivalent transconductance of common gate transistor in the feedback poppet error amplifier of circuit is promoted by mutual conductance, and then increase ratio of damping, the complex pole that may occur in elimination system, and then improve system stability.
Accompanying drawing explanation
Fig. 1 is the LDO circuit theory diagrams of the cascade miller compensation mode of the band buffer stage that prior art provides;
Fig. 2 is the circuit theory diagrams of the frequency compensated circuit of the low pressure difference linear voltage regulator that the embodiment of the present invention one provides;
Fig. 3 is the circuit diagram of Fig. 2;
Fig. 4 is the circuit theory diagrams of the frequency compensated circuit of the low pressure difference linear voltage regulator that the embodiment of the present invention two provides;
Fig. 5 is the circuit diagram of Fig. 4;
Fig. 6 is the circuit theory diagrams of the frequency compensated circuit of the low pressure difference linear voltage regulator that the embodiment of the present invention three provides;
Fig. 7 is the circuit diagram of Fig. 6.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
For prior art Problems existing, the present invention proposes a kind of frequency compensated circuit of low pressure difference linear voltage regulator.This circuit is the positive correlation utilizing ratio of damping gridistor mutual conductance together, is promoted the equivalent transconductance of common gate transistor in the feedback poppet error amplifier of circuit by mutual conductance, and then increases ratio of damping, the complex pole that may occur in elimination system.Implementation of the present invention is described in detail below in conjunction with embodiment:
embodiment one
The embodiment of the present invention one proposes a kind of frequency compensated circuit of low pressure difference linear voltage regulator, as shown in Figure 2, for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention one.
Specifically, the frequency compensated circuit of low pressure difference linear voltage regulator that the embodiment of the present invention one provides adopts the cascade miller compensation mode of band buffer stage to realize frequency compensation.Now, low pressure difference linear voltage regulator comprises: the error amplifier 1 of folded cascode configuration, and the negative input end of error amplifier 1 connects reference voltage V ref; Correctional tube 2, the input end of Correctional tube 2 connects input voltage vin, and the output terminal of Correctional tube 2 connects load; Resistance-feedback network 3, the input end of resistance-feedback network 3 connects the output terminal of Correctional tube 2, and the output terminal of resistance-feedback network 3 connects the positive input terminal of error amplifier 1.Then the frequency compensated circuit of this low pressure difference linear voltage regulator comprises: buffer stage circuit 4, and the input end of buffer stage circuit 4 connects the output terminal of error amplifier 1, and the output terminal of buffer stage circuit 4 connects the drive end of Correctional tube 2; Cascade Miller's compensating circuit 5, the input end of cascade Miller's compensating circuit 5 connects the output terminal of Correctional tube 2, and the output terminal of cascade Miller's compensating circuit 5 connects error amplifier 1.
For solving prior art Problems existing, the frequency compensated circuit of the low pressure difference linear voltage regulator that the embodiment of the present invention one provides also comprises: the mutual conductance connecting the common gate transistor of error amplifier 1 promotes circuit 6, for promoting the equivalent transconductance of common gate transistor in error amplifier 1, and then increase ratio of damping, the complex pole that may occur in elimination system, under solving the cascade miller compensation mode of band buffer stage, system damping coefficient is too small and produce the problem of complex pole, improves system stability.
Further, as shown in Figure 3, error amplifier 1 adopts dual input, single folded cascode configuration exported, and can comprise: the 5th metal-oxide-semiconductor M5 of the 4th metal-oxide-semiconductor M4, P type of the 3rd metal-oxide-semiconductor M3, P type of second metal-oxide-semiconductor M2, P type of first metal-oxide-semiconductor M1, P type of P type, the 6th metal-oxide-semiconductor M6 of N-type, the 7th metal-oxide-semiconductor M7 of N-type, the 8th metal-oxide-semiconductor M8 of N-type, the 9th metal-oxide-semiconductor M9 of N-type.
Wherein, the grid of the 3rd metal-oxide-semiconductor M3 connects a bias voltage, the source electrode of the 3rd metal-oxide-semiconductor M3 connects input voltage vin, the drain electrode of the 3rd metal-oxide-semiconductor M3 connects the source electrode of the first metal-oxide-semiconductor M1 and the source electrode of the second metal-oxide-semiconductor M2, the output terminal of the grid contact resistance feedback network 3 of the first metal-oxide-semiconductor M1, the grid of the second metal-oxide-semiconductor M2 connects reference voltage Vref, the grid of the 4th metal-oxide-semiconductor M4 connects the grid of the 5th metal-oxide-semiconductor M5, the source electrode of the 4th metal-oxide-semiconductor M4 is connected input voltage vin with the source electrode of the 5th metal-oxide-semiconductor M5, the drain electrode of the 4th metal-oxide-semiconductor M4 connects the drain electrode of the 6th metal-oxide-semiconductor M6 and the grid of the 4th metal-oxide-semiconductor M4, the drain electrode of the 5th metal-oxide-semiconductor M5 connects the drain electrode of the 7th metal-oxide-semiconductor M7, the source electrode of the 6th metal-oxide-semiconductor M6 connects the drain electrode of the 8th metal-oxide-semiconductor M8 and the drain electrode of the first metal-oxide-semiconductor M1, the source electrode of the 7th metal-oxide-semiconductor M7 connects the drain electrode of the 9th metal-oxide-semiconductor M9 and the drain electrode of the second metal-oxide-semiconductor M2, the source electrode of the 8th metal-oxide-semiconductor M8 and the source ground of the 9th metal-oxide-semiconductor M9, the grid of the 8th metal-oxide-semiconductor M8 connects grid and a bias voltage Vbias of the 9th metal-oxide-semiconductor M9, 6th metal-oxide-semiconductor M6 and the 7th metal-oxide-semiconductor M7 is the common gate transistor of error amplifier 1, and the grid of the 6th metal-oxide-semiconductor M6 is connected mutual conductance lifting circuit 6 with the grid of source electrode and the 7th metal-oxide-semiconductor M7 with source electrode, the drain electrode of the 5th metal-oxide-semiconductor M5 connects the input end of buffer stage circuit 4 as the output terminal of error amplifier 1.
Certainly, in practice, error amplifier 1 can be not limited to circuit structure shown in Fig. 3, and adopt telescoping structure or other can realize the structure of cascade miller compensation.
Further, as shown in Figure 3, mutual conductance lifting circuit 6 can comprise: the 12 metal-oxide-semiconductor M12, the 3rd resistance R3 of the tenth metal-oxide-semiconductor M10 of N-type, the 11 metal-oxide-semiconductor M11, P type of N-type and the 4th resistance R4.
Wherein, the grid of the 12 metal-oxide-semiconductor M12 connects a bias voltage, the source electrode of the 12 metal-oxide-semiconductor M12 connects input voltage vin, and the drain electrode of the 12 metal-oxide-semiconductor M12 connects the drain electrode of the tenth metal-oxide-semiconductor M10 by the 3rd resistance R3, and is connected the drain electrode of the 11 metal-oxide-semiconductor M11 by the 4th resistance R4; The source ground of the tenth metal-oxide-semiconductor M10, the source ground of the 11 metal-oxide-semiconductor M11, the drain and gate of the tenth metal-oxide-semiconductor M10 and the drain and gate of the 11 metal-oxide-semiconductor M11 connect the common gate transistor of error amplifier 1.Particularly, when error amplifier 1 adopt as shown in Figure 3 circuit structure time, the drain electrode of the tenth metal-oxide-semiconductor M10 connects the grid of the 6th metal-oxide-semiconductor M6, and the grid of the tenth metal-oxide-semiconductor M10 connects the source electrode of the 6th metal-oxide-semiconductor M6; The drain electrode of the 11 metal-oxide-semiconductor M11 connects the grid of the 7th metal-oxide-semiconductor M7, and the grid of the 11 metal-oxide-semiconductor M11 connects the source electrode of the 7th metal-oxide-semiconductor M7.
Promote in circuit 6 in the mutual conductance with this structure, the equivalent transconductance of the 6th metal-oxide-semiconductor M6 and the 7th metal-oxide-semiconductor M7 is improved 1+gm in theory respectively
m10r
3doubly and 1+gm
m11r
4doubly, wherein, gm
m10be the mutual conductance of the tenth metal-oxide-semiconductor M10, gm
m11be the mutual conductance of the 11 metal-oxide-semiconductor M11, R
3be the resistance of the 3rd resistance R3, R
4it is the resistance of the 4th resistance R4.
In practice, also by increasing the passage current of the tenth metal-oxide-semiconductor M10 and the 11 metal-oxide-semiconductor M11 and/or increasing the mode of width/length ratio of the tenth metal-oxide-semiconductor M10 and the 11 metal-oxide-semiconductor M11, to strengthen the effect that mutual conductance promotes further.
Further, as shown in Figure 3, Correctional tube 2 can be the 21 metal-oxide-semiconductor ML of P type, the grid of the 21 metal-oxide-semiconductor ML connects the output terminal of buffer stage circuit 4 as the drive end of Correctional tube 2, the source electrode of the 21 metal-oxide-semiconductor ML connects input voltage vin as the input end of Correctional tube 2, and the drain electrode of the 21 metal-oxide-semiconductor ML connects load, the input end of cascade Miller's compensating circuit 5 and the input end of resistance-feedback network 3 as the output terminal of Correctional tube 2.
Further, as shown in Figure 3, resistance-feedback network 3 can comprise the first resistance R1 and the second resistance R2.One end of first resistance R1 connects the output terminal of Correctional tube 2 as the input end of resistance-feedback network 3, the other end of the first resistance R1 connects the negative input end of error amplifier 1 as the output terminal of resistance-feedback network 3, and the other end of the first resistance R1 is simultaneously by the second resistance R2 ground connection.
Further, as shown in Figure 3, buffer stage circuit 4 can comprise: the 14 metal-oxide-semiconductor M14 of the 13 metal-oxide-semiconductor M13, P type of P type.
Wherein, the grid of the 13 metal-oxide-semiconductor M13 connects a bias voltage, the source electrode of the 13 metal-oxide-semiconductor M13 connects input voltage vin, the drain electrode of the 13 metal-oxide-semiconductor M13 connects the drive end of Correctional tube 2 as the output terminal of buffer stage circuit 4, the drain electrode of the 13 metal-oxide-semiconductor M13 connects the source electrode of the 14 metal-oxide-semiconductor M14 simultaneously, the grounded drain of the 14 metal-oxide-semiconductor M14, the grid of the 14 metal-oxide-semiconductor M14 connects the output terminal of error amplifier 1 as the input end of buffer stage circuit 4.
Further, as shown in Figure 3, cascade Miller's compensating circuit 5 can comprise building-out capacitor Cc, one end of building-out capacitor Cc connects the output terminal of Correctional tube 2 as the input end of cascade Miller's compensating circuit 5, and the other end of building-out capacitor Cc connects error amplifier 1 as the output terminal of cascade Miller's compensating circuit 5.Particularly, when error amplifier 1 adopt as shown in Figure 3 circuit structure time, the other end of building-out capacitor Cc connects the drain electrode of the 9th metal-oxide-semiconductor M9.
In addition, the frequency compensated circuit of low pressure difference linear voltage regulator that the embodiment of the present invention one provides also comprises: be connected to the load capacitance CL between the output terminal of Correctional tube 2 and ground.And namely substantially increase load capacitance CL, the frequency compensated circuit with the low pressure difference linear voltage regulator of aforementioned structure also can make system when the equivalent series resistance (ESR) not relying on load capacitance CL compensates, realize the full-load range high stability of similar one-pole system, and there is excellent transient response characteristic.
embodiment two
The embodiment of the present invention two proposes a kind of frequency compensated circuit of low pressure difference linear voltage regulator, as shown in Figure 4, for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention two.
Due in the cascade miller compensation mode of band buffer stage, the unit gain frequency of low pressure difference linear voltage regulator increases with the increase of load current, for ensureing that time dominant pole frequency is all the time higher than unit gain frequency, require that buffer stage circuit 4 must consume larger quiescent current, to ensure when large load current, buffer stage circuit 4 exports has lower equivalent resistance, can cause the high quiescent dissipation of low pressure difference linear voltage regulator like this.For head it off, different from embodiment one, the frequency compensated circuit of the low pressure difference linear voltage regulator that the embodiment of the present invention two provides also comprises: be connected to the electric current dynamic adjustments circuit 7 between the drive end of Correctional tube 2 and buffer stage circuit 4, for the electric current by dynamic adjustments buffer stage circuit 4, to realize the low quiescent current of the buffer stage circuit 4 when zero load or low load current, ensure the stability of the system when large load current simultaneously.
Further, as shown in Figure 5, electric current dynamic adjustments circuit 7 can comprise: the 16 metal-oxide-semiconductor M16, the 17 metal-oxide-semiconductor M17 of N-type of the 15 metal-oxide-semiconductor M15, P type of P type, the 19 metal-oxide-semiconductor M19 of the 18 metal-oxide-semiconductor M18, P type of N-type.
Wherein, the grid of the 15 metal-oxide-semiconductor M15 connects a bias voltage, the source electrode of the 15 metal-oxide-semiconductor M15 connects input voltage vin, the drain electrode of the 15 metal-oxide-semiconductor M15 connects the drain electrode of the 16 metal-oxide-semiconductor M16, the source electrode of the 16 metal-oxide-semiconductor M16 connects input voltage vin, the drain electrode of the 16 metal-oxide-semiconductor M16 connects the drain electrode of the 17 metal-oxide-semiconductor M17 simultaneously, the source ground of the 17 metal-oxide-semiconductor M17, the grid of the 17 metal-oxide-semiconductor M17 connects the drain electrode of the 17 metal-oxide-semiconductor M17 and the grid of the 18 metal-oxide-semiconductor M18, the source ground of the 18 metal-oxide-semiconductor M18, the drain electrode of the 18 metal-oxide-semiconductor M18 is connected buffer stage circuit 4 with the grid of the 16 metal-oxide-semiconductor M16, the source electrode of the 19 metal-oxide-semiconductor M19 connects input voltage vin, and the grid of the 19 metal-oxide-semiconductor M19 is connected buffer stage circuit 4 with drain electrode.Particularly, when buffer stage circuit 4 adopt as shown in Figure 3 circuit structure time, the drain electrode of the grid of the 16 metal-oxide-semiconductor M16, the grid of the 19 metal-oxide-semiconductor M19 and drain electrode connection the 13 metal-oxide-semiconductor M13, the drain electrode of the 18 metal-oxide-semiconductor M18 connects the drain electrode of the 14 metal-oxide-semiconductor M14.
In the embodiment of the present invention two, the electric current dynamic adjustments circuit 7 in Fig. 5 can when ensureing full load current low pressure difference linear voltage regulator stability prerequisite under, realize the low zero load quiescent dissipation of low pressure difference linear voltage regulator.Its principle is: the bias voltage of the grid of the 13 metal-oxide-semiconductor M13 is the quiescent current of buffer stage circuit 4 when being provided in zero load; The Dynamic Regulating Process of the quiescent current of buffer stage circuit 4 is, first followed the trail of by the 16 metal-oxide-semiconductor M16 proportional with the size of Correctional tube and the 19 change of metal-oxide-semiconductor M19 to load current, then regulate the electric current of buffer stage circuit 4 to realize by the current mirror that the 17 metal-oxide-semiconductor M17 and the 18 metal-oxide-semiconductor M18 forms.Like this, when large current load, the unity gain bandwidth of low pressure difference linear voltage regulator increases, and buffer stage electric current also increases, and ensure that equiva lent impedance less between the output terminal of buffer stage circuit 4 and the drive end of Correctional tube; And when load current reduces, the unity gain bandwidth of low pressure difference linear voltage regulator reduces, the electric current of buffer stage circuit 4 also reduces, thus ensure in full-load range, secondary dominant pole frequency, all the time higher than unity gain bandwidth, therefore also achieves the characteristic of low speed paper tape reader static power disspation while ensureing stability.
embodiment three
The embodiment of the present invention three proposes a kind of frequency compensated circuit of low pressure difference linear voltage regulator, as shown in Figure 6, for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention three.
Different from embodiment two, in embodiment three, in order on the basis not increasing buffer stage quiescent current consumption, the output equivalent impedance of further reduction buffer stage circuit 4, the frequency compensated circuit of this low pressure difference linear voltage regulator also can comprise: be connected to the buffer stage output impedance attenuator circuit 8 between the drive end of Correctional tube 2 and buffer stage circuit 4, for utilizing Shunt negative feedback to reduce the output equivalent impedance of buffer stage circuit 4.
Further, as shown in Figure 7, buffer stage output impedance attenuator circuit 8 can comprise the 20 metal-oxide-semiconductor M20 of N-type.The drain electrode of the 20 metal-oxide-semiconductor M20 connects the drive end of Correctional tube 2, the source ground of the 20 metal-oxide-semiconductor M20, and the grid of the 20 metal-oxide-semiconductor M20 connects buffer stage circuit 4.Particularly, when buffer stage circuit 4 has structure as shown in Figure 7, the grid of the 20 metal-oxide-semiconductor M20 connects the drain electrode of the 14 metal-oxide-semiconductor M14.
In addition, in the embodiment of the present invention three, the BJT pipe that the 20 metal-oxide-semiconductor M20 also can be N-type replaced.
In the embodiment of the present invention three, in Fig. 7, buffer stage output impedance attenuator circuit 8 is by the Shunt negative feedback to the output terminal of buffer stage circuit 4, realizes the significantly decay of the equivalent resistance of this output terminal.When load current increases, the drain voltage of the 18 metal-oxide-semiconductor M18 raises, and causes more electric current to flow through the 20 metal-oxide-semiconductor M20, therefore reduce further the output impedance of buffer stage circuit 4.
embodiment four
The embodiment of the present invention four proposes a kind of low pressure difference linear voltage regulator, comprise the frequency compensated circuit of error amplifier 1, Correctional tube 2, resistance-feedback network 3 and the low pressure difference linear voltage regulator as above described in embodiment one to embodiment three any embodiment, be not repeated herein.
In sum, the frequency compensated circuit of low pressure difference linear voltage regulator provided by the invention is the positive correlation utilizing ratio of damping gridistor mutual conductance together, the equivalent transconductance of common gate transistor in the feedback poppet error amplifier of circuit 6 is promoted by mutual conductance, and then increase ratio of damping, the complex pole that may occur in elimination system, and then improve system stability.Have again, the frequency compensated circuit of this low pressure difference linear voltage regulator also can utilize electric current dynamic adjustments circuit 7 to realize the dynamic adjustments of the electric current to buffer stage circuit 4, to realize the low quiescent current of the buffer stage circuit 4 when zero load or low load current, ensure the stability of the system when large load current simultaneously.Have again, the frequency compensated circuit of this low pressure difference linear voltage regulator also can utilize buffer stage output impedance attenuator circuit 8 to realize buffer stage circuit 4 under the condition not increasing quiescent current consumption, to the further reduction of output equivalent impedance, thus further ensure the stability of system.In addition, the present invention is under the effect of frequency compensated circuit, and the stability of LDO system does not rely on the ESR that load capacitance CL carries completely, and the transient response characteristic achieved very well, does not therefore need extra transient state intensifier circuit yet.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the frequency compensated circuit of a low pressure difference linear voltage regulator, it is characterized in that, the frequency compensated circuit of described low pressure difference linear voltage regulator comprises buffer stage circuit and cascade Miller's compensating circuit, the frequency compensated circuit of described low pressure difference linear voltage regulator also comprises: connect in low pressure difference linear voltage regulator the mutual conductance with common gate transistor in the error amplifier of folded cascode configuration and promote circuit, described mutual conductance promotes circuit and comprises: the 12 metal-oxide-semiconductor of the tenth metal-oxide-semiconductor of N-type, the 11 metal-oxide-semiconductor of N-type, P type, the 3rd resistance and the 4th resistance;
The grid of described 12 metal-oxide-semiconductor connects a bias voltage, the source electrode of described 12 metal-oxide-semiconductor connects input voltage, the drain electrode of described 12 metal-oxide-semiconductor connects the drain electrode of described tenth metal-oxide-semiconductor by described 3rd resistance, and the drain electrode of described 11 metal-oxide-semiconductor is connected by described 4th resistance, the source ground of described tenth metal-oxide-semiconductor, the source ground of described 11 metal-oxide-semiconductor, the drain and gate of described tenth metal-oxide-semiconductor and the drain and gate of described 11 metal-oxide-semiconductor connect the described common gate transistor of described error amplifier.
2. the frequency compensated circuit of low pressure difference linear voltage regulator as claimed in claim 1, it is characterized in that, described buffer stage circuit comprises: the 13 metal-oxide-semiconductor of P type, the 14 metal-oxide-semiconductor of P type;
The grid of described 13 metal-oxide-semiconductor connects a bias voltage, the source electrode of described 13 metal-oxide-semiconductor connects input voltage, the drain electrode of described 13 metal-oxide-semiconductor connects the drive end of Correctional tube in described low pressure difference linear voltage regulator as the output terminal of described buffer stage circuit, the drain electrode of described 13 metal-oxide-semiconductor connects the source electrode of described 14 metal-oxide-semiconductor simultaneously, the grounded drain of described 14 metal-oxide-semiconductor, the grid of described 14 metal-oxide-semiconductor connects the output terminal of described error amplifier as the input end of described buffer stage circuit.
3. the frequency compensated circuit of low pressure difference linear voltage regulator as claimed in claim 2, it is characterized in that, the frequency compensated circuit of described low pressure difference linear voltage regulator also comprises electric current dynamic adjustments circuit, and described electric current dynamic adjustments circuit comprises: the 15 metal-oxide-semiconductor of P type, the 16 metal-oxide-semiconductor of P type, the 17 metal-oxide-semiconductor of N-type, the 18 metal-oxide-semiconductor of N-type, the 19 metal-oxide-semiconductor of P type;
The grid of described 15 metal-oxide-semiconductor connects a bias voltage, the source electrode of described 15 metal-oxide-semiconductor connects input voltage, the drain electrode of described 15 metal-oxide-semiconductor connects the drain electrode of described 16 metal-oxide-semiconductor, the source electrode of described 16 metal-oxide-semiconductor connects input voltage, the drain electrode of described 16 metal-oxide-semiconductor connects the drain electrode of described 17 metal-oxide-semiconductor simultaneously, the source ground of described 17 metal-oxide-semiconductor, the grid of described 17 metal-oxide-semiconductor connects the drain electrode of described 17 metal-oxide-semiconductor and the grid of described 18 metal-oxide-semiconductor, the source ground of described 18 metal-oxide-semiconductor, the source electrode of described 19 metal-oxide-semiconductor connects input voltage, the grid of described 16 metal-oxide-semiconductor, the grid of described 19 metal-oxide-semiconductor is connected the drain electrode of described 13 metal-oxide-semiconductor with drain electrode, the drain electrode of described 18 metal-oxide-semiconductor connects the drain electrode of described 14 metal-oxide-semiconductor.
4. the frequency compensated circuit of low pressure difference linear voltage regulator as claimed in claim 2, it is characterized in that, the frequency compensated circuit of described low pressure difference linear voltage regulator also comprises buffer stage output impedance attenuator circuit, and described buffer stage output impedance attenuator circuit comprises the 20 metal-oxide-semiconductor of N-type;
The drain electrode of described 20 metal-oxide-semiconductor connects the drive end of described Correctional tube, the source ground of described 20 metal-oxide-semiconductor, and the grid of described 20 metal-oxide-semiconductor connects the drain electrode of described 14 metal-oxide-semiconductor.
5. the frequency compensated circuit of low pressure difference linear voltage regulator as claimed in claim 1, it is characterized in that, described cascade Miller's compensating circuit comprises building-out capacitor, one end of described building-out capacitor connects the output terminal of Correctional tube in described low pressure difference linear voltage regulator as the input end of described cascade Miller's compensating circuit, and the other end of described building-out capacitor connects described error amplifier as the output terminal of described cascade Miller's compensating circuit.
6. the frequency compensated circuit of low pressure difference linear voltage regulator as claimed in claim 1, it is characterized in that, the frequency compensated circuit of described low pressure difference linear voltage regulator also comprises the load capacitance between output terminal and ground being connected to Correctional tube in described low pressure difference linear voltage regulator.
7. a low pressure difference linear voltage regulator, comprise error amplifier, Correctional tube, resistance-feedback network, it is characterized in that, described low pressure difference linear voltage regulator also comprises frequency compensated circuit, and described frequency compensated circuit is the frequency compensated circuit of the low pressure difference linear voltage regulator as described in any one of claim 1 to 6.
8. low pressure difference linear voltage regulator as claimed in claim 7, it is characterized in that, described error amplifier comprises: the 5th metal-oxide-semiconductor of the 3rd metal-oxide-semiconductor of the first metal-oxide-semiconductor of P type, the second metal-oxide-semiconductor of P type, P type, the 4th metal-oxide-semiconductor of P type, P type, the 6th metal-oxide-semiconductor of N-type, the 7th metal-oxide-semiconductor of N-type, the 8th metal-oxide-semiconductor of N-type, the 9th metal-oxide-semiconductor of N-type;
The grid of described 3rd metal-oxide-semiconductor connects a bias voltage, the source electrode of described 3rd metal-oxide-semiconductor connects input voltage, the drain electrode of described 3rd metal-oxide-semiconductor connects the source electrode of described first metal-oxide-semiconductor and the source electrode of described second metal-oxide-semiconductor, the grid of described first metal-oxide-semiconductor connects the output terminal of described resistance-feedback network, the grid of described second metal-oxide-semiconductor connects reference voltage, the grid of described 4th metal-oxide-semiconductor connects the grid of described 5th metal-oxide-semiconductor, the source electrode of described 4th metal-oxide-semiconductor is connected input voltage with the source electrode of described 5th metal-oxide-semiconductor, the drain electrode of described 4th metal-oxide-semiconductor connects the drain electrode of described 6th metal-oxide-semiconductor and the grid of described 4th metal-oxide-semiconductor, the drain electrode of described 5th metal-oxide-semiconductor connects the drain electrode of described 7th metal-oxide-semiconductor, the source electrode of described 6th metal-oxide-semiconductor connects the drain electrode of described 8th metal-oxide-semiconductor and the drain electrode of described first metal-oxide-semiconductor, the source electrode of described 7th metal-oxide-semiconductor connects the drain electrode of described 9th metal-oxide-semiconductor and the drain electrode of described second metal-oxide-semiconductor, the source electrode of described 8th metal-oxide-semiconductor and the source ground of described 9th metal-oxide-semiconductor, the grid of described 8th metal-oxide-semiconductor connects grid and a bias voltage of described 9th metal-oxide-semiconductor, described 6th metal-oxide-semiconductor and described 7th metal-oxide-semiconductor are the described common gate transistor of described error amplifier, the drain electrode of described 5th metal-oxide-semiconductor connects the input end of described buffer stage circuit as the output terminal of described error amplifier,
The drain electrode of described tenth metal-oxide-semiconductor connects the grid of described 6th metal-oxide-semiconductor, the grid of described tenth metal-oxide-semiconductor connects the source electrode of described 6th metal-oxide-semiconductor, the drain electrode of described 11 metal-oxide-semiconductor connects the grid of described 7th metal-oxide-semiconductor, and the grid of described 11 metal-oxide-semiconductor connects the source electrode of described 7th metal-oxide-semiconductor.
9. low pressure difference linear voltage regulator as claimed in claim 7, it is characterized in that, described Correctional tube is the 21 metal-oxide-semiconductor of P type, the grid of described 21 metal-oxide-semiconductor connects the output terminal of described buffer stage circuit as the drive end of described Correctional tube, the source electrode of described 21 metal-oxide-semiconductor connects input voltage as the input end of described Correctional tube, and the drain electrode of described 21 metal-oxide-semiconductor connects load, the input end of described cascade Miller's compensating circuit and the input end of described resistance-feedback network as the output terminal of described Correctional tube.
10. low pressure difference linear voltage regulator as claimed in claim 7, it is characterized in that, described resistance-feedback network comprises the first resistance and the second resistance;
One end of described first resistance connects the output terminal of described Correctional tube as the input end of described resistance-feedback network, the other end of described first resistance connects the negative input end of described error amplifier as the output terminal of described resistance-feedback network, and the other end of described first resistance is simultaneously by described second resistance eutral grounding.
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