CN208351365U - A kind of low pressure difference linear voltage regulator of the outer capacitor of optional contact pin - Google Patents
A kind of low pressure difference linear voltage regulator of the outer capacitor of optional contact pin Download PDFInfo
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- CN208351365U CN208351365U CN201820806593.4U CN201820806593U CN208351365U CN 208351365 U CN208351365 U CN 208351365U CN 201820806593 U CN201820806593 U CN 201820806593U CN 208351365 U CN208351365 U CN 208351365U
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Abstract
The utility model discloses a kind of low pressure difference linear voltage regulators of capacitor outside optional contact pin, including error amplifier, power adjustment pipe, transmission gate switch, compensating electric capacity, first resistor and second resistance；First resistor is connected with second resistance；The non-inverting input terminal of error amplifier connects reference voltage, the sampled point between the reverse input end connection first resistor and second resistance of error amplifier, the grid of the output end connection power adjustment pipe of error amplifier；The source electrode of power adjustment pipe connects power supply, the drain electrode of power adjustment pipe is grounded by first resistor and second resistance, the input terminal of compensating electric capacity is connect by transmission gate switch with the source electrode of a transistor in error amplifier, the drain electrode of the output end connection power adjustment pipe of compensating electric capacity.Using the utility model, two kinds of operating modes can be realized by same circuit structure, structure is simple, easy to operate, strong flexibility.
Description
Technical field
The utility model relates to electronic circuit technology field more particularly to a kind of low pressure difference linearities of the outer capacitor of optional contact pin
Voltage-stablizer.
Background technique
With the development of on-chip integration system (SOC), the demand of integrated power supply Managed Solution is also continuously increased.Low voltage difference line
Property voltage-stablizer (Low Dropout Regulator, LDO) be used as a member therein, with its operating voltage is low, output noise is low,
The small in size and simple feature of application, is applied in portable electronic product more and more widely.LDO linear voltage regulator is suitable
For decompression transformation, for basic principle, LDO adjusts the output resistance of itself according to the situation of change of load, to protect
The voltage for demonstrate,proving output end is invariable.Since output end voltage and input terminal voltage pressure difference can accomplish very little, LDO is than general
Linear voltage regulator is more efficient.
Traditional LDO is typically necessary the capacitor in external 1 μ of μ F -10 F of output end to guarantee to stablize, this compensation side
The reliability of method depends on equivalent series resistance (Equivalent Series Resistance, ESR) value of the external capacitor
Size.This will improve the complexity and application cost of application, and this external stable capacitor can occupy certain pcb board sky
Between, so that the volume of product is restricted, but due to the presence of external bulky capacitor, the transient response performance of this LDO is good.
Using without capacitive LDO (Capless LDO), is then conducive to reduction chip area and cost, reduces for external
The chip pin number of capacitor.But the transient response characteristic due to lacking bulky capacitor outside piece, without capacitive LDO than traditional LDO
It is deteriorated, and stability also faces huge challenge.
In practical applications, demand of the different application environments to LDO is also different.Some application environments need more to pacify
Quiet power supply, some application environments can endure bigger noise.In order to reduce design cost and chip area, need to design one
Kind can external capacitor use and remove external capacitor as the composite LDO used without capacitive LDO as tradition LDO
To adapt to the requirement of varying environment.
Utility model content
It is easy to operate technical problem to be solved by the utility model is to provide a kind of structure is simple, strong flexibility
The low pressure difference linear voltage regulator of the outer capacitor of optional contact pin, can be realized two kinds of operating modes using same circuit structure.
In order to solve the above-mentioned technical problem, the utility model provide a kind of outer capacitor of optional contact pin low pressure difference linearity it is steady
Depressor, including error amplifier, power adjustment pipe, transmission gate switch, compensating electric capacity, first resistor and second resistance；Described
One resistance is connected with second resistance；The non-inverting input terminal of the error amplifier connects reference voltage, the error amplifier
Reverse input end connects the sampled point between first resistor and second resistance, and the output end of the error amplifier connects power tune
The grid of homogeneous tube；The source electrode of the power adjustment pipe connects power supply, and the drain electrode of the power adjustment pipe passes through first resistor and the
The input terminal of two resistance eutral groundings, the compensating electric capacity is connected by the source electrode of a transistor in transmission gate switch and error amplifier
It connects, the drain electrode of the output end connection power adjustment pipe of the compensating electric capacity.
As an improvement of the above scheme, the error amplifier includes Differential input circuit, common-source common-gate current mirror circuit
And common current mirror circuit, the common-source common-gate current mirror circuit on one side are connect with Differential input circuit, the other end and common electricity
Current mirror circuit connection.
As an improvement of the above scheme, the Differential input circuit includes the first difference transistor and the second differential crystal
Pipe；The drain electrode of first difference transistor and the drain electrode of the second difference transistor connect with common-source common-gate current mirror circuit respectively
It connects；The source electrode of first difference transistor and the source electrode of the second difference transistor connect to power supply respectively；First difference
The grid of transistor connects reference voltage, between the grid connection first resistor and second resistance of second difference transistor
Sampled point.
As an improvement of the above scheme, the common-source common-gate current mirror circuit includes the first common source transistors, the second common source
Transistor, third common source transistors, the 4th common source transistors, the 5th common source transistors, the 6th common source transistors, the 7th common source are brilliant
Body pipe and the 8th common source transistors；First common source transistors, the second common source transistors, the 5th common source transistors and the 6th are total
The grid of source transistor connects bias voltage；The third common source transistors, the 4th common source transistors, the 7th common source transistors and
The grid of 8th common source transistors connects Differential input circuit；The drain electrode connection Differential Input electricity of first common source transistors
Road, the drain electrode of the source electrode connection third common source transistors of first common source transistors, the source electrode of the third common source transistors
Ground connection；The drain electrode of second common source transistors connects common current mirror circuit, the source electrode connection of second common source transistors
The drain electrode of 4th common source transistors, the source electrode ground connection of the 4th common source transistors；The drain electrode of 5th common source transistors connects
Common current mirror circuit is connect, the source electrode of the 5th common source transistors connects the drain electrode of the 7th common source transistors and transmission gate is opened
It closes, the source electrode ground connection of the 7th common source transistors；The drain electrode of 6th common source transistors connects Differential input circuit, described
The source electrode of 6th common source transistors connects the drain electrode of the 8th common source transistors, the source electrode ground connection of the 8th common source transistors.
As an improvement of the above scheme, the common current mirror includes the first normal transistor and the second normal transistor；
The source electrode of first normal transistor connects power supply, and the drain electrode of first normal transistor is separately connected cascode current
The grid of mirror circuit and the first normal transistor；The source electrode of second normal transistor connects power supply, and described second is common brilliant
The drain electrode of body pipe is separately connected the grid of common-source common-gate current mirror circuit and power adjustment pipe, the grid of second normal transistor
Pole connects the grid of the first normal transistor.
As an improvement of the above scheme, the transmission gate switch includes the first transmission transistor and the second biography parallel with one another
Defeated transistor.
It as an improvement of the above scheme, further include biasing circuit, the biasing circuit includes the first biasing transistor, second
It biases transistor and third biases transistor；The source electrode of the first biasing transistor connects power supply, the first biasing crystal
The drain electrode of pipe connects bias current；The source electrode of the second biasing transistor connects power supply, the leakage of the second biasing transistor
Pole connects the drain electrode of third biasing transistor；The grid of the first biasing transistor and the grid of the second biasing transistor are mutual
Connect and be separately connected bias current and error amplifier；The grid of the third biasing transistor and the third bias crystal
The drain electrode of pipe connects and provides bias voltage, the source electrode ground connection of the third biasing transistor for error amplifier.
As an improvement of the above scheme, the low pressure difference linear voltage regulator of the outer capacitor of the optional contact pin further includes overcurrent protection
Circuit, one end of the current foldback circuit connect power supply, and the other end connects the output end of error amplifier.
As an improvement of the above scheme, the low pressure difference linear voltage regulator of the outer capacitor of the optional contact pin further includes output loading
Circuit, the output loading circuit include equivalent resistive load and on piece parasitic capacitance parallel with one another；It is described equivalent resistive negative
The drain electrode of one end connection power adjustment pipe of load, other end ground connection；One end of the on piece parasitic capacitance connects power adjustment pipe
Drain electrode, the other end ground connection.
As an improvement of the above scheme, the output loading circuit further includes the outer capacitor of piece and parasitic electricity being serially connected
Resistance, one end of described outer capacitor connect the drain electrode of power adjustment pipe, other end ground connection by dead resistance.
Implement the utility model, has the following beneficial effects:
The low pressure difference linear voltage regulator of the outer capacitor of the optional contact pin of the utility model can be realized using same circuit structure
Two kinds of operating modes, and the switching of operating mode is controlled by the switching signal of transmission gate switch, structure is simple and convenient to operate,
Strong flexibility.When transmission gate switch disconnects, the utility model can come using the outer capacitor of the piece of the external 1 μ μ of F -10 F as tradition LDO
It uses, the stability of circuit relies primarily on the dead resistance of the outer capacitor of piece to compensate at this time；When transmission gate switch is closed, this is practical
The novel piece dispatch from foreign news agency Rongcheng that removes is without capacitive LDO, and the stability of circuit is compensated by compensating electric capacity in piece at this time, this side
Formula can be adapted for different application environments, reduce design cost and chip area.
Detailed description of the invention
Circuit diagram when Fig. 1 is capacitor outside the utility model contact pin；
Frequency response Bode diagram when Fig. 2 is capacitor outside the utility model contact pin；
Fig. 3 is the utility model without the circuit diagram outside piece when capacitor；
Fig. 4 is the utility model without the frequency response Bode diagram outside piece when capacitor；
Transistor-level schematic when Fig. 5 is capacitor outside the utility model contact pin.
Specific embodiment
It is practical new to this below in conjunction with attached drawing to keep the purpose of this utility model, technical solution and advantage clearer
Type is described in further detail.Only this state, the utility model occur in the text or will occur upper and lower, left and right, it is preceding,
Afterwards, the orientation such as inside and outside word is not the specific restriction to the utility model only on the basis of the attached drawing of the utility model.
Referring to Fig. 1 and Fig. 3, Fig. 1 and Fig. 3 show the low pressure difference linear voltage regulator of the outer capacitor of the optional contact pin of the utility model
Circuit diagram comprising error amplifier EA, power adjustment pipe MP, transmission gate switch SW, compensating electric capacity CM, first resistor R1 and
Second resistance R2；Specifically, the first resistor R1 connects with second resistance R2；The non-inverting input terminal of the error amplifier EA
Reference voltage Vref is connected, the reverse input end of the error amplifier EA connects between first resistor R1 and second resistance R2
The output end of sampled point, the error amplifier EA connects power adjustment pipe MPGrid；The power adjustment pipe MPSource electrode connect
Meet power supply VCC, the power adjustment pipe MPDrain electrode be grounded by first resistor R1 and second resistance R2, the compensating electric capacity CM
Input terminal pass through transmission gate switch SWIt is connect with the source electrode of a transistor in error amplifier EA, the compensating electric capacity CMIt is defeated
Outlet connects power adjustment pipe MPDrain electrode.
When work, the output voltage of the utility model low pressure difference linear voltage regulator passes through first resistor R1 and second resistance R2
Divided, be then attached to the reverse input end of error amplifier EA, the voltage value that error amplifier EA obtains partial pressure with
The difference of reference voltage Vref amplifies, and the voltage that error is amplified is connected to power adjustment pipe MPGrid.Cause
The low pressure difference linear voltage regulator of this utility model forms a feedback loop, when low pressure difference linear voltage regulator is stablized, the
The partial pressure value of one resistance R1 and second resistance R2 is equal with reference voltage Vref, therefore available low pressure difference linear voltage regulator
Output voltage Vout, specifically, Vout=Vref × (1+R1/R2).
Further, the low pressure difference linear voltage regulator of the outer capacitor of the optional contact pin further includes output loading circuit, described defeated
Load circuit includes equivalent resistive load R parallel with one another outLAnd on piece parasitic capacitance CL；The equivalent resistive load RLOne
End connection power adjustment pipe MPDrain electrode, the other end ground connection；The on piece parasitic capacitance CLOne end connect power adjustment pipe MP's
Drain electrode, other end ground connection.
Correspondingly, the output loading circuit further includes the outer capacitor Cout and dead resistance R of piece being serially connectedESR, described
One end of the outer capacitor Cout of piece passes through dead resistance RESRConnect power adjustment pipe MPDrain electrode, the other end ground connection.
It should be noted that two kinds of operating modes can be realized using same circuit structure in the utility model, and by passing
Defeated door switch SWSwitching signal control the switching of operating mode.As transmission gate switch SWIt disconnects, the utility model can be external
The outer capacitor Cout of the piece of 1 μ of μ F -10 F comes as tradition LDO using the stability of circuit relies primarily on the outer capacitor Cout of piece at this time
Dead resistance RESRTo compensate；As transmission gate switch SWClosure, the utility model remove the outer capacitor Cout of piece and become without capacitive
LDO, the stability of circuit is by compensating electric capacity C in piece at this timeMIt compensates, this mode can be adapted for different applying ring
Design cost and chip area are reduced in border.
Below with reference to specific attached drawing, the utility model is further described in detail.
It as shown in Figures 1 and 2, need to be by transmission gate switch when low pressure difference linear voltage regulator needs capacitor Cout outside contact pin
SWIt disconnects, compensating electric capacity C at this timeMIt does not play a role.Due to the presence of capacitor Cout outside piece, dominant pole P1 is low voltage difference line
Property voltage-stablizer output end, secondary pole P2 be error amplifier EA output end.
P1=1/2 π RdsCout；
P2=1/2 π REACPMOS；
Wherein, Cout is the outer capacitor of the external piece of output end, RdsFor power adjustment pipe MPEquivalent resistance and output resistance are simultaneously
Connection, CPMOSFor power adjustment pipe MPParasitic gate capacitor.REAFor the output resistance of error amplifier EA, REA=ro12//
gm7ro7ro9。
Since there are the dead resistance R of equivalent series by capacitor Cout outside pieceESR, Left half-plane zero point a Z1, Z1 can be introduced
=1/2 π RESRCout。
As dead resistance RESRWhen sufficiently large, zero point Z1 will enter within unity gain bandwidth, participate in frequency compensation, support
Disappear time effect of pole P2.Outside external potsherd in the case where the 1 μ F of μ F -10 of capacitor, the utility model low pressure difference linearity pressure stabilizing
Device can achieve stabilization.If it is electrolytic capacitor (dead resistance R that outer contact pin dispatch from foreign news agency, which holds Cout,ESRIt is bigger), then the utility model is low
The phase margin of pressure difference linear voltage regulator can be higher.
It as shown in Figures 3 and 4, need to be by transmission gate switch S as the outer capacitor Cout of low pressure difference linear voltage regulator not contact pinW
Closure.Due to smaller (the on piece parasitic capacitance C of the load capacitance of low pressure difference linear voltage regulatorLBelow nF magnitude), dominant pole
P1 is in error amplifier EA output end, and secondary pole P2 is in low pressure difference linear voltage regulator output end.
Dominant pole P1=1/2 π REAgmpRdsCC；
Secondary pole P2=gm7gmpREA/2πCL；
Zero point Z1=gm7gmpREA/2πCC；
Due to compensating electric capacity CMPlay the role of dividing pole, keep dominant pole mobile to origin direction, make time pole to from
The direction of Kaiyuan point is mobile.From it is common it is miller-compensated unlike, compensating electric capacity CMIt is not connected directly across power adjustment pipe MP
Grid leak two-stage, but connect the source electrode of the output end and error amplifier EA cascade device in low pressure difference linear voltage regulator.
The advantages of this method is can to shift the Right-half-plant zero that miller compensation introduces onto very high frequency, will not influence low voltage difference
The stability of linear voltage regulator, and the numerical value of secondary pole P2 is also miller-compensated more much larger than common.Therefore this without capacitive
The bandwidth of LDO is more much larger than traditional LDO.
As shown in figure 5, the error amplifier EA includes Differential input circuit F, common-source common-gate current mirror circuit G and common
Current mirroring circuit E, described one end common-source common-gate current mirror circuit G are connect with Differential input circuit F, the other end and common current mirror
Circuit E connection.
Correspondingly, the compensating electric capacity CMInput terminal pass through transmission gate switch SWWith cascade in error amplifier EA
The source electrode of current mirroring circuit G connects.
It should be noted that from it is common it is miller-compensated unlike, compensating electric capacity C in the utility modelMThere is no straight
It connects and is connected across power adjustment pipe MPGrid leak two-stage, but connect the output end and error amplifier EA in low pressure difference linear voltage regulator
The source electrode of cascade device.The advantages of this method be can by miller compensation introduce Right-half-plant zero shift onto it is very high
Frequency will not influence the stability of low pressure difference linear voltage regulator, and the numerical value of secondary pole is also miller-compensated more much larger than common,
Therefore this bandwidth without capacitive LDO is more much larger than traditional LDO.
The Differential input circuit F includes the first difference transistor M1 and the second difference transistor M2；First difference
The drain electrode of transistor M1 and the drain electrode of the second difference transistor M2 are connect with common-source common-gate current mirror circuit G respectively；Described first
The source electrode of the source electrode of difference transistor M1 and the second difference transistor M2 are connect with power vd D respectively；First differential crystal
The grid of pipe M1 connects reference voltage Vref, the grid connection first resistor R1 and second resistance of the second difference transistor M
Sampled point between R2.
The common-source common-gate current mirror circuit G includes the first common source transistors M3, the second common source transistors M4, third common source
Transistor M5, the 4th common source transistors M6, the 5th common source transistors M7, the 6th common source transistors M8, the 7th common source transistors M9
And the 8th common source transistors M10；The first common source transistors M3, the second common source transistors M4, the 5th common source transistors M7 and
The grid of 6th common source transistors M8 connects bias voltage；The third common source transistors M5, the 4th common source transistors M6, the 7th
The grid of common source transistors M9 and the 8th common source transistors M10 connect Differential input circuit F；The first common source transistors M3's
The drain electrode of the source electrode connection third common source transistors M5 of drain electrode connection Differential input circuit F, the first common source transistors M3, institute
State the source electrode ground connection of third common source transistors M5；The drain electrode of the second common source transistors M4 connects common current mirror circuit E, institute
The source electrode for stating the second common source transistors M4 connects the drain electrode of the 4th common source transistors M6, the source electrode of the 4th common source transistors M6
Ground connection；The drain electrode of the 5th common source transistors M7 connects common current mirror circuit E, the source electrode of the 5th common source transistors M7
Connect drain electrode and the transmission gate switch S of the 7th common source transistors M9W, the source electrode ground connection of the 7th common source transistors M9；It is described
The drain electrode of 6th common source transistors M8 connects Differential input circuit F, and the source electrode connection the 8th of the 6th common source transistors M8 is total
The drain electrode of source transistor M10, the source electrode ground connection of the 8th common source transistors M10.Meanwhile the compensating electric capacity CMInput terminal
Pass through transmission gate switch SWIt is connect with the source electrode of the 5th common source transistors M7.
The common current mirror E includes the first normal transistor M11 and the second normal transistor M12；Described first is common
The source electrode of transistor M11 connects power vd D, and the drain electrode of the first normal transistor M11 is separately connected common-source common-gate current mirror
The grid of circuit G and the first normal transistor M11；The source electrode of the second normal transistor M12 connects power vd D, and described the
The drain electrode of two normal transistor M12 is separately connected common-source common-gate current mirror circuit G and power adjustment pipe MPGrid, described second
The grid of normal transistor M12 connects the grid of the first normal transistor M11.
The transmission gate switch SWIncluding the first transmission transistor SW and the second transmission transistor SWB parallel with one another.Control
Signal processed is external signal SW and SWB, SW and SWB inverted signal each other.
Further, the low pressure difference linear voltage regulator of the outer capacitor of the optional contact pin further includes biasing circuit H, the biased electrical
Road H includes that the first biasing transistor M15, the second biasing transistor M14 and third bias transistor M16；First biasing is brilliant
The source electrode of body pipe M15 connects power vd D, and the drain electrode of the first biasing transistor M15 connects bias current Ibias, described inclined
Setting electric current Ibias can be provided by current source circuit；It is described second biasing transistor M14 source electrode connect power vd D, described second
Bias the drain electrode of the drain electrode connection third biasing transistor M16 of transistor M14；It is described first biasing transistor M15 grid with
The grid of second biasing transistor M14 is connected with each other and is separately connected bias current Ibias and error amplifier EA；The third
The grid for biasing transistor M16 connect with the drain electrode of third biasing transistor M16 and provides biasing for error amplifier EA
Voltage, the source electrode ground connection of the third biasing transistor M16.
Correspondingly, the error amplifier EA further includes error transistor M13, and the source electrode of the error transistor M13 connects
Connect power vd D, the source electrode of the first difference transistor M1 and the source of the second difference transistor M2 in drain electrode connection Differential input circuit F
Pole, grid connect biasing circuit H.
In addition, the low pressure difference linear voltage regulator of the outer capacitor of the optional contact pin further includes current foldback circuit Q, the overcurrent
One end of circuit Q is protected to connect power vd D, the other end connects the output end of error amplifier EA.It can by current foldback circuit Q
It effectively prevent low pressure difference linear voltage regulator to provide excessive electric current to the external world and causes chip itself to burn.
From the foregoing, it will be observed that two kinds of operating modes can be realized using same circuit structure in the utility model, and by transmission gate
Switch SWSwitching signal control the switching of operating mode.As transmission gate switch SWIt disconnects, the utility model can be with external 1 μ
The outer capacitor of the piece of 10 μ F of F-comes as tradition LDO using the stability of circuit relies primarily on the dead resistance of the outer capacitor of piece at this time
To compensate；As transmission gate switch SWClosure, it is without capacitive LDO that the utility model, which removes piece dispatch from foreign news agency Rongcheng, and circuit is steady at this time
It is qualitative to rely on compensating electric capacity C in pieceMCompensate, this mode can be adapted for different application environment, reduce design cost and
Chip area.
The above is preferred embodiments of the present invention, it is noted that for the ordinary skill of the art
For personnel, without departing from the principle of this utility model, several improvements and modifications can also be made, these are improved and profit
Decorations are also considered as the protection scope of the utility model.
Claims (10)
1. a kind of low pressure difference linear voltage regulator of the outer capacitor of optional contact pin, which is characterized in that including error amplifier, power adjustment
Pipe, transmission gate switch, compensating electric capacity, first resistor and second resistance；
The first resistor is connected with second resistance；
The non-inverting input terminal of the error amplifier connects reference voltage, the reverse input end connection first of the error amplifier
Sampled point between resistance and second resistance, the grid of the output end connection power adjustment pipe of the error amplifier；
The source electrode of the power adjustment pipe connects power supply, and the drain electrode of the power adjustment pipe is connect by first resistor and second resistance
Ground；
The input terminal of the compensating electric capacity is connect by transmission gate switch with error amplifier, and the output end of the compensating electric capacity connects
Connect the drain electrode of power adjustment pipe.
2. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as described in claim 1, which is characterized in that the error is put
Big device includes Differential input circuit, common-source common-gate current mirror circuit and common current mirror circuit, the common-source common-gate current mirror electricity
Road one end is connect with Differential input circuit, and the other end is connect with common current mirror circuit.
3. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as claimed in claim 2, which is characterized in that the difference is defeated
Entering circuit includes the first difference transistor and the second difference transistor；
The drain electrode of first difference transistor and the drain electrode of the second difference transistor connect with common-source common-gate current mirror circuit respectively
It connects；
The source electrode of first difference transistor and the source electrode of the second difference transistor connect to power supply respectively；
The grid of first difference transistor connects reference voltage, and the grid of second difference transistor connects first resistor
Sampled point between second resistance.
4. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as claimed in claim 2, which is characterized in that the common source is total
Cascode current mirror circuit include the first common source transistors, the second common source transistors, third common source transistors, the 4th common source transistors,
5th common source transistors, the 6th common source transistors, the 7th common source transistors and the 8th common source transistors；
The grid company of first common source transistors, the second common source transistors, the 5th common source transistors and the 6th common source transistors
Connect bias voltage；
The grid company of the third common source transistors, the 4th common source transistors, the 7th common source transistors and the 8th common source transistors
Connect Differential input circuit；
The drain electrode of first common source transistors connects Differential input circuit, and the source electrode of first common source transistors connects third
The drain electrode of common source transistors, the source electrode ground connection of the third common source transistors；
The drain electrodes of second common source transistors connects common current mirror circuit, the source electrode connection of second common source transistors the
The drain electrode of four common source transistors, the source electrode ground connection of the 4th common source transistors；
The drain electrodes of 5th common source transistors connects common current mirror circuit, the source electrode connection of the 5th common source transistors the
The drain electrode of seven common source transistors and transmission gate switch, the source electrode ground connection of the 7th common source transistors；
The drain electrode of 6th common source transistors connects Differential input circuit, the source electrode connection the 8th of the 6th common source transistors
The drain electrode of common source transistors, the source electrode ground connection of the 8th common source transistors.
5. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as claimed in claim 2, which is characterized in that the common electricity
Flowing mirror includes the first normal transistor and the second normal transistor；
The source electrode of first normal transistor connects power supply, and the drain electrode of first normal transistor is separately connected cascade
The grid of current mirroring circuit and the first normal transistor；
The source electrode of second normal transistor connects power supply, and the drain electrode of second normal transistor is separately connected cascade
The grid of current mirroring circuit and power adjustment pipe, the grid of second normal transistor connect the grid of the first normal transistor
Pole.
6. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as described in claim 1, which is characterized in that the transmission gate
Switch includes the first transmission transistor and the second transmission transistor parallel with one another.
7. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as described in claim 1, which is characterized in that further include biasing
Circuit, the biasing circuit include that the first biasing transistor, the second biasing transistor and third bias transistor；
The source electrode of the first biasing transistor connects power supply, and the drain electrode of the first biasing transistor connects bias current；
The source electrode of the second biasing transistor connects power supply, and the drain electrode connection third of the second biasing transistor biases crystal
The drain electrode of pipe；
The grid of the grid of the first biasing transistor and the second biasing transistor is connected with each other and is separately connected bias current
And error amplifier；
The grid of the third biasing transistor connect with the drain electrode of third biasing transistor and provides for error amplifier
Bias voltage, the source electrode ground connection of the third biasing transistor.
8. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as described in claim 1, which is characterized in that further include overcurrent
Circuit is protected, one end of the current foldback circuit connects power supply, and the other end connects the output end of error amplifier.
9. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as described in claim 1, which is characterized in that further include output
Load circuit, the output loading circuit include equivalent resistive load and on piece parasitic capacitance parallel with one another；
The drain electrode of one end connection power adjustment pipe of the equivalent resistive load, other end ground connection；
The drain electrode of one end connection power adjustment pipe of the on piece parasitic capacitance, other end ground connection.
10. the low pressure difference linear voltage regulator of the outer capacitor of optional contact pin as claimed in claim 9, which is characterized in that the output
Load circuit further includes that the outer capacitor of piece being serially connected and dead resistance, one end of described outer capacitor are connected by dead resistance
The drain electrode of power adjustment pipe, other end ground connection.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108445959A (en) * | 2018-05-28 | 2018-08-24 | 佛山华芯微特科技有限公司 | A kind of low pressure difference linear voltage regulator of the outer capacitance of optional contact pin |
| CN109947167A (en) * | 2019-03-14 | 2019-06-28 | 上海奥令科电子科技有限公司 | A kind of negative pressure linear voltage regulator |
| CN114375432A (en) * | 2019-11-28 | 2022-04-19 | 深圳市汇顶科技股份有限公司 | Voltage stabilizer, image sensor and method |
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2018
- 2018-05-28 CN CN201820806593.4U patent/CN208351365U/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108445959A (en) * | 2018-05-28 | 2018-08-24 | 佛山华芯微特科技有限公司 | A kind of low pressure difference linear voltage regulator of the outer capacitance of optional contact pin |
| CN109947167A (en) * | 2019-03-14 | 2019-06-28 | 上海奥令科电子科技有限公司 | A kind of negative pressure linear voltage regulator |
| CN114375432A (en) * | 2019-11-28 | 2022-04-19 | 深圳市汇顶科技股份有限公司 | Voltage stabilizer, image sensor and method |
| CN114375432B (en) * | 2019-11-28 | 2024-01-26 | 深圳市汇顶科技股份有限公司 | Voltage stabilizer, image sensor and method |
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