CN108445959B - Low-dropout linear voltage regulator with selectable tab external capacitance - Google Patents
Low-dropout linear voltage regulator with selectable tab external capacitance Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The invention discloses a low-dropout linear voltage regulator with an external capacitor with a selectable tab, which comprises an error amplifier, a power adjusting tube, a transmission gate switch, a compensation capacitor, a first resistor and a second resistor, wherein the error amplifier is connected with the power adjusting tube; the first resistor is connected in series with the second resistor; the non-inverting input end of the error amplifier is connected with the reference voltage, the inverting input end of the error amplifier is connected with a sampling point between the first resistor and the second resistor, and the output end of the error amplifier is connected with the grid electrode of the power adjusting tube; the source electrode of the power adjusting tube is connected with a power supply, the drain electrode of the power adjusting tube is grounded through the first resistor and the second resistor, the input end of the compensation capacitor is connected with the source electrode of a transistor in the error amplifier through the transmission gate switch, and the output end of the compensation capacitor is connected with the drain electrode of the power adjusting tube. By adopting the invention, two working modes can be realized through the same circuit structure, and the invention has the advantages of simple structure, convenient operation and strong flexibility.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a low-dropout linear voltage regulator with an external capacitor of a selectable tab.
Background
With the development of integrated Systems On Chip (SOC), the need for integrated power management schemes is increasing. As one of the components, a low dropout linear regulator (Low Dropout Regulator, LDO) is increasingly used in portable electronic products due to its low operating voltage, low output noise, small size and simple application. The LDO linear voltage stabilizer is suitable for buck conversion, and in terms of basic principle, the LDO adjusts the output resistance of the LDO according to the change condition of a load, so that the voltage of an output end is ensured to be constant. Because the voltage difference between the output end voltage and the input end voltage can be small, the LDO has higher efficiency than a common linear voltage stabilizer.
The conventional LDO generally needs to connect a capacitor of 1 μf-10 μf to the output terminal to ensure stability, and the reliability of the compensation method depends on the value of the Equivalent series resistance (Equivalent SERIES RESISTANCE, ESR) of the external capacitor. The complexity and the application cost of the application are improved, and the external stable capacitor occupies a certain PCB space, so that the volume of a product is limited, but the transient response performance of the LDO is good due to the existence of the external large capacitor.
The adoption of the capacitor-free LDO (Capless LDO) is beneficial to reducing the area and cost of the chip and reducing the number of pins of the chip for externally connecting the capacitor. However, due to the lack of off-chip large capacitance, the transient response characteristics of the capacitance-free LDO are worse than those of the conventional LDO, and stability is also a great challenge.
In practical applications, the LDO requirements for different application environments are also different. Some applications require a quieter power supply and some applications may tolerate greater noise. In order to reduce the design cost and the chip area, the design of the multiplexing LDO which can be used as a traditional LDO and can be used as a capacitance-free LDO without the external capacitor is needed to meet the requirements of different environments.
Disclosure of Invention
The invention aims to solve the technical problem of providing the low-dropout linear voltage regulator with simple structure, convenient operation and strong flexibility, which can select the external capacitance of the tab, and can realize two working modes by using the same circuit structure.
In order to solve the technical problem, the invention provides a low-dropout linear voltage regulator with an external capacitor with a selectable tab, which comprises an error amplifier, a power adjusting tube, a transmission gate switch, a compensation capacitor, a first resistor and a second resistor; the first resistor is connected with the second resistor in series; the non-inverting input end of the error amplifier is connected with a reference voltage, the inverting input end of the error amplifier is connected with a sampling point between the first resistor and the second resistor, and the output end of the error amplifier is connected with the grid electrode of the power adjusting tube; the source electrode of the power adjusting tube is connected with a power supply, the drain electrode of the power adjusting tube is grounded through a first resistor and a second resistor, the input end of the compensation capacitor is connected with the source electrode of a transistor in the error amplifier through a transmission gate switch, and the output end of the compensation capacitor is connected with the drain electrode of the power adjusting tube.
As an improvement of the scheme, the error amplifier comprises a differential input circuit, a cascode current mirror circuit and a common current mirror circuit, wherein one end of the cascode current mirror circuit is connected with the differential input circuit, and the other end of the cascode current mirror circuit is connected with the common current mirror circuit.
As an improvement of the above-mentioned scheme, the differential input circuit includes a first differential transistor and a second differential transistor; the drain electrode of the first differential transistor and the drain electrode of the second differential transistor are respectively connected with a cascode current mirror circuit; the source electrode of the first differential transistor and the source electrode of the second differential transistor are respectively connected with a power supply; and the grid electrode of the first differential transistor is connected with a reference voltage, and the grid electrode of the second differential transistor is connected with a sampling point between the first resistor and the second resistor.
As an improvement of the above solution, the cascode current mirror circuit includes a first cascode transistor, a second cascode transistor, a third cascode transistor, a fourth cascode transistor, a fifth cascode transistor, a sixth cascode transistor, a seventh cascode transistor, and an eighth cascode transistor; the gates of the first common-source transistor, the second common-source transistor, the fifth common-source transistor and the sixth common-source transistor are connected with bias voltages; the gates of the third common-source transistor, the fourth common-source transistor, the seventh common-source transistor and the eighth common-source transistor are connected with a differential input circuit; the drain electrode of the first common-source transistor is connected with the differential input circuit, the source electrode of the first common-source transistor is connected with the drain electrode of a third common-source transistor, and the source electrode of the third common-source transistor is grounded; the drain electrode of the second common source transistor is connected with the common current mirror circuit, the source electrode of the second common source transistor is connected with the drain electrode of the fourth common source transistor, and the source electrode of the fourth common source transistor is grounded; the drain electrode of the fifth common source transistor is connected with the common current mirror circuit, the source electrode of the fifth common source transistor is connected with the drain electrode of the seventh common source transistor and the transmission gate switch, and the source electrode of the seventh common source transistor is grounded; the drain electrode of the sixth common source transistor is connected with the differential input circuit, the source electrode of the sixth common source transistor is connected with the drain electrode of the eighth common source transistor, and the source electrode of the eighth common source transistor is grounded.
As an improvement of the above scheme, the common current mirror includes a first common transistor and a second common transistor; the source electrode of the first common transistor is connected with a power supply, and the drain electrode of the first common transistor is respectively connected with the cascode current mirror circuit and the grid electrode of the first common transistor; the source electrode of the second common transistor is connected with a power supply, the drain electrode of the second common transistor is respectively connected with the grid electrodes of the common-source common-grid current mirror circuit and the power adjusting tube, and the grid electrode of the second common transistor is connected with the grid electrode of the first common transistor.
As an improvement of the above scheme, the pass gate switch includes a first pass transistor and a second pass transistor connected in parallel.
As an improvement of the scheme, the circuit further comprises a bias circuit, wherein the bias circuit comprises a first bias transistor, a second bias transistor and a third bias transistor; the source electrode of the first bias transistor is connected with a power supply, and the drain electrode of the first bias transistor is connected with bias current; the source electrode of the second bias transistor is connected with a power supply, and the drain electrode of the second bias transistor is connected with the drain electrode of the third bias transistor; the grid electrode of the first bias transistor is connected with the grid electrode of the second bias transistor and is respectively connected with bias current and an error amplifier; the grid electrode of the third bias transistor is connected with the drain electrode of the third bias transistor and provides bias voltage for the error amplifier, and the source electrode of the third bias transistor is grounded.
As an improvement of the scheme, the low dropout linear voltage regulator with the optional tab external capacitor further comprises an overcurrent protection circuit, wherein one end of the overcurrent protection circuit is connected with a power supply, and the other end of the overcurrent protection circuit is connected with the output end of the error amplifier.
As an improvement of the scheme, the low dropout linear voltage regulator with the selectable tab external capacitance further comprises an output load circuit, wherein the output load circuit comprises an equivalent resistive load and an on-chip parasitic capacitance which are connected in parallel; one end of the equivalent resistive load is connected with the drain electrode of the power adjusting tube, and the other end of the equivalent resistive load is grounded; one end of the on-chip parasitic capacitor is connected with the drain electrode of the power adjusting tube, and the other end of the on-chip parasitic capacitor is grounded.
As an improvement of the scheme, the output load circuit further comprises an off-chip capacitor and a parasitic resistor which are connected in series, one end of the off-chip capacitor is connected with the drain electrode of the power adjusting tube through the parasitic resistor, and the other end of the off-chip capacitor is grounded.
The implementation of the invention has the following beneficial effects:
The low-dropout linear voltage regulator with the tab-selectable external capacitor can realize two working modes by using the same circuit structure, and the switching of the working modes is controlled by the switching signal of the transmission gate switch, so that the low-dropout linear voltage regulator has the advantages of simple structure, convenience in operation and strong flexibility. When the transmission gate switch is disconnected, the invention can be externally connected with an off-chip capacitor of 1 mu F-10 mu F to be used as a traditional LDO, and the stability of the circuit is mainly compensated by the parasitic resistance of the off-chip capacitor; when the transmission gate switch is closed, the off-chip capacitor is removed to form the non-capacitance LDO, and the stability of the circuit is compensated by the on-chip compensation capacitor, so that the method can be suitable for different application environments, and the design cost and the chip area are reduced.
Drawings
FIG. 1 is a circuit diagram of an external capacitor of the present invention;
FIG. 2 is a diagram of the frequency response Boud of the present invention when the capacitance is external to the tab;
FIG. 3 is a circuit diagram of the invention without an off-chip capacitor;
FIG. 4 is a diagram of the frequency response Boud of the present invention without an off-chip capacitor;
fig. 5 is a circuit diagram of a transistor stage in the case of the extra-tab capacitor of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It is only stated that the terms of orientation such as up, down, left, right, front, back, inner, outer, etc. used in this document or the imminent present invention, are used only with reference to the drawings of the present invention, and are not meant to be limiting in any way.
Referring to fig. 1 and 3, fig. 1 and 3 show a circuit diagram of a low dropout linear regulator of an external capacitor with optional tabs according to the present invention, which includes an error amplifier EA, a power regulator M P, a transmission gate switch S W, a compensation capacitor C M, a first resistor R1 and a second resistor R2; specifically, the first resistor R1 is connected in series with the second resistor R2; the non-inverting input end of the error amplifier EA is connected with a reference voltage Vref, the inverting input end of the error amplifier EA is connected with a sampling point between the first resistor R1 and the second resistor R2, and the output end of the error amplifier EA is connected with the grid electrode of the power adjusting tube M P; the source of the power adjustment tube M P is connected to the power supply VCC, the drain of the power adjustment tube M P is grounded through the first resistor R1 and the second resistor R2, the input of the compensation capacitor C M is connected to the source of a transistor in the error amplifier EA through the transmission gate switch S W, and the output of the compensation capacitor C M is connected to the drain of the power adjustment tube M P.
When the low dropout linear regulator disclosed by the invention works, the output voltage of the low dropout linear regulator is divided by the first resistor R1 and the second resistor R2 and then is connected to the reverse input end of the error amplifier EA, the error amplifier EA amplifies the difference value between the voltage value obtained by the division and the reference voltage Vref, and the voltage obtained by the error amplification is connected to the grid electrode of the power adjusting tube M P. Therefore, the low dropout linear regulator of the present invention forms a negative feedback loop, and when the low dropout linear regulator is stable, the voltage division value of the first resistor R1 and the second resistor R2 is equal to the reference voltage Vref, so that the output voltage Vout of the low dropout linear regulator, specifically vout=vref× (1+r1/R2) can be obtained.
Further, the low dropout linear voltage regulator with the selectable tab external capacitance further comprises an output load circuit, wherein the output load circuit comprises an equivalent resistive load R L and an on-chip parasitic capacitance C L which are connected in parallel; one end of the equivalent resistive load R L is connected with the drain electrode of the power adjusting tube M P, and the other end of the equivalent resistive load R L is grounded; one end of the on-chip parasitic capacitor C L is connected with the drain electrode of the power adjusting tube M P, and the other end of the on-chip parasitic capacitor C L is grounded.
Correspondingly, the output load circuit further comprises an off-chip capacitor Cout and a parasitic resistor R ESR which are connected in series, wherein one end of the off-chip capacitor Cout is connected with the drain electrode of the power adjusting tube M P through the parasitic resistor R ESR, and the other end of the off-chip capacitor Cout is grounded.
It should be noted that, the present invention can realize two operation modes by using the same circuit structure, and the switching signal of the transmission gate switch S W controls the switching of the operation modes. When the transmission gate switch S W is disconnected, the invention can be externally connected with an off-chip capacitor Cout of 1 mu F-10 mu F to be used as a traditional LDO, and the stability of the circuit is mainly compensated by the parasitic resistance R ESR of the off-chip capacitor Cout; when the transmission gate switch S W is closed, the off-chip capacitor Cout is removed to form the capacitance-free LDO, and the stability of the circuit is compensated by the on-chip compensation capacitor C M, so that the method can be suitable for different application environments, and the design cost and the chip area are reduced.
The invention is described in further detail below with reference to the specific drawings.
As shown in fig. 1 and 2, when the low dropout linear regulator needs the external capacitor Cout, the transmission gate switch S W needs to be turned off, and the compensation capacitor C M does not function. Because of the off-chip capacitor Cout, the primary pole P1 is the output of the low dropout linear regulator, and the secondary pole P2 is the output of the error amplifier EA.
P1＝1/2πRdsCout；
P2＝1/2πREACPMOS；
Wherein Cout is an off-chip capacitor with an external output end, R ds is an equivalent resistor of the power adjusting tube M P and an output resistor are connected in parallel, and C PMOS is a gate parasitic capacitor of the power adjusting tube M P. R EA is the output resistance of the error amplifier EA, R EA＝ro12//gm7ro7ro9.
Since the off-chip capacitor Cout has an equivalent series parasitic resistance R ESR, a left half-plane zero Z1, z1=1/2 pi R ESR Cout is introduced.
When the parasitic resistance R ESR is large enough, the zero Z1 will enter the unity gain bandwidth, participate in frequency compensation, and cancel the effect of the secondary pole P2. Under the condition of 1 mu F-10 mu F of external ceramic chip external capacitor, the low-dropout linear voltage regulator can achieve stability. If the external off-chip capacitor Cout is an electrolytic capacitor (parasitic resistance R ESR is larger), the phase margin of the low dropout linear regulator of the present invention is higher.
As shown in fig. 3 and 4, when the low dropout linear regulator does not have the external capacitor Cout, the pass gate switch S W is closed. Because the load capacitance of the low dropout linear voltage regulator is smaller (the on-chip parasitic capacitance C L is lower than the nF magnitude), the main pole point P1 is at the output end of the error amplifier EA, and the secondary pole point P2 is at the output end of the low dropout linear voltage regulator.
The dominant pole p1=1/2 pi R EAgmpRdsCC;
Secondary pole p2=g m7gmpREA/2πCL;
zero z1=g m7gmpREA/2πCC;
Since the compensation capacitor C M plays a role of splitting a pole, the primary pole is moved toward the origin, and the secondary pole is moved away from the origin. Unlike the common miller compensation, the compensation capacitor C M is not directly connected across the gate-drain two stages of the power regulator M P, but is connected to the output terminal of the low dropout linear regulator and the source of the error amplifier EA cascode device. The method has the advantages that the right half-plane zero point introduced by the Miller compensation can be pushed to a very high frequency, the stability of the low dropout linear voltage stabilizer is not affected, and the value of the secondary pole P2 is much larger than that of the common Miller compensation. Therefore, the bandwidth of the capacitance-free LDO is much larger than that of the traditional LDO.
As shown in fig. 5, the error amplifier EA includes a differential input circuit F, a cascode current mirror circuit G, and a common current mirror circuit E, where one end of the cascode current mirror circuit G is connected to the differential input circuit F, and the other end is connected to the common current mirror circuit E.
Correspondingly, the input end of the compensation capacitor C M is connected with the source electrode of the cascode current mirror circuit G in the error amplifier EA through a transmission gate switch S W.
It should be noted that, unlike the common miller compensation, the compensation capacitor C M in the present invention is not directly connected across the gate-drain two stages of the power regulator M P, but is connected to the output terminal of the low dropout linear regulator and the source of the error amplifier EA cascode device. The method has the advantages that the right half-plane zero point introduced by Miller compensation can be pushed to a very high frequency, the stability of the low-dropout linear voltage regulator is not affected, and the value of the secondary pole is much larger than that of the common Miller compensation, so that the bandwidth of the capacitance-free LDO is much larger than that of the traditional LDO.
The differential input circuit F comprises a first differential transistor M1 and a second differential transistor M2; the drain electrode of the first differential transistor M1 and the drain electrode of the second differential transistor M2 are respectively connected with a cascode current mirror circuit G; the source of the first differential transistor M1 and the source of the second differential transistor M2 are respectively connected with a power supply VDD; the gate of the first differential transistor M1 is connected to the reference voltage Vref, and the gate of the second differential transistor M is connected to a sampling point between the first resistor R1 and the second resistor R2.
The cascode current mirror circuit G comprises a first common-source transistor M3, a second common-source transistor M4, a third common-source transistor M5, a fourth common-source transistor M6, a fifth common-source transistor M7, a sixth common-source transistor M8, a seventh common-source transistor M9 and an eighth common-source transistor M10; the gates of the first common-source transistor M3, the second common-source transistor M4, the fifth common-source transistor M7 and the sixth common-source transistor M8 are connected with bias voltages; the gates of the third common-source transistor M5, the fourth common-source transistor M6, the seventh common-source transistor M9 and the eighth common-source transistor M10 are connected with the differential input circuit F; the drain electrode of the first common-source transistor M3 is connected with the differential input circuit F, the source electrode of the first common-source transistor M3 is connected with the drain electrode of the third common-source transistor M5, and the source electrode of the third common-source transistor M5 is grounded; the drain electrode of the second common-source transistor M4 is connected with the common current mirror circuit E, the source electrode of the second common-source transistor M4 is connected with the drain electrode of the fourth common-source transistor M6, and the source electrode of the fourth common-source transistor M6 is grounded; the drain electrode of the fifth common-source transistor M7 is connected to the common current mirror circuit E, the source electrode of the fifth common-source transistor M7 is connected to the drain electrode of the seventh common-source transistor M9 and the transmission gate switch S W, and the source electrode of the seventh common-source transistor M9 is grounded; the drain electrode of the sixth common-source transistor M8 is connected to the differential input circuit F, the source electrode of the sixth common-source transistor M8 is connected to the drain electrode of the eighth common-source transistor M10, and the source electrode of the eighth common-source transistor M10 is grounded. Meanwhile, the input end of the compensation capacitor C M is connected to the source of the fifth common-source transistor M7 through the transmission gate switch S W.
The common current mirror E comprises a first common transistor M11 and a second common transistor M12; the source electrode of the first common transistor M11 is connected with the power supply VDD, and the drain electrode of the first common transistor M11 is respectively connected with the cascode current mirror circuit G and the grid electrode of the first common transistor M11; the source of the second common transistor M12 is connected to the power supply VDD, the drain of the second common transistor M12 is connected to the gate of the power adjustment transistor M P and the gate of the cascode current mirror circuit G, respectively, and the gate of the second common transistor M12 is connected to the gate of the first common transistor M11.
The pass gate switch S W includes a first pass transistor SW and a second pass transistor SWB connected in parallel. The control signals are external signals SW and SWB, and the external signals SW and SWB are mutually inverse signals.
Further, the low dropout linear regulator of the selectable extra-tab capacitance further comprises a bias circuit H comprising a first bias transistor M15, a second bias transistor M14 and a third bias transistor M16; the source of the first bias transistor M15 is connected to the power supply VDD, the drain of the first bias transistor M15 is connected to a bias current Ibias, which may be provided by a current source circuit; the source electrode of the second bias transistor M14 is connected with the power supply VDD, and the drain electrode of the second bias transistor M14 is connected with the drain electrode of the third bias transistor M16; the grid electrode of the first bias transistor M15 is connected with the grid electrode of the second bias transistor M14 and is respectively connected with bias current Ibias and an error amplifier EA; the gate of the third bias transistor M16 is connected to the drain of the third bias transistor M16 and provides a bias voltage for the error amplifier EA, and the source of the third bias transistor M16 is grounded.
Correspondingly, the error amplifier EA further includes an error transistor M13, where a source of the error transistor M13 is connected to the power supply VDD, a drain of the error transistor M13 is connected to a source of the first differential transistor M1 and a source of the second differential transistor M2 in the differential input circuit F, and a gate of the error transistor M is connected to the bias circuit H.
In addition, the low dropout linear voltage regulator with the optional tab external capacitor further comprises an overcurrent protection circuit Q, wherein one end of the overcurrent protection circuit Q is connected with a power supply VDD, and the other end of the overcurrent protection circuit Q is connected with the output end of the error amplifier EA. The overcurrent protection circuit Q can effectively prevent the chip from being burnt out due to the fact that the low-dropout linear voltage regulator supplies excessive current to the outside.
Therefore, the invention can realize two working modes by using the same circuit structure, and the switching of the working modes is controlled by the switching signal of the transmission gate switch S W. When the transmission gate switch S W is disconnected, the invention can be externally connected with an off-chip capacitor of 1 mu F-10 mu F to be used as a traditional LDO, and the stability of the circuit is mainly compensated by the parasitic resistance of the off-chip capacitor; when the transmission gate switch S W is closed, the off-chip capacitor is removed to form the capacitance-free LDO, and the stability of the circuit is compensated by the on-chip compensation capacitor C M, so that the method can be suitable for different application environments, and the design cost and the chip area are reduced.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (7)
1. The low-dropout linear voltage regulator with the tab-selectable external capacitor is characterized by comprising an error amplifier, a power adjusting tube, a transmission gate switch, a compensation capacitor, a first resistor and a second resistor;
the first resistor is connected with the second resistor in series;
The non-inverting input end of the error amplifier is connected with a reference voltage, the inverting input end of the error amplifier is connected with a sampling point between the first resistor and the second resistor, and the output end of the error amplifier is connected with the grid electrode of the power adjusting tube;
The source electrode of the power adjusting tube is connected with a power supply, and the drain electrode of the power adjusting tube is grounded through a first resistor and a second resistor;
The input end of the compensation capacitor is connected with the source electrode of a transistor in the error amplifier through a transmission gate switch, and the output end of the compensation capacitor is connected with the drain electrode of the power adjusting tube;
The error amplifier comprises a differential input circuit, a cascode current mirror circuit and a common current mirror circuit, wherein one end of the cascode current mirror circuit is connected with the differential input circuit, and the other end of the cascode current mirror circuit is connected with the common current mirror circuit;
The differential input circuit comprises a first differential transistor and a second differential transistor; the drain electrode of the first differential transistor and the drain electrode of the second differential transistor are respectively connected with a cascode current mirror circuit; the source electrode of the first differential transistor and the source electrode of the second differential transistor are respectively connected with a power supply; the grid electrode of the first differential transistor is connected with a reference voltage, and the grid electrode of the second differential transistor is connected with a sampling point between the first resistor and the second resistor;
The cascode current mirror circuit comprises a first common-source transistor, a second common-source transistor, a third common-source transistor, a fourth common-source transistor, a fifth common-source transistor, a sixth common-source transistor, a seventh common-source transistor and an eighth common-source transistor; the gates of the first common-source transistor, the second common-source transistor, the fifth common-source transistor and the sixth common-source transistor are connected with bias voltages; the gates of the third common-source transistor, the fourth common-source transistor, the seventh common-source transistor and the eighth common-source transistor are connected with a differential input circuit; the drain electrode of the first common-source transistor is connected with the differential input circuit, the source electrode of the first common-source transistor is connected with the drain electrode of a third common-source transistor, and the source electrode of the third common-source transistor is grounded; the drain electrode of the second common source transistor is connected with the common current mirror circuit, the source electrode of the second common source transistor is connected with the drain electrode of the fourth common source transistor, and the source electrode of the fourth common source transistor is grounded; the drain electrode of the fifth common source transistor is connected with the common current mirror circuit, the source electrode of the fifth common source transistor is connected with the drain electrode of the seventh common source transistor and the transmission gate switch, and the source electrode of the seventh common source transistor is grounded; the drain electrode of the sixth common source transistor is connected with the differential input circuit, the source electrode of the sixth common source transistor is connected with the drain electrode of the eighth common source transistor, and the source electrode of the eighth common source transistor is grounded.
2. The low dropout linear regulator of claim 1, wherein said common current mirror comprises a first common transistor and a second common transistor;
the source electrode of the first common transistor is connected with a power supply, and the drain electrode of the first common transistor is respectively connected with the cascode current mirror circuit and the grid electrode of the first common transistor;
the source electrode of the second common transistor is connected with a power supply, the drain electrode of the second common transistor is respectively connected with the grid electrodes of the common-source common-grid current mirror circuit and the power adjusting tube, and the grid electrode of the second common transistor is connected with the grid electrode of the first common transistor.
3. The low dropout linear regulator of claim 1, wherein said pass gate switch comprises a first pass transistor and a second pass transistor connected in parallel with each other.
4. The low dropout linear regulator of the selectable extra-tab capacitor of claim 1 further comprising a bias circuit including a first bias transistor, a second bias transistor, and a third bias transistor;
The source electrode of the first bias transistor is connected with a power supply, and the drain electrode of the first bias transistor is connected with bias current;
The source electrode of the second bias transistor is connected with a power supply, and the drain electrode of the second bias transistor is connected with the drain electrode of the third bias transistor;
the grid electrode of the first bias transistor is connected with the grid electrode of the second bias transistor and is respectively connected with bias current and an error amplifier;
The grid electrode of the third bias transistor is connected with the drain electrode of the third bias transistor and provides bias voltage for the error amplifier, and the source electrode of the third bias transistor is grounded.
5. The low dropout linear regulator of claim 1, further comprising an over-current protection circuit having one end connected to a power supply and the other end connected to an output of the error amplifier.
6. The low dropout linear regulator of claim 1, further comprising an output load circuit comprising an equivalent resistive load and an on-chip parasitic capacitance in parallel with each other;
one end of the equivalent resistive load is connected with the drain electrode of the power adjusting tube, and the other end of the equivalent resistive load is grounded;
one end of the on-chip parasitic capacitor is connected with the drain electrode of the power adjusting tube, and the other end of the on-chip parasitic capacitor is grounded.
7. The low dropout linear regulator of claim 6, wherein said output load circuit further comprises an off-chip capacitor and a parasitic resistor connected in series, one end of said off-chip capacitor being connected to the drain of the power regulator tube through the parasitic resistor, and the other end being grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810522576.2A CN108445959B (en) | 2018-05-28 | 2018-05-28 | Low-dropout linear voltage regulator with selectable tab external capacitance |
Applications Claiming Priority (1)
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| CN208351365U (en) * | 2018-05-28 | 2019-01-08 | 佛山华芯微特科技有限公司 | A kind of low pressure difference linear voltage regulator of the outer capacitor of optional contact pin |
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| US9122292B2 (en) * | 2012-12-07 | 2015-09-01 | Sandisk Technologies Inc. | LDO/HDO architecture using supplementary current source to improve effective system bandwidth |
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| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
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