CN109116901B - Linear voltage stabilizing circuit and integrated circuit - Google Patents
Linear voltage stabilizing circuit and integrated circuit Download PDFInfo
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- CN109116901B CN109116901B CN201811289153.7A CN201811289153A CN109116901B CN 109116901 B CN109116901 B CN 109116901B CN 201811289153 A CN201811289153 A CN 201811289153A CN 109116901 B CN109116901 B CN 109116901B
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- voltage stabilizing
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- 230000000087 stabilizing effect Effects 0.000 title claims abstract description 41
- 230000004044 response Effects 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 230000008859 change Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 238000004590 computer program Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000003381 stabilizer Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009125 negative feedback regulation Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The application discloses a linear voltage stabilizing circuit and an integrated circuit, wherein the linear voltage stabilizing circuit is applied to the integrated circuit, and particularly comprises an operational amplifier circuit, a first resistor, a second resistor, a first NMOS tube, a second NMOS tube, a PMOS tube, a filter capacitor and a charge pump, which are connected in a response mode. Compared with the traditional circuit, the first NMOS tube, the second NMOS tube and the PMOS tube in the linear voltage stabilizing circuit form a quick response loop, so that when large load jump occurs, output voltage with smaller change can be obtained, and the stabilizing time of the output voltage is shorter.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a linear voltage stabilizing circuit and an integrated circuit.
Background
The linear voltage stabilizer has the advantages of simple circuit structure, small occupied chip area, low noise and the like, and becomes an important component in the power management chip. With the development of technology, the requirements on the supply current of the linear voltage stabilizer are larger and larger, and the requirements on the load response are also higher, particularly when the load jumps greatly, the output voltage needs to be changed less and the stabilizing time needs to be shorter.
Disclosure of Invention
In view of the above, the present application provides a linear voltage stabilizing circuit and an integrated circuit for providing an output voltage with less variation and shorter stabilizing time when a large jump occurs in a load.
In order to achieve the above object, the following solutions have been proposed:
the utility model provides a linear voltage stabilizing circuit, is applied to the integrated circuit, linear voltage stabilizing circuit includes operational amplifier circuit, first resistance, second resistance, first NMOS pipe, second NMOS pipe, PMOS pipe, filter capacitor and charge pump, wherein:
the non-inverting input end of the operational amplifier circuit is connected with a reference voltage, and the output end of the operational amplifier circuit is connected with the grid electrode of the PMOS tube;
the grid electrode of the first NMOS tube is connected with the charge pump and the drain electrode of the second NMOS tube, the drain electrode is used for connecting a driving voltage, the source electrode is connected with the grid electrode of the second NMOS tube, one end of the first resistor and one end of the filter capacitor, and the grid electrode is used as the positive electrode of the voltage output end of the linear voltage stabilizing circuit;
the source electrode of the second NMOS tube is connected with the source electrode of the PMOS tube;
the other end of the first resistor is connected with the inverting input end of the operational amplifier circuit and one end of the second resistor;
the other end of the second resistor is connected with the drain electrode of the PMOS tube and the other end of the filter capacitor, is used as the negative electrode of the voltage output end of the linear voltage stabilizing circuit, and is grounded.
Optionally, the first NMOS transistor and the second NMOS transistor are NMOS transistors of the same type.
Optionally, the first NMOS transistor, the second NMOS transistor, and the PMOS transistor form a fast response loop.
Optionally, the negative electrode of the voltage output terminal is grounded through a power supply of the integrated circuit.
An integrated circuit, characterized in that a linear voltage stabilizing circuit as described above is provided.
The application discloses a linear voltage stabilizing circuit and an integrated circuit, wherein the linear voltage stabilizing circuit is applied to the integrated circuit, and particularly comprises an operational amplifier circuit, a first resistor, a second resistor, a first NMOS tube, a second NMOS tube, a PMOS tube, a filter capacitor and a charge pump, which are connected in a response mode. Compared with the traditional circuit, the first NMOS tube, the second NMOS tube and the PMOS tube in the linear voltage stabilizing circuit form a quick response loop, so that when large load jump occurs, output voltage with smaller change can be obtained, and the stabilizing time of the output voltage is shorter.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a linear voltage stabilizing circuit according to an embodiment of the present application;
fig. 2 is a load response graph of a linear voltage stabilizing circuit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Example 1
Fig. 1 is a circuit diagram of a linear voltage stabilizing circuit according to an embodiment of the present application.
As shown in fig. 1, the linear voltage stabilizing circuit provided in this embodiment is applied to a chip of an integrated circuit and is used for providing voltage driving for the integrated circuit, where the linear voltage stabilizing circuit includes an operational amplifier circuit A1, a first resistor R1, a second resistor R2, a first NMOS transistor M1, a second NMOS transistor M2, a PMOS transistor M3, a filter capacitor C0 and a charge pump.
The non-inverting input end of the operational amplifier circuit is used for connecting reference voltage VREF, and the output end is connected with the grid electrode of the PMOS tube. The reference voltage is provided by a reference voltage circuit within the integrated circuit.
The grid electrode of the first NMOS tube is connected with the charge pump and the drain electrode of the second NMOS tube, the drain electrode of the first NMOS tube is used for being connected with the driving voltage Vdd, and the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, one end of the first resistor and one end of the filter capacitor and is used as the positive electrode of the voltage output end of the linear voltage stabilizing circuit.
The source electrode of the second NMOS tube is connected with the source electrode of the PMOS tube; the other end of the first resistor is connected with the inverting input end of the operational amplifier circuit and one end of the second resistor; the other end of the second resistor is connected with the drain electrode of the PMOS tube and the other end of the filter capacitor, is used as the negative electrode of the voltage output end of the linear voltage stabilizing circuit, and is grounded through the power supply of the integrated circuit.
The first NMOS transistor and the second NMOS transistor in this embodiment are NMOS transistors of the same type.
The first resistor and the second resistor are voltage dividing resistors of the output voltage of the linear voltage stabilizing circuit and are used for feeding back the output voltage to the positive input end of the operational amplifier A1, and the negative feedback regulation effect of the operational amplifier of the linear voltage stabilizing circuit and the first NMOS tube enables the positive voltage to be equal to the voltage V of the positive input end REF Thus V OUT ＝V REF * (1+R1/R2) to obtain stable output voltage V which does not vary with load current OUT . The charge pump provides a gate driving voltage for the first NMOS transistor.
When the large load Iload changes, the output voltage drops, the voltage is divided by the first resistor and the second resistor and fed back to the time T1 of the operational amplifier circuit, the time T2 for making the grid voltage of the PMOS tube lower is responded by the operation circuit, the time T3 for making the grid voltage of the PMOS tube higher is responded by the charge pump, the time T4 for making the grid voltage of the charge pump driving M1 tube higher is driven by the M1 adjusting tube, the whole responding process time T=t1+t2+t3+t4 is prolonged, the dropping voltage of the VOUT is approximately expressed as delta V= (T×Iload/C0) in the process, and the larger the load current is, the smaller the C0 is, the more the voltage drops.
The first NMOS tube, the second NMOS tube and the PMOS tube form a quick response loop, when the Iload is changed from low to high, the output voltage is reduced, the voltage of the grid electrode of the second NMOS tube is reduced, the voltage is reacted in advance, and the charge pump drives the grid electrode of the first NMOS tube to be increased, so that the output voltage is increased. The response time of T1 and T2 is saved, T is approximately t3+t4, and therefore DeltaV= (T×Iload/C0) is reduced, and the response speed of the linear voltage stabilizing circuit is remarkably improved. The specific response curves are shown in fig. 2.
From the above technical solution, it can be seen that this embodiment provides a linear voltage stabilizing circuit, which is applied to an integrated circuit, and specifically includes an operational amplifier circuit, a first resistor, a second resistor, a first NMOS tube, a second NMOS tube, a PMOS tube, a filter capacitor, and a charge pump, and is connected in a responsive manner. Compared with the traditional circuit, the first NMOS tube, the second NMOS tube and the PMOS tube in the linear voltage stabilizing circuit form a quick response loop, so that when large load jump occurs, output voltage with smaller change can be obtained, and the stabilizing time of the output voltage is shorter.
Example two
The present embodiment provides an integrated circuit provided with the linear voltage stabilizing circuit provided in the previous embodiment. The linear voltage stabilizing circuit specifically comprises an operational amplifier circuit, a first resistor, a second resistor, a first NMOS tube, a second NMOS tube, a PMOS tube, a filter capacitor and a charge pump, and is connected in a response mode. Compared with the traditional circuit, the first NMOS tube, the second NMOS tube and the PMOS tube in the linear voltage stabilizing circuit form a quick response loop, so that when large load jump occurs, output voltage with smaller change can be obtained, the stabilizing time of the output voltage is shorter, and the integrated circuit can be driven by voltage with better quality and work is more stable.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has outlined rather broadly the more detailed description of the application in order that the detailed description of the application that follows may be better understood, and in order that the present principles and embodiments may be better understood; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (5)
1. The utility model provides a linear voltage stabilizing circuit, is applied to integrated circuit, its characterized in that, linear voltage stabilizing circuit includes operational amplifier circuit, first resistance, second resistance, first NMOS pipe, second NMOS pipe, PMOS pipe, filter capacitor and charge pump, wherein:
the non-inverting input end of the operational amplifier circuit is connected with a reference voltage, and the output end of the operational amplifier circuit is connected with the grid electrode of the PMOS tube;
the grid electrode of the first NMOS tube is connected with the charge pump and the drain electrode of the second NMOS tube, the drain electrode is used for connecting a driving voltage, the source electrode is connected with the grid electrode of the second NMOS tube, one end of the first resistor and one end of the filter capacitor, and the grid electrode is used as the positive electrode of the voltage output end of the linear voltage stabilizing circuit;
the source electrode of the second NMOS tube is connected with the source electrode of the PMOS tube;
the other end of the first resistor is connected with the inverting input end of the operational amplifier circuit and one end of the second resistor;
the other end of the second resistor is connected with the drain electrode of the PMOS tube and the other end of the filter capacitor, is used as the negative electrode of the voltage output end of the linear voltage stabilizing circuit, and is grounded.
2. The linear voltage regulator circuit of claim 1, wherein the first NMOS transistor and the second NMOS transistor are of the same type.
3. The linear voltage regulator circuit of claim 1, wherein the first NMOS transistor, the second NMOS transistor, and the PMOS transistor form a fast response loop.
4. The linear voltage regulator circuit of claim 1, wherein the voltage output terminal negative electrode is coupled to ground through a power supply of the integrated circuit.
5. An integrated circuit, characterized in that a linear voltage stabilizing circuit as claimed in any one of claims 1-3 is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811289153.7A CN109116901B (en) | 2018-10-31 | 2018-10-31 | Linear voltage stabilizing circuit and integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811289153.7A CN109116901B (en) | 2018-10-31 | 2018-10-31 | Linear voltage stabilizing circuit and integrated circuit |
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| CN109116901A CN109116901A (en) | 2019-01-01 |
| CN109116901B true CN109116901B (en) | 2023-09-15 |
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| CN110262610B (en) * | 2019-07-10 | 2021-01-05 | 上海艾为电子技术股份有限公司 | Linear voltage stabilizer of power tube |
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