WO2018058950A1

WO2018058950A1 - Power supply management circuit and implementation method therefor

Info

Publication number: WO2018058950A1
Application number: PCT/CN2017/082277
Authority: WO
Inventors: 李子悦
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-09-28
Filing date: 2017-04-27
Publication date: 2018-04-05
Also published as: CN107872152B; CN107872152A

Abstract

Disclosed is a power supply management circuit and an implementation method therefor. The circuit comprises: an oscillator circuit, a charge pump circuit and a negative feedback circuit. The oscillator circuit is connected to the charge pump circuit, and the negative feedback circuit is respectively connected to the oscillator circuit and the charge pump circuit. The oscillator circuit is configured to generate two opposite clock signals to the charge pump circuit according to an input voltage. The charge pump circuit is configured to boost, according to the two opposite clock signals generated by the oscillator circuit, the input voltage and output same. The negative feedback circuit is configured to stabilize an output voltage of the charge pump circuit and output a feedback signal, wherein the feedback signal is used for controlling the working of the oscillator circuit.

Description

Power management circuit and implementation method thereof

Cross-reference to related applications

The present application is based on a Chinese patent application filed on Jan. 28, 2016, the entire disclosure of which is hereby incorporated by reference.

Technical field

Embodiments of the present invention relate to the field of integrated circuits, and in particular, to a power management circuit and an implementation method thereof.

Background technique

Nowadays, the application of chips is more and more extensive, ranging from a miniature signal tracker to a space station, and the chip plays a vital role in various application fields. However, the operation of the chip is inseparable from the supply of power. For most devices, the chip can be supplied with a continuous power supply by replacing the battery, but for some special devices, such as implantable medical devices, animal tracking devices, etc., by replacing the battery. Providing a continuous power supply to the chip is almost impossible. However, most of the environment in which the chip works is available, such as electromagnetic waves, light energy, vibration, temperature changes, etc., which can be collected in some way and converted into electrical energy, such as micro-thermal energy generated by temperature difference. Batteries, individual solar cells, microbial fuel cells, devices that use the building's own tiny vibrations to obtain electrical energy to monitor the temperature of the room, thereby not only solving the problem that the chip cannot be powered, but also reducing the frequency of use of the low-voltage battery. For example, in a Bluetooth headset, the battery life of the existing battery is very short, and due to the cost and portability requirements, the Bluetooth headset may be equipped with a high-performance battery or a large-capacity battery, so if it can be self-powered by using environmental energy collection. Can save a lot of battery power consumption even To completely replace the battery.

However, in actual operation, the energy obtained through energy collection is not ideal, and the collected energy supply usually provides a low output voltage, which often requires a variable frequency power management circuit to switch to a higher power supply voltage for use. Under the state-of-the-art Complementary Metal Oxide Semiconductor (CMOS) process, even if the threshold voltage of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) can reach less than 400mV, Running a high-performance circuit at 0.5V is still a very difficult task. Therefore, the collected energy can not be directly used as the power supply of the chip, or it needs to be boosted, rectified and regulated. Then at this time, a circuit is needed to rectify, boost and stabilize these low-voltage energy sources to supply the chip. In the prior art, the input voltage is often boosted by a boost converter circuit. However, these boost converters need to be implemented by some special structures such as an extra high battery voltage and a mechanical oscillation switch, and the structure is very complicated and difficult to implement. Therefore, how to simply and conveniently boost and stabilize the low-voltage unstable energy collected in the environment to obtain a stable voltage that can be supplied to the chip is an urgent problem to be solved.

Summary of the invention

In view of this, embodiments of the present invention are directed to providing a power management circuit and an implementation method thereof for simply and conveniently boosting and stabilizing a low-voltage unstable energy collected in an environment, thereby obtaining a work that can be supplied to the chip. Stabilize the voltage.

The technical solution of the embodiment of the present invention is implemented as follows:

A power management circuit includes: an oscillator circuit, a charge pump circuit, and a negative feedback circuit; the oscillator circuit is coupled to the charge pump circuit, and the negative feedback circuit is coupled to the oscillator circuit and the charge pump, respectively Connected to the circuit;

The oscillator circuit is configured to generate two opposite clock signals to the charge pump circuit according to an input voltage;

The charge pump circuit is configured to boost and output the input voltage according to two opposite clock signals generated by the oscillator circuit;

The negative feedback circuit is configured to regulate an output voltage of the charge pump circuit and output a feedback signal for controlling operation of the oscillator circuit.

In other embodiments of the invention, the negative feedback circuit is a zero temperature coefficient negative feedback circuit.

In other embodiments of the present invention, the oscillator circuit includes a ring oscillator circuit and a linear oscillator circuit, the ring oscillator circuit is composed of 13 inverters configured to generate a first clock signal by self-oscillation The linear oscillator circuit is configured to divide the first clock signal into two second clock signals that are 180 out of phase.

In other embodiments of the invention, the first clock signal has a frequency of 8.14 MHz.

In other embodiments of the invention, the charge pump circuit is a 6 stage Pelliconi charge pump circuit.

A method for implementing a power management circuit includes:

Generating two opposite clock signals based on the input voltage;

The input voltage is boosted and output according to the two opposite clock signals;

The output voltage is regulated and a feedback signal is output, the feedback signal being used to control the input voltage.

The power management circuit provided by the embodiment of the invention includes: an oscillator circuit, a charge pump circuit and a negative feedback circuit; the oscillator circuit is connected to the charge pump circuit, and the negative feedback circuit is respectively connected to the oscillator circuit and the charge pump circuit; the oscillator circuit Configuring to generate two opposite clock signals according to the input voltage to the charge pump circuit; the charge pump circuit configured to boost and output the input voltage according to two opposite clock signals generated by the oscillator circuit; a negative feedback circuit, configured In order to regulate the output voltage of the charge pump circuit and output a feedback signal, the feedback signal is used to control the operation of the oscillator circuit. It is simple and convenient to boost and stabilize the low-voltage unstable energy collected in the environment, thereby obtaining a stable voltage that can supply the chip to work.

DRAWINGS

1 is a schematic structural diagram of an embodiment of a power management circuit according to the present invention;

2 is a schematic structural view of an oscillator circuit of the present invention;

3 is a schematic structural view of a charge pump circuit of the present invention;

4 is a schematic structural view of a zero temperature coefficient negative feedback circuit of the present invention;

5 is a schematic structural view of a first part of a zero temperature coefficient negative feedback circuit of the present invention;

6 is a schematic structural view of a second part of a zero temperature coefficient negative feedback circuit of the present invention;

7 is a schematic structural view of a third portion of a zero temperature coefficient negative feedback circuit of the present invention;

8 is a schematic structural view of a fourth part of a zero temperature coefficient negative feedback circuit of the present invention;

FIG. 9 is a schematic flowchart diagram of an embodiment of a method for implementing a power management circuit according to the present invention.

detailed description

In order to avoid the use of additional structures to increase cost and process difficulty, the power management circuit provided by the present invention is implemented by a standard CMOS process.

1 is a schematic structural diagram of an embodiment of a power management circuit according to the present invention. As shown in FIG. 1, the power management circuit provided in this embodiment includes: an oscillator circuit, a charge pump circuit, and a negative feedback circuit; and the oscillator circuit is connected to the charge pump circuit. The negative feedback circuit is respectively connected to the oscillator circuit and the charge pump circuit;

An oscillator circuit configured to generate two opposite clock signals according to an input voltage to the charge pump circuit; the charge pump circuit configured to boost and output the input voltage according to two opposite clock signals generated by the oscillator circuit; negative feedback The circuit is configured to regulate the output voltage of the charge pump circuit and output a feedback signal for controlling the operation of the oscillator circuit.

It should be noted that the negative feedback circuit is a zero temperature coefficient negative feedback circuit.

2 is a schematic structural diagram of an oscillator circuit of the present invention. As shown in FIG. 2, the oscillator circuit includes a ring oscillator circuit and a linear oscillator circuit. The ring oscillator circuit is composed of 13 inverters and configured to generate self-oscillation. a first clock signal; the linear oscillator circuit is configured to be the first time The clock signal is divided into two second clock signals that are 180 out of phase. The first clock signal has a frequency of 8.14 MHz.

It should also be noted that the charge pump circuit is a 6-stage Pelliconi charge pump circuit. 3 is a schematic structural view of a charge pump circuit of the present invention. As shown in FIG. 3, an N-Metal-Oxide-Semiconductor (NMOS) named near the clock signal CLK ₁ is respectively M _n1 , M _N3 , M _n5 , M _n7 , M _n9 , M _n11 , P-Metal-Oxide-Semiconductor (PMOS) are M _p1 , M _p3 , M _p5 , M _p7 , M _p9 , M _p11 ; The NMOS named near the clock signal CLK ₂ is M _n2 , M _n4 , M _n6 , M _n8 , M _n10 , M _n12 , respectively, and the PMOS is M _p2 , M _p4 , M _p6 , M _p8 , M _p10 , M _P12 . When the clock signal CLK ₁ is at a high level and the clock signal CLK ₂ is at a low level, M _p1 and _{Mn4 are} turned on, and from node A ₁ to node B ₂ , the voltage rises from V _DD to 2V _DD ; when the clock signal CLK ₁ is low level, when clock signal CLK ₂ is high level, M _p2 and M _{n3 are} turned on, and from node A ₂ to node B ₁ , the voltage rises from V _DD to 2V _DD . Each stage has the same effect, and the voltage can be boosted by a V _DD , and so on. At the final output, the voltage will rise to 6V _DD to boost the low voltage.

4 is a schematic structural diagram of a zero temperature coefficient negative feedback circuit of the present invention, assuming that the ambient voltage of the analog input is a low voltage of 400 mV to 800 mV, and the output terminal is required to obtain a stable voltage of 1 V, and the precision is designed within a range of 3% error, and Capable of driving a 1nF capacitor, the operation of the zero temperature coefficient negative feedback circuit of the present invention will be described below. Due to the complexity of this part of the circuit structure, it will be described as a four-part circuit. 5 is a schematic structural view of a first part of a zero temperature coefficient negative feedback circuit of the present invention, FIG. 6 is a schematic structural view of a second part of a zero temperature coefficient negative feedback circuit of the present invention, and FIG. 7 is a third part of the zero temperature coefficient negative feedback circuit of the present invention. FIG. 8 is a schematic structural view of the fourth part of the zero temperature coefficient negative feedback circuit of the present invention.

As shown in Figure 5, V _cc is the output voltage V _out of the charge pump, that is, the input voltage of the zero temperature coefficient negative feedback circuit, V _cc rises from zero volts, according to the design of the charge pump circuit, if the load and circuit are not considered The loss, in theory, V _cc will rise to 6V _cc , which is obviously not satisfactory. The negative feedback circuit starts to work when V _cc rises above 1V, and feeds back a signal to the circuit to stop the charge pump circuit. Therefore, the voltage stops rising.

V _cc rises from zero volts, a starting voltage V _cc is very low, below the threshold voltage of M _N1, M _N1 thus actually in the OFF state, the following effect R ₇ does not generate the voltage zero volts at point B , M _N2 and M _N3 is lower than the threshold voltage, M _N2 and M _N3 is also in the oFF state. At this point, the voltage at point A is V _cc . Since both M _N1 and M _N3 are off, there is no current flowing down from M _P1 , and the entire circuit does not work at all when V _{cc is} less than the threshold voltage of M _N1 .

When the threshold voltage V _cc is greater than M _N1, M _N1 is turned on, see _{_{M P1 -> M N1 ->}} R 7 this branch to work with current down. The current of the M _P1 -> M _N1 -> R ₇ branch rises from zero, that is, the current at the beginning of the M _P1 -> M _N1 -> branch is very small, and this current is recorded as I _b . When I _b is very small, the voltage V _C generated by M _N1 flowing through R ₇ and having a very small impedance after conduction is also low, and the impedance of M _P1 is small, which causes the current I _{b to} increase. In this case, I _b is small, V _B = I _b R ₇ is very small, less than M _N1 and the threshold voltage of M _N3, M _N1 and M _N3 remain off.

Then V _cc continues to increase, I _b also gradually increases, V _C also increases, and because V _C controls the gate of M _P1 , V _C increases, the impedance of M _P1 increases, but decreases I. _b , will eventually reach a balance point. The voltage V _B generated by the flow of I _b through R ₇ will increase as the household grows, and eventually tends to be stable.

As shown in FIG. 6, V _X = V _BE1 , V _Y = V _BE2 + V _R1 , where V _BE1 and V _{BE2 are} the emission stage voltages of the transistors Q ₁ and Q ₂ . Since the specifications of the PMOS transistors M _P1 and M _P2 are the same, the currents I ₁ and I ₂ flowing downward from the M _P9 and the M _P2 tubes are the same, so that I ₁ = I ₂ = I, and V _X = V _Y can be obtained. Further, R ₂ = R ₄ and R ₃ = R _{5 are} designed, and then the current I(R ₂ , R ₃ ) flowing through R ₂ and R ₃ = I (R ₄ , R ₅ ). Flowing through _Q1 and the current flowing through Q Q I _Q2 ₂ is the same current I _1, the definition of _{_{_{I Q1 = I Q2 = I Q}}} . Obviously, since V _X = V _Y , I _Q1 = I _Q2 , V _BE1 = V _X = V _Y = V _BE2 + I _Q2 R ₁ = V _BE2 + I _Q R ₁ , and ΔV _BE = V _BE1 - V _BE2 =I _Q R ₁ . According to the bandgap reference principle, V _BE is a negative temperature coefficient voltage, and ΔV _BE is a positive temperature coefficient voltage, ΔV _BE =I _Q R ₁ , V _BE1 =V _X =(II _Q )(R ₄ +R ₅ ), combined with two

Then, a proper zero temperature coefficient current I can be obtained by appropriately adjusting the ratio of R ₁ and R ₄ + R ₅ .

As shown in Figure 7, V ₁ and V ₂ serve as the two inputs of the comparator, respectively. V ₁ and V ₂ control the gates of the two PMOSs, respectively, since V ₁ < V ₂ . V ₁ is then controlled PMOS conductivity better than V ₂ of PMOS control, causing a current to the comparator is greater than the flow through the left branch to the right leg. The voltage drawn from the left branch is a high level. This high level is greater than the threshold voltage of the NMOS it controls, and M _{N6 is} turned on. Referring to Figure 8, when V _cc exceeds 1V, M _N4 , M _N5 , M _N6 , M _N7 are all turned on, and O point gets a low level. After passing through an inverter, the negative feedback circuit outputs a high level. To meet the design requirements.

As shown in Fig. 8, when V _{cc is} low, the current I _s through R _{P 5} , R ₈ is small, and the U point voltage V _U = I _s R ₈ is also low. M _P3 mirrors the current I _s . The initial V _{cc is} not high, the voltage at point D is not high, and the threshold voltage is not exceeded. M _N4 , M _N5 and M _N7 are not turned on. When V _{cc is} low, the current I flowing through the bandgap reference is not large, which can be considered as the ideal case, that is, V _X = V _Y , and because the resistances R ₂ = R ₄ and R ₃ = R ₅ , then R ₂ between the voltage V and the voltage V between R _₃₂ and R ₅ ₁ and R ₄ are the same. 4 to 6 in conjunction with FIG zero temperature coefficient portion of the negative feedback circuit, the comparator output voltage V _com is low, the control gate V _com M _N6, in which case M _N6 has not turned on, the voltage V _O is the point O A high level, after passing through the inverter, the negative feedback circuit outputs a low level.

As V _cc rises gradually, the current in the bandgap reference increases, a non-ideal condition occurs, V ₁ and V ₂ begin to differ, and the comparator outputs a high level V _com , at which point V _{com is} greater than the threshold voltage of M _N6 , M _{N6 is} turned on. But at this time, V _cc has not risen to 1V, and a negative feedback is needed to output a low level to ensure that the charge pump continues to work boost. Then, in order to make the O point voltage V _O high, M _N4 , M _N5 and M _{N7 are used.} . Since the parameter specifications of M _N4 and M _N5 are the same, the voltage at point D is the general value of the gate voltage of M _N4 , that is, even if the current becomes larger, the gate voltage of _MN4 exceeds a threshold voltage, but as long as it does not exceed 2 times The threshold voltage, the voltage at point D is still not enough to make _MN7 turn on, so O still maintains a high level, which satisfies the requirement that the negative feedback circuit outputs a low level before V _{cc is} less than 1V.

In the power management circuit provided in this embodiment, the oscillator circuit generates two opposite clock signals to the charge pump circuit, and the charge pump circuit boosts the input voltage according to two opposite clock signals generated by the oscillator circuit, and the zero temperature coefficient is negative. The feedback circuit regulates the output voltage of the charge pump circuit, so as to simply and conveniently boost and stabilize the low-voltage unstable energy collected in the environment, thereby obtaining a stable voltage that can be supplied to the chip.

FIG. 9 is a schematic flowchart of a method for implementing a power management circuit according to the present invention. The method for implementing a power management circuit provided by the present invention includes:

Step 11. Generate two opposite clock signals according to the input voltage;

Step 12: boosting and outputting the input voltage according to two opposite clock signals;

Step 13. Regulate the output voltage and output a feedback signal, and the feedback signal is used to control the input voltage.

The implementation method of the power management circuit provided by this embodiment is implemented based on the power management circuit, and the implementation principle and technical effects are similar, and details are not described herein again.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to generate a machine for generating instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory comprise an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to generate computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

The power management circuit provided by the embodiment of the invention includes: an oscillator circuit, a charge pump circuit and a negative feedback circuit; the oscillator circuit is connected to the charge pump circuit, and the negative feedback circuit is respectively connected to the oscillator circuit and the charge pump circuit; the oscillator circuit Configuring to generate two opposite clock signals according to the input voltage to the charge pump circuit; the charge pump circuit configured to boost and output the input voltage according to two opposite clock signals generated by the oscillator circuit; a negative feedback circuit, configured For electricity The output voltage of the pump circuit is regulated and a feedback signal is output, and the feedback signal is used to control the operation of the oscillator circuit. It is simple and convenient to boost and stabilize the low-voltage unstable energy collected in the environment, thereby obtaining a stable voltage that can supply the chip to work.

Claims

A power management circuit, the power management circuit includes: an oscillator circuit, a charge pump circuit, and a negative feedback circuit; the oscillator circuit is coupled to the charge pump circuit, and the negative feedback circuit and the oscillator circuit are respectively The charge pump circuit is connected;

The oscillator circuit is configured to generate two opposite clock signals to the charge pump circuit according to an input voltage;

The charge pump circuit is configured to boost and output the input voltage according to two opposite clock signals generated by the oscillator circuit;

The negative feedback circuit is configured to regulate an output voltage of the charge pump circuit and output a feedback signal for controlling operation of the oscillator circuit.
The power management circuit of claim 1 wherein said negative feedback circuit is a zero temperature coefficient negative feedback circuit.
The power management circuit according to claim 1, wherein said oscillator circuit comprises a ring oscillator circuit and a linear oscillator circuit, said ring oscillator circuit being composed of 13 inverters configured to generate a self-oscillation a first clock signal; the linear oscillator circuit configured to divide the first clock signal into two second clock signals that are 180 out of phase.
The power management circuit of claim 3 wherein said first clock signal has a frequency of 8.14 MHz.
The power management circuit of claim 1 wherein said charge pump circuit is a 6-stage Pelliconi charge pump circuit.
A method for implementing a power management circuit, the method comprising: generating two opposite clock signals according to an input voltage; boosting and outputting the input voltage according to the two opposite clock signals; and stabilizing the output voltage The feedback signal is pressed and output, and the feedback signal is used to control the input voltage.