CN102650893B - Low dropout linear regulator - Google Patents
Low dropout linear regulator Download PDFInfo
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- CN102650893B CN102650893B CN201110054224.7A CN201110054224A CN102650893B CN 102650893 B CN102650893 B CN 102650893B CN 201110054224 A CN201110054224 A CN 201110054224A CN 102650893 B CN102650893 B CN 102650893B
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Abstract
The invention provides a low dropout linear regulator which comprises a differential amplifying circuit, an output stage circuit, a feedback circuit, a current-limiting circuit and a start ending signal generation circuit, wherein the start ending signal generation circuit is connected with the differential amplifying circuit or is connected with the current-limiting circuit and is used for generating a start ending signal according to the voltage changing along with the starting process in the differential amplifying circuit or the current-limiting circuit when the starting process of the low dropout linear regulator is ended and maintaining the start ending signal; a time point generated by the start ending signal corresponds to a time point of the ending of the starting process; and the start ending signal is a voltage signal. According to the low dropout linear regulator disclosed by the invention, the start ending signal can be generated to accurately distinguish the start state from the normal work state of the low dropout linear regulator, so that parameters of certain devices in the low dropout linear regulator can be adjusted and further the performances of the low dropout linear regulator are improved.
Description
Technical field
The present invention relates to a kind of low pressure difference linear voltage regulator, relate in particular to a kind of low pressure difference linear voltage regulator that can produce startup end signal.
Background technology
Low pressure difference linear voltage regulator (LDO voltage stabilizer) is because its cost is low, and noise is low, and quiescent current is little and be widely used in battery powered portable type electronic product, in the composite power source module such as mobile phone, digital camera and MP3 etc.
Fig. 1 has shown the structural representation of LDO voltage stabilizer of the prior art.As shown in Figure 1, LDO voltage stabilizer 1 of the prior art comprises differential amplifier circuit 11, output-stage circuit 12, feedback circuit 13 and current-limiting circuit 14.The normal phase input end of differential amplifier circuit 11 is connected with the output terminal of feedback circuit 13, and the inverting input input of differential amplifier circuit 11 has reference voltage V ref, and the output terminal of differential amplifier circuit 11 is connected with the input end of output-stage circuit 12.Be connected with current-limiting circuit 14 at the input end of output-stage circuit 12.The input end of feedback circuit 13 is connected with the output terminal of output-stage circuit 12.Differential amplifier circuit 11, is controlled output-stage circuit 12 by feedback circuit 13, so that the output voltage of output-stage circuit 12 stable outputs in normal operating conditions in the situation that at LDO voltage stabilizer 1.Current-limiting circuit 14, is controlled output-stage circuit 12, to limit the output current of output-stage circuit 12 in starting state in the situation that at LDO voltage stabilizer 1.
For the LDO voltage stabilizer 1 of the prior art shown in Fig. 1, we are merely able to the opening/closing of this LDO voltage stabilizer 1 to control, still, and for the current duty of LDO voltage stabilizer 1, especially the startup end time of LDO voltage stabilizer 1, we also do not know.
In LDO voltage stabilizer 1, owing to not knowing the startup end time of LDO voltage stabilizer 1, cannot distinguish starting state and the normal operating conditions of LDO voltage stabilizer 1, therefore can not adjust the parameter of the device in LDO circuit.
In addition, in the time that LDO voltage stabilizer 1 starts, sometimes need to limit especially the starting current of LDO voltage stabilizer 1.But, owing to not knowing the startup end time of LDO voltage stabilizer 1, therefore, also need delay circuit is set in addition at the control circuit of the starting current for limiting LDO voltage stabilizer 1, thereby cause the complex structure of control circuit.
In composite power source module, if adopt the LDO voltage stabilizer 1 of prior art, in the time starting multiple LDO voltage stabilizer 1, owing to not knowing the startup end time of each LDO voltage stabilizer 1, therefore, need in startup sequential circuit, increase delay circuit, thereby cause the complex structure that starts sequential circuit, in addition, the overall startup time of multiple LDO voltage stabilizers 1 is also longer.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of low pressure difference linear voltage regulator, this low pressure difference linear voltage regulator can produce startup end signal, accurately to distinguish starting state and the normal operating conditions of low pressure difference linear voltage regulator.
A kind of low pressure difference linear voltage regulator of the present invention, comprises differential amplifier circuit, output-stage circuit, feedback circuit and current-limiting circuit, wherein:
The normal phase input end of differential amplifier circuit is connected with the output terminal of feedback circuit, and the input of the inverting input of differential amplifier circuit has reference voltage, and the output terminal of differential amplifier circuit and the input end of output-stage circuit are connected; Input end at output-stage circuit is connected with current-limiting circuit; The input end of feedback circuit is connected with the output terminal of output-stage circuit;
Differential amplifier circuit, is controlled output-stage circuit by feedback circuit, so that the output voltage of output-stage circuit stable output in normal operating conditions in the situation that at low pressure difference linear voltage regulator;
Current-limiting circuit, is controlled output-stage circuit, to limit the output current of output-stage circuit in starting state in the situation that at low pressure difference linear voltage regulator;
Low pressure difference linear voltage regulator further comprises that starting end signal produces circuit, this startup end signal produces circuit and is connected with differential amplifier circuit, or be connected with current-limiting circuit, for when the start-up course of low pressure difference linear voltage regulator finishes, produce and start end signal according to the voltage changing with start-up course in differential amplifier circuit or current-limiting circuit, and keeping this startup end voltage signal, the time point that the time point that startup end voltage signal produces finishes with start-up course is corresponding.
In low pressure difference linear voltage regulator of the present invention, start end voltage signal owing to producing, accurately to distinguish starting state and the normal operating conditions of low pressure difference linear voltage regulator, therefore can adjust the parameter of some device in low pressure difference linear voltage regulator, thus the performance of raising low pressure difference linear voltage regulator.
In addition, in low pressure difference linear voltage regulator of the present invention, start end voltage signal owing to producing, therefore in the time needing the starting current of special restriction low pressure difference linear voltage regulator, in control circuit, do not need delay circuit is set in addition, thereby simplified control circuit.
Further, when adopt multiple low pressure difference linear voltage regulator of the present invention in composite power source module time, in the time starting multiple low pressure difference linear voltage regulator of the present invention, because can both producing, each low pressure difference linear voltage regulator starts end voltage signal, that is to say, can know the startup end time of each LDO voltage stabilizer 1, therefore, can simplify startup sequential circuit, also can shorten the overall startup time of multiple low pressure difference linear voltage regulators simultaneously.
Brief description of the drawings
Fig. 1 has shown the structural representation of LDO voltage stabilizer of the prior art;
Fig. 2 has shown according to the structural representation of the LDO voltage stabilizer of the first embodiment of the present invention;
Fig. 3 has shown an example according to the circuit diagram of the LDO voltage stabilizer of the first embodiment of the present invention;
Fig. 4 has shown according to another example of the circuit diagram of the LDO voltage stabilizer of the first embodiment of the present invention;
Fig. 5 has shown according to another example of the circuit diagram of the LDO voltage stabilizer of the first embodiment of the present invention;
Fig. 6 has shown the structural representation of LDO voltage stabilizer according to a second embodiment of the present invention;
Fig. 7 has shown the partial circuit diagram of LDO voltage stabilizer according to a second embodiment of the present invention;
Fig. 8 (A) has shown the sequential chart that the starting current of the LDO voltage stabilizer of control circuit to prior art is controlled;
Fig. 8 (B) has shown the sequential chart that control circuit is controlled the starting current of LDO voltage stabilizer of the present invention;
Fig. 9 (A) has shown the sequential chart that the LDO voltage stabilizer of multiple prior aries starts in composite power source module;
Fig. 9 (B) has shown the sequential chart that multiple LDO voltage stabilizers of the present invention start in composite power source module.
Embodiment
Below will be described with reference to the drawings according to various embodiments of the present invention.
For LDO voltage stabilizer; main point of following two kinds of duties: normal operating conditions (output voltage, output current are all in normal interval); and guard mode (output current is greater than normal output current; LDO voltage stabilizer need to limit the electric current self staying, and then plays the object of protection).
When LDO voltage stabilizer is during in starting state, output voltage is less than normal voltage, and LDO voltage stabilizer need to be to outside capacitor charging, and output current can exceed normal current, if not restriction, electric current will exceed the current capacity of outside or inner wire.That is to say, the starting state of LDO voltage stabilizer belongs to the one in guard mode.
No matter which kind of state, LDO voltage stabilizer all needs the reference mark Pgate of output-stage circuit to control.
When LDO voltage stabilizer is during in normal operating conditions, output-stage circuit is controlled by differential amplifier circuit, and meanwhile, the output of current-limiting circuit is relatively in high-impedance state.On the contrary, when LDO voltage stabilizer is when guard mode (starting state), output-stage circuit is controlled by current-limiting circuit, and meanwhile, the output of differential amplifier circuit is relatively in high-impedance state.Therefore, no matter be from differential amplifier circuit or from current-limiting circuit, can judge LDO voltage stabilizer whether in starting state, start end signal (RISEND signal) thereby produce.
RISEND signal is the signal that represents that the starting state of LDO voltage stabilizer finishes.The time point that RISEND signal produces is corresponding with the time point that the starting state of LDO voltage stabilizer finishes.Before RISEND signal produces, represent that LDO voltage stabilizer is in starting state, after RISEND signal produces, represent that LDO voltage stabilizer is in normal operating conditions.In the present invention, RISEND signal is with the form performance of voltage signal.
The first embodiment
Illustrate according to the example of the LDO voltage stabilizer from differential amplifier circuit generation RISEND signal of the first embodiment of the present invention below with reference to Fig. 2 to Fig. 5.Fig. 2 has shown according to the structural representation of the LDO voltage stabilizer of the first embodiment of the present invention.Fig. 3 has shown an example according to the circuit diagram of the LDO voltage stabilizer of the first embodiment of the present invention.Fig. 4 has shown according to another example of the circuit diagram of the LDO voltage stabilizer of the first embodiment of the present invention.Fig. 5 has shown according to another example of the circuit diagram of the LDO voltage stabilizer of the first embodiment of the present invention.
As shown in Figures 2 to 5, LDO voltage stabilizer 2 of the present invention comprises differential amplifier circuit 21, output-stage circuit 22, feedback circuit 23, current-limiting circuit 24 and starts end signal generation circuit 25.
(1) differential amplifier circuit 21
As shown in Figure 2, the normal phase input end of differential amplifier circuit 21 is connected with the output terminal of feedback circuit 23, and the inverting input input of differential amplifier circuit 21 has reference voltage V ref, and the output terminal of differential amplifier circuit 21 is connected with output-stage circuit 22.Differential amplifier circuit 21, is controlled output-stage circuit 22 by feedback circuit 23, so that the output voltage V out of output-stage circuit 22 stable outputs in normal operating conditions in the situation that at LDO voltage stabilizer 2.
In addition, as shown in Figure 2, differential amplifier circuit 21 also produces circuit 25 with startup end signal and is connected, and produces circuit 25 when the start-up course of LDO voltage stabilizer 2 finishes so that start end signal, according to the voltage generation RISEND signal changing with start-up course in differential amplifier circuit 21.Then, starting end signal generation circuit 25 can input to the RISEND signal feedback of generation in differential amplifier circuit 21, so that differential amplifier circuit 21 is adjusted the parameter of some device according to RISEND signal, such as adjusting the reference voltage V ref that produces and be input to by external voltage source in the inverting input of differential amplifier circuit 21, or can adjust etc. the feedback voltage Vfb that produces and be input to the normal phase input end in differential amplifier circuit 21 by feedback circuit 23.
Illustrate according to the circuit structure of the differential amplifier circuit 21 of the first embodiment of the present invention below with reference to Fig. 3 to Fig. 5.
As shown in Figures 3 and 4, differential amplifier circuit 21 comprises metal-oxide-semiconductor field effect transistor M12～M16 and current source Is1, Is2, and wherein M12～M14 is PMOS field effect transistor, and M15 and M16 are NMOS field effect transistor.The grid of M16 is connected with the external voltage source that produces reference voltage V ref, and the source electrode of M16 is connected with the first end of current source Is1, and the drain electrode of M16 is connected with the grid of the drain and gate of M14 and M13.The source electrode of M12, M13 and M14 is connected with direct supply.The drain electrode of M13 is connected with the drain electrode of the grid of M12 and M15.The source electrode of M15 is connected with the first end of current source Is1, and the grid of M15 is connected with feedback circuit 23.The drain electrode of M12 is connected with first end and the output-stage circuit 22 of current source Is2.The second end ground connection of current source Is1 and Is2.
Current source Is1 and Is2, for providing bias current at differential amplifier circuit 21, also can replace with other circuit blocks such as metal-oxide-semiconductor field effect transistor etc.
The circuit structure of differential amplifier circuit 21 is not limited to the concrete structure shown in Fig. 3 and Fig. 4, all can be used as the differential amplifier circuit 21 in the present invention as long as can realize the circuit structure of " at LDO voltage stabilizer in normal operating conditions in the situation that; by feedback circuit, output-stage circuit is controlled, so that the output voltage V out of output-stage circuit stable output " this function.
In the present invention, as shown in Figure 3 and Figure 4, M12 is the final stage metal-oxide-semiconductor field effect transistor of differential amplifier circuit 21, the voltage Va at the grid place of M12 is the voltage changing with start-up course when the start-up course of LDO voltage stabilizer 2 finishes in differential amplifier circuit 21, therefore, start end signal generation circuit 25 and can produce RISEND signal according to this voltage Va.
In the time that LDO voltage stabilizer 2 is before starting and in start-up course, the voltage Va at the grid place of M12 equals the voltage Vdd of direct supply, M12 cut-off, and differential amplifier circuit 21 is in high-impedance state.When LDO voltage stabilizer 2 is in the time that start-up course finishes, the voltage Va step-down at the grid place of M12, M12 conducting, differential amplifier circuit 21 is started working.Therefore, the voltage Va at the grid place of the final stage metal-oxide-semiconductor field effect transistor M12 in differential amplifier circuit 21 is the voltage changing with start-up course when the start-up course of LDO voltage stabilizer 2 finishes in differential amplifier circuit 21.
In the present invention, although the example for generation of the voltage of RISEND signal in using the voltage Va at the grid place of final stage metal-oxide-semiconductor field effect transistor M12 as differential amplifier circuit 21 describes, but, in differential amplifier circuit, can be not limited to for generation of the voltage of RISEND signal the voltage at the grid place of the final stage metal-oxide-semiconductor field effect transistor of differential amplifier circuit.For example, when because of needs the M12 of differential amplifier circuit 21 increase again what metal-oxide-semiconductor field effect transistor below time, the voltage at the grid place of the final stage metal-oxide-semiconductor field effect transistor newly increasing, or the voltage at the grid place of M12 all can be used as the voltage for generation of RISEND signal.That is to say, in differential amplifier circuit, all can be used as the voltage for generation of RISEND signal as long as meet at the voltage of " start-up course of LDO voltage stabilizer changes with start-up course in finishing " this condition.
In addition, in the start-up course of LDO voltage stabilizer 2, in the time that the output voltage V out of LDO voltage stabilizer 2 rises to target voltage, because expended the reflecting time of differential amplifier circuit 21, charging current can not terminate in external capacitive, and therefore overshoot phenomenon occurs output voltage V out sometimes.For fear of this overshoot phenomenon, the RISEND signal that we can produce based on startup end signal generation circuit 25 is adjusted the reference voltage V ref or the feedback voltage Vfb that input to differential amplifier circuit 21.
Fig. 5 has shown the example based on starting end signal and produce the circuit structure of the differential amplifier circuit 21 that the RISEND signal that produces of circuit 25 adjusts reference voltage V ref.As shown in Figure 5, differential amplifier circuit 21 is except comprising the metal-oxide-semiconductor field effect transistor M12～M16 shown in Fig. 3 and Fig. 4 and current source Is1, Is2, differential amplifier circuit 21 also comprises reference voltage regulating circuit 211, for the RISEND signal producing according to startup end signal generation circuit 25, the reference voltage V ref of input is adjusted.The switch that reference voltage regulating circuit 211 comprises voltage source V os1 and is in parallel with voltage source V os1, the opening/closing of switch is subject to the control of RISEND signal, the positive pole of voltage source V os1 is connected with the positive pole of the voltage source that produces reference voltage V ref, the negative pole of voltage source V os1 is connected with the grid of M16, and the voltage Vref ' at the grid place of M16 is the reference voltage after adjusting.
In the time that differential amplifier circuit 21 does not receive RISEND signal, represent that LDO voltage stabilizer 2 is in starting state, switch opens, the reference voltage V ref ' after adjustment equals reference voltage V ref and deducts the voltage of voltage source V os1.In the time that differential amplifier circuit 21 receives RISEND signal, the starting state of expression LDO voltage stabilizer 2 finishes and in normal operating conditions, switch cuts out, and the reference voltage V ref ' after adjustment equals reference voltage V ref.Like this, due in the time that LDO voltage stabilizer 2 starts, the target voltage of output voltage V out is set for and is less than final goal voltage, even if therefore overshoot phenomenon occurs output voltage V out, voltage when its overshoot is also less than final goal voltage, thereby has avoided the problem causing because of overshoot.After 2 startups of LDO voltage stabilizer finish, the target voltage of output voltage V out is got back to final goal voltage, controls by differential amplifier circuit 21, and overshoot phenomenon can not occur output voltage V out.
Herein, use voltage source V os1 to be only used to be convenient to explanation and produce the RISEND signal that circuit 25 produces reference voltage V ref is adjusted based on starting end signal, the represented voltage of voltage source V os1 can be realized by concrete circuit.
The RISEND signal that in like manner, also can produce based on startup end signal generation circuit 25 is adjusted feedback voltage Vfb.Concrete circuit structure will elaborate hereinafter.
(2) start end signal and produce circuit 25
As shown in Figure 2, starting end signal generation circuit 25 is connected with differential amplifier circuit 21, for when the start-up course of LDO voltage stabilizer 2 finishes, produce RISEND signal according to the voltage changing with start-up course in differential amplifier circuit 21, and keeping this RISEND signal, the time point that the time point that RISEND signal produces finishes with start-up course is corresponding.
In addition, as shown in Figure 2, starting end signal generation circuit 25 can be input to the RISEND signal of generation in differential amplifier circuit 21 and/or feedback circuit 23.
Illustrate the circuit structure that produces circuit 25 according to the startup end signal of the first embodiment of the present invention below with reference to Fig. 3 to Fig. 5.
Start end signal produce circuit 25 comprise metal-oxide-semiconductor field effect transistor M1～M5, resistance R 1 or door OR, with door AND and reverser INV, wherein M1～M4 is PMOS field effect transistor, M5 is NMOS field effect transistor.The source electrode of M1 is connected with the grid of the M12 (final stage metal-oxide-semiconductor field effect transistor) of differential amplifier circuit 21, and the drain electrode of M1 is connected with the grid of the drain electrode of M2 and M3, the grid of M1 with or door OR output terminal be connected.The source electrode of M2 is connected with direct supply, and the grid of M2 is connected with switching signal EN.The source electrode of M3 is connected with direct supply after being connected with the source electrode of M4, after the drain electrode of M3 is connected with the drain electrode of M4, is connected with the first end of resistance R 1 and with the first input end of door AND.The grid of M4 is connected with the output terminal of reverser INV and the grid of M5.The source ground of M5, the drain electrode of M5 is connected with the second end of resistance R 1.Or the first input end of door OR is connected with phase-veversal switch signal ENB, or the second input end of OR be connected with the output terminal of door AND.Be connected with switching signal EN with the second input end of door AND, with the output terminal output RISEND signal of door AND.The input end of reverser INV be connected with the output terminal of door AND.Switching signal EN is the signal of instigating LDO voltage stabilizer energising of the present invention, and phase-veversal switch signal ENB is to the signal after switching signal EN negate.
The startup end signal according to the first embodiment of the present invention showing below in conjunction with Fig. 3 to Fig. 5 produces the circuit structure of circuit 25, and the principle that RISEND signal produces is described.
In the time that LDO voltage stabilizer 2 is before starting state, the voltage Va at the grid place of M12 equals the voltage Vdd of direct supply, and phase-veversal switch signal ENB is high level, M1 cut-off, switching signal EN is low level, M2 conducting, the voltage Vb at the grid place of M3 uprises, M3 cut-off, AND is output as low level with door, phase inverter INV is output as high level, M4 cut-off, M5 conducting.Now, RISEND signal as with the output of door AND, be low level, represent not yet to produce RISEND signal.
In the time that LDO voltage stabilizer 2 is in starting state, switching signal EN becomes high level, and phase-veversal switch signal ENB becomes low level, or door OR is output as low level, M1 conducting, M2 cut-off, the voltage Vb that the voltage Va at the grid place of M12 equals the grid place of M3 is high level, M3 cut-off, AND is output as low level with door, phase inverter INV is output as high level, M4 cut-off, M5 conducting.Now, RISEND signal as with the output of door AND, be low level, represent not yet to produce RISEND signal.
When LDO voltage stabilizer 2 is in the time that starting state finishes, the voltage Va step-down at the grid place of M12, the voltage Vb at the grid place of M3 equals the voltage Va at the grid place of M12, voltage between grid and the source electrode of M3 is greater than the threshold voltage of M3, M3 conducting, the voltage Vc of drain electrode place of M3 uprises, and switching signal EN is high level, and AND is output as high level with door.Now, RISEND signal as with the output of door AND, be high level, represent to produce RISEND signal.
Once produce RISEND signal, when RISEND signal becomes high level, M1 cut-off, M4 conducting, M5 cut-off, the high level state of RISEND signal is kept.
The circuit structure that starts end signal generation circuit 25 is not limited to the concrete structure shown in Fig. 3 to Fig. 5, all can be used as the startup end signal generation circuit 25 in the present invention as long as can realize the circuit structure of " when the start-up course of LDO voltage stabilizer finishes; produce RISEND signal according to the voltage changing with start-up course in differential amplifier circuit; and keep this RISEND signal, the time point that the time point that RISEND signal produces finishes with start-up course is corresponding " this function.
After producing, RISEND signal can be imported in differential amplifier circuit 21 and/or feedback circuit 23, in order to the parameter of some devices in differential amplifier circuit 21 and/or feedback circuit 23 is adjusted.The capacity of for example, speed-up capacitor in the reference voltage V ref that, can produce the external voltage source being input in differential amplifier circuit 21, feedback voltage Vfb and the feedback circuit that feedback circuit 23 is exported etc. is adjusted.About the adjustment of above-mentioned parameter, in to the specific descriptions of differential amplifier circuit 21 and feedback circuit 23, provide detailed explanation.
(3) current-limiting circuit 24
As shown in Figure 2, be connected with current-limiting circuit 24 at the input end of output-stage circuit 22, this current-limiting circuit 24, is controlled output-stage circuit 22, to limit the output current of output-stage circuit 22 in starting state in the situation that at LDO voltage stabilizer 2.
Illustrate according to the circuit structure of the current-limiting circuit 24 of the first embodiment of the present invention below with reference to Fig. 3 to Fig. 5.
As shown in Figures 3 to 5, current-limiting circuit 24 comprises metal-oxide-semiconductor field effect transistor M6, M7, M9, M10 and M11, and variable resistor R2, and wherein M6, M10 and M11 are PMOS field effect transistor, and M7 and M9 are NMOS field effect transistor.The source electrode of M11 is connected with direct supply, and the drain electrode of M11 is connected with the source electrode of M10, and the grid of M11 is connected with the drain electrode of M6 and output-stage circuit 22.The grid input of M10 has the bias voltage of himself, and the drain electrode of M10 is connected with the grid of drain electrode and M7 with the grid of M9.The source electrode of M6 is connected with direct supply after being connected with variable-resistance first end, and the grid of M6 is connected with the second end of variable resistor R2 and the drain electrode of M7.The source ground of M7 and M9.M6 is the final stage metal-oxide-semiconductor field effect transistor of current-limiting circuit 24.The circuit structure of current-limiting circuit 24 is not limited to the concrete structure shown in Fig. 3 to Fig. 5, all can be used as the current-limiting circuit 24 in the present invention as long as can realize the circuit structure of " at LDO voltage stabilizer in starting state in the situation that; output-stage circuit is controlled, to limit the output current of output-stage circuit " this function.
(4) output-stage circuit 22
As shown in Figure 2, the input end of output-stage circuit 22 is connected with differential amplifier circuit 21 and current-limiting circuit 24, for when LDO voltage stabilizer 2 is during in normal operating conditions, under the control of differential amplifier circuit 21, the output voltage V out of stable output, when LDO voltage stabilizer 2 is during in starting state, under the control of current-limiting circuit 24, limit its output current.
Illustrate according to the circuit structure of the output-stage circuit 22 of the first embodiment of the present invention below with reference to Fig. 3 to Fig. 5.
As shown in Figures 3 to 5, output-stage circuit 22 comprises metal-oxide-semiconductor field effect transistor M17, and M17 is PMOS field effect transistor.The source electrode of M17 is connected with direct supply.The grid of M11 and the drain electrode of M6 in drain electrode and the current-limiting circuit 24 of the grid Pgate of M17 and the M12 in differential amplifier circuit 21 are connected.The drain electrode of M17 is connected with feedback circuit 23 and output voltage V out.The circuit structure of output-stage circuit 22 is not limited to the concrete structure shown in Fig. 3 to Fig. 5, all can be used as the output-stage circuit 22 in the present invention as long as can realize the circuit structure of " when LDO voltage stabilizer 2 is during in normal operating conditions; under the control of differential amplifier circuit 21; the output voltage V out of stable output; when LDO voltage stabilizer 2 is during in starting state; under the control of current-limiting circuit 24, limit its output current " this function.
(5) feedback circuit 23
As shown in Figure 2, the input end of feedback circuit 23 is connected with the output terminal of output-stage circuit 22, and feedback circuit 22 is for feeding back to the output voltage of output-stage circuit 22 normal phase input end of differential amplifier circuit 21.
In addition, as shown in Figure 2, starting end signal generation circuit 25 can input to the RISEND signal of generation in feedback circuit 23, so that feedback circuit 23 is adjusted the parameter of some device according to RISEND signal, such as adjusting the capacity of speed-up capacitor 231 in feedback circuit 23, or can adjust etc. the feedback voltage Vfb of its generation.
Illustrate according to the circuit structure of the feedback circuit 23 of the first embodiment of the present invention below with reference to Fig. 3 to Fig. 5.
As shown in Figure 3, feedback circuit 23 comprises resistance R 3 and R4 and speed-up capacitor 231.After resistance R 3 and speed-up capacitor 231 is in parallel, one end are connected with the drain electrode of the M17 in output-stage circuit 22, the other end ground connection afterwards of connecting with resistance R 4.The voltage Vfb of the tie point between resistance R 3 and resistance R 4 is imported into the grid of the M15 in differential amplifier circuit 21 as feedback voltage.The circuit structure of feedback circuit 23 is not limited to the concrete structure shown in Fig. 3, all can be used as the feedback circuit 23 in the present invention as long as can realize the circuit structure of " normal phase input end that the output voltage of output-stage circuit is fed back to differential amplifier circuit " this function.For example, feedback circuit 23 can only comprise resistance R 3 and R4 and not comprise speed-up capacitor 231.
For feedback circuit 23, at LDO voltage stabilizer 2 in normal operating conditions, in order to ensure phase place, reduce output noise, need the speed-up capacitor 231 of larger capacity, and at LDO voltage stabilizer 2 in starting state, in order to ensure less start-up time, need compared with the speed-up capacitor of low capacity 231.In order to address this problem, the RISEND signal that we can produce based on startup end signal generation circuit 25 is adjusted the capacity of the speed-up capacitor 231 comprising in feedback circuit 23.
Fig. 4 and Fig. 5 have shown the example based on starting end signal and produce the circuit structure of the feedback circuit 23 that the RISEND signal that produces of circuit 25 adjusts the capacity of speed-up capacitor 231.As shown in Figure 4 and Figure 5, the speed-up capacitor 231 in feedback circuit 23 further comprises capacitor C 1 and C2, and metal-oxide-semiconductor field effect transistor M18, and M18 is NMOS field effect transistor.Capacitor C 2 is in parallel with capacitor C 1 after connecting with M18, tie point between capacitor C 1 and capacitor C 2 is connected with the drain electrode of M17, between capacitor C 1 and the source electrode of M18, tie point is connected with the tie point between resistance R 3 and resistance R 4, and the grid input of M18 has RISEND signal.
In the time that feedback circuit 23 does not receive RISEND signal, represent that LDO voltage stabilizer 2 is in starting state, M18 cut-off, the capacity of speed-up capacitor 231 equals the capacity of capacitor C 1.In the time that feedback circuit 23 receives RISEND signal, the starting state that represents LDO voltage stabilizer 2 finishes and in normal operating conditions, and the capacity that the capacity of speed-up capacitor 231 equals capacitor C 1 adds the capacity of capacitor C 2.Like this, with regard to making feedback circuit 23 to ensure phase place and reduce output noise in normal operating conditions at LDO voltage stabilizer 2, can in starting state, ensure less start-up time at LDO voltage stabilizer 2 again.
In addition, hereinbefore, mention in the start-up course of LDO voltage stabilizer 2, in the time that the output voltage V out of LDO voltage stabilizer 2 rises to target voltage, because expended the reflecting time of differential amplifier circuit 21, charging current can not terminate in external capacitive, and therefore overshoot phenomenon occurs output voltage V out sometimes.For fear of this overshoot phenomenon, the RISEND signal that we can produce based on startup end signal generation circuit 25 is adjusted feedback voltage Vfb.
The example of the circuit structure of the feedback circuit 23 that the RISEND signal producing based on startup end signal generation circuit 25 below with reference to Fig. 4 explanation is adjusted feedback voltage Vfb.As shown in Figure 4, feedback circuit 23 is except comprising the resistance R 3 shown in Fig. 3 and Fig. 5 and R4 and speed-up capacitor 231, feedback circuit 23 also comprises feedback voltage Circuit tuning 232, and feedback voltage Vfb feedback circuit 23 being produced for the RISEND signal producing according to startup end signal generation circuit 25 is adjusted.The switch that feedback voltage Circuit tuning 232 comprises voltage source V os2 and is in parallel with voltage source V os2, the opening/closing of switch is subject to the control of RISEND signal, the positive pole of voltage source V os2 is connected to the grid of the M15 in differential amplifier circuit 21, the negative pole of voltage source V os2 is connected to the tie point between resistance R 3 and resistance R 4, and the voltage Vfb ' at the grid place of M15 is the feedback voltage after adjusting.
In the time that feedback circuit 23 does not receive RISEND signal, represent that LDO voltage stabilizer 2 is in starting state, switch opens, the feedback voltage Vfb after adjustment ' equal feedback voltage Vfb and add the voltage of voltage source V os2.In the time that feedback circuit 23 receives RISEND signal, the starting state that represents LDO voltage stabilizer 2 finishes and in normal operating conditions, switch cuts out, the feedback voltage Vfb after adjustment ' equal feedback voltage Vfb.Like this, can in the time that LDO voltage stabilizer 2 start, the target voltage of output voltage V out be set for and be less than final goal voltage equally, and after 2 startups of LDO voltage stabilizer finish, make the target voltage of output voltage V out get back to final goal voltage, thereby avoided the problem causing because of overshoot.
Herein, use voltage source V os2 to be only used to be convenient to explanation and produce the RISEND signal that circuit 25 produces feedback voltage Vfb is adjusted based on starting end signal, the represented voltage of voltage source V os2 can be realized by concrete circuit.
In addition,, if the feedback voltage Circuit tuning 232 in feedback circuit 23 is set in differential amplifier circuit, also can reach identical effect.
The second embodiment
The example of the LDO voltage stabilizer from current-limiting circuit generation RISEND signal is according to a second embodiment of the present invention described below with reference to Fig. 6 and Fig. 7.Fig. 6 has shown the structural representation of LDO voltage stabilizer according to a second embodiment of the present invention.Fig. 7 has shown according to the partial circuit diagram of the LDO voltage stabilizer of the first embodiment of the present invention.
As shown in Figure 6, the structure of the LDO voltage stabilizer 2 of the first embodiment shown in structure and Fig. 2 of the LDO voltage stabilizer 3 of the second embodiment of the present invention is basic identical, its difference only exists: in the first embodiment, start end signal and produce circuit 25 according to the voltage generation RISEND signal in differential amplifier circuit, and in a second embodiment, start end signal and produce circuit 35 according to the voltage generation RISEND signal in current-limiting circuit.
Due to the circuit structure of the differential amplifier circuit 31 in the second embodiment, output-stage circuit 32 and feedback circuit 33, identical with the circuit structure of differential amplifier circuit 21, output-stage circuit 22 and feedback circuit 23 in the first embodiment, therefore, omitted its related description at this.
Illustrate current-limiting circuit 34 according to a second embodiment of the present invention and start end signal the circuit structure that produces circuit 35 below with reference to Fig. 6 and Fig. 7.
(1) current-limiting circuit 34
As shown in Figure 6, be connected with current-limiting circuit 34 at the input end of output-stage circuit 32, this current-limiting circuit 34, is controlled output-stage circuit 32, to limit the output current of output-stage circuit 32 in starting state in the situation that at LDO voltage stabilizer 3.
In addition, as shown in Figure 6, current-limiting circuit 34 also produces circuit 35 with startup end signal and is connected, and produces circuit 35 when the start-up course of LDO voltage stabilizer 3 finishes so that start end signal, according to the voltage generation RISEND signal changing with start-up course in current-limiting circuit 34.
As shown in Figure 7, the circuit structure of current-limiting circuit 34 is according to a second embodiment of the present invention with basic identical according to the circuit structure of the current-limiting circuit 24 of the first embodiment of the present invention, distinguish and be only, current-limiting circuit 34 has according to a second embodiment of the present invention increased a NMOS field effect transistor M8.
As shown in Figure 7, current-limiting circuit 34 comprises metal-oxide-semiconductor field effect transistor M6, M7, M8, M9, M10 and M11, and variable resistor R2, and wherein M6, M10 and M11 are PMOS field effect transistor, and M7, M8 and M9 are NMOS field effect transistor.The source electrode of M11 is connected with direct supply, and the drain electrode of M11 is connected with the source electrode of M10, and the grid of M11 is connected with the drain electrode of M6 and output-stage circuit 22.The grid input of M10 has the bias voltage of himself, and the drain electrode of M10 is connected with the grid of drain electrode and M7 with the grid of M9.The source electrode of M6 is connected with direct supply after being connected with variable-resistance first end, and the grid of M6 is connected with the second end of variable resistor R2 and the drain electrode of M7.The source ground of M9, the source electrode of M7 is connected with the drain electrode of M8, the source ground of M8, the grid of M8 is connected with switching signal EN.M6 is the final stage metal-oxide-semiconductor field effect transistor of current-limiting circuit 34.The circuit structure of current-limiting circuit 34 is not limited to the concrete structure shown in Fig. 7, also can adopt the circuit structure in Fig. 3 to Fig. 5, or the circuit structure of this function that other can realize " at LDO voltage stabilizer in starting state in the situation that; output-stage circuit is controlled, to limit the output current of output-stage circuit ".
In the present invention, as shown in Figure 7, M6 is the final stage metal-oxide-semiconductor field effect transistor of current-limiting circuit 34, the voltage Va ' at the grid place of M6 is the voltage changing with start-up course when the start-up course of LDO voltage stabilizer 3 finishes in current-limiting circuit 34, therefore, start end signal generation circuit 25 and can produce RISEND signal according to this voltage Va '.
In the time that LDO voltage stabilizer 3 is before starting and in start-up course, the voltage Va at the grid place of M6 is low-voltage, and the voltage between source electrode and the grid of M6 is greater than the threshold voltage of M6, M6 conducting, and current-limiting circuit 34 is started working.When LDO voltage stabilizer 2 is in the time that start-up course finishes, the voltage Va ' at the grid place of M6 uprises, M6 conducting, and current-limiting circuit 34 is in high-impedance state.Therefore, the voltage Va ' at the grid place of the final stage metal-oxide-semiconductor field effect transistor M6 in current-limiting circuit 34 is the voltage changing with start-up course when the start-up course of LDO voltage stabilizer 3 finishes in current-limiting circuit 34.
In the present invention, although the example for generation of the voltage of RISEND signal in using the voltage Va ' at the grid place of final stage metal-oxide-semiconductor field effect transistor M6 as current-limiting circuit 34 describes, but, in current-limiting circuit, can be not limited to for generation of the voltage of RISEND signal the voltage at the grid place of the final stage metal-oxide-semiconductor field effect transistor of current-limiting circuit.For example, when because of needs the M6 of current-limiting circuit 34 increase again what metal-oxide-semiconductor field effect transistor below time, the voltage at the grid place of the final stage metal-oxide-semiconductor field effect transistor newly increasing, or the voltage at the grid place of M6 all can be used as the voltage for generation of RISEND signal.That is to say, in current-limiting circuit, all can be used as the voltage for generation of RISEND signal as long as meet at the voltage of " start-up course of LDO voltage stabilizer changes with start-up course in finishing " this condition.
(2) start end signal and produce circuit 35
As shown in Figure 6, starting end signal generation circuit 35 is connected with current-limiting circuit 34, for when the start-up course of LDO voltage stabilizer 3 finishes, produce RISEND signal according to the voltage changing with start-up course in current-limiting circuit 34, and keeping this RISEND signal, the time point that the time point that RISEND signal produces finishes with start-up course is corresponding.
In addition, as shown in Figure 6, with identical in the first embodiment, starting end signal generation circuit 35 can be input to the RISEND signal of generation in differential amplifier circuit 31 and/or feedback circuit 33.
Illustrate the circuit structure of startup end signal generation circuit 35 according to a second embodiment of the present invention below with reference to Fig. 7.
Start end signal generation circuit 35 and comprise metal-oxide-semiconductor field effect transistor M1 '～M4 ', resistance R 1 ', Sheffer stroke gate NAND, reverser INV ' and current source Is ', wherein M1 ' and M4 ' are PMOS field effect transistor, and M2 ' and M3 ' are NMOS field effect transistor.The source electrode of M1 ' is connected with direct supply, and the drain electrode of M1 ' is connected with the first end of resistance R 1 ', and the grid of M1 ' is connected with phase-veversal switch signal ENB.The source electrode of M2 ' is connected with the drain electrode of M3 ', and the drain electrode of M2 ' is connected with the first input end of Sheffer stroke gate NAND with the second end of resistance R 1 ', and the grid of M2 ' is connected with the input end of reverser INV ' with the output terminal of Sheffer stroke gate NAND.The source ground of M3 ', the grid of M3 ' is connected with the first end of current source Is ' with the drain electrode of M4 '.The source electrode of M4 ' is connected with direct supply, and the grid of M4 ' is connected with the grid of the M6 (final stage metal-oxide-semiconductor field effect transistor) of current-limiting circuit 34.The second end ground connection of current source Is ', the second input end of Sheffer stroke gate NAND is connected with switching signal EN, the output terminal output RISEND signal of reverser INV '.
Here, current source Is ' provides bias current for producing circuit 35 at startup end signal, also can replace with other circuit blocks such as metal-oxide-semiconductor field effect transistor etc.
Switching signal EN is the signal that instruction makes LDO voltage stabilizer energising of the present invention, and phase-veversal switch signal ENB is to the signal after switching signal EN negate.
The startup end signal according to a second embodiment of the present invention showing below in conjunction with Fig. 7 produces the circuit structure of circuit 35, and the principle that RISEND signal produces is described.
In the time that LDO voltage stabilizer 3 is before starting state, the voltage Va ' that the voltage at the grid place of M4 ' equals the grid place of M6 is low-voltage, M4 ' conducting; Because the electric current of current source Is ' is less, therefore the voltage Vb ' at the grid place of M3 ' is high voltage, M3 ' conducting; Phase-veversal switch signal ENB is high level, M1 ' cut-off; Switching signal EN is low level, and Sheffer stroke gate NAND is output as high level, M2 ' conducting, and phase inverter INV ' is output as low level.Now, RISEND signal, as the output of phase inverter INV ', is low level, represents not yet to produce RISEND signal.
In the time that LDO voltage stabilizer 3 is in starting state, the voltage Va ' that the voltage at the grid place of M4 ' equals the grid place of M6 is low-voltage, M4 ' conducting; Because the electric current of current source Is ' is less, therefore the voltage Vb ' at the grid place of M3 ' is high voltage, M3 ' conducting; Phase-veversal switch signal ENB becomes low level, M1 ' conducting; Switching signal EN becomes high level, and the voltage Vc ' of the input end except switching signal EN of Sheffer stroke gate NAND is low-voltage, and Sheffer stroke gate NAND is output as high level, M2 ' conducting, and phase inverter INV ' is output as low level.Now, RISEND signal, as the output of phase inverter INV ', is low level, represents not yet to produce RISEND signal.
When LDO voltage stabilizer 3 is in the time that starting state finishes, the voltage Va ' that the voltage at the grid place of M4 ' equals the grid place of M6 uprises, M4 ' cut-off, and the voltage Vb ' at the grid place of M3 ' is ground, M3 ' cut-off; The voltage Vc ' of the input end except switching signal EN of Sheffer stroke gate NAND uprises because of the existence of pull-up resistor R1 ', and two of not gate NAND inputs are all high level, and it is output as low level, and phase inverter INV ' is output as high level.Now, RISEND signal, as the output of phase inverter INV ', is high level, represents to produce RISEND signal.
Once produce RISEND signal, when RISEND signal becomes high level, M2 ' cut-off, the high level state of RISEND signal is kept.
The circuit structure that starts end signal generation circuit 35 is not limited to the concrete structure shown in Fig. 7, all can be used as the startup end signal generation circuit 35 in the present invention as long as can realize the circuit structure of " when the start-up course of LDO voltage stabilizer finishes; produce RISEND signal according to the voltage changing with start-up course in current-limiting circuit; and keep this RISEND signal, the time point that the time point that RISEND signal produces finishes with start-up course is corresponding " this function.
After producing, RISEND signal can be imported in differential amplifier circuit 31 and/or feedback circuit 33, in order to the parameter of some devices in differential amplifier circuit 31 and/or feedback circuit 33 is adjusted.The capacity of for example, speed-up capacitor in the reference voltage V ref that, can produce the external voltage source being input in differential amplifier circuit 31, feedback voltage Vfb and the feedback circuit that feedback circuit 33 is exported etc. is adjusted.About the adjustment of above-mentioned parameter, in the first embodiment, provide detailed explanation, therefore omit its description at this.
LDO voltage stabilizer of the present invention is owing to can producing RISEND signal, therefore, not only can improve beyond self performance some device parameters adjustment in self circuit, but also can be applied in a lot of circuit structures, below in conjunction with Fig. 8 to Figure 11, several application of LDO voltage stabilizer of the present invention are once described:
(1) inrush current limitation
In the time that LDO voltage stabilizer starts, sometimes need to limit especially the starting current of LDO voltage stabilizer.But, for the LDO voltage stabilizer of prior art, owing to not knowing the startup end time of LDO voltage stabilizer, therefore, also need delay circuit is set in addition at the control circuit of the starting current for limiting LDO voltage stabilizer, thereby cause the complex structure of control circuit.
Fig. 8 (A) has shown the sequential chart that the starting current of the LDO voltage stabilizer of control circuit to prior art is controlled.In Fig. 8, EN represents to make the switching signal of LDO voltage stabilizer energising, and SHTEST represents the current limiting signal that the starting current to LDO voltage stabilizer of control circuit output limits, and VOUT represents the output voltage of LDO voltage stabilizer.As can be seen from Figure 8, owing to not knowing the startup end time of LDO voltage stabilizer, therefore, control circuit need to be preset for example delay time of 200 μ s to the SHTEST signal of output, thereby causes control circuit because the complex structure that delay circuit causes need to be set in addition.
But, for LDO voltage stabilizer of the present invention, owing to can producing startup end signal, therefore, in the time needing the starting current of special restriction LDO, in control circuit, do not need delay circuit is set in addition, thereby simplified control circuit.
Fig. 8 (B) has shown the sequential chart that control circuit is controlled the starting current of LDO voltage stabilizer of the present invention.As can be seen from Figure 9, because LDO voltage stabilizer of the present invention has produced RISEND signal, that is to say, can know the startup end time of LDO voltage stabilizer, therefore, control circuit does not need the default delay time of the SHTEST signal of output, once produce RISEND signal, control circuit just stops the control to starting current.Therefore, in control circuit, do not need delay circuit is set in addition, thereby simplified control circuit.
(2) startup of the LDO voltage stabilizer in composite power source module
In composite power source module, if adopt the LDO voltage stabilizer of prior art, in the time starting multiple LDO voltage stabilizer, owing to not knowing the startup end time of each LDO voltage stabilizer, therefore, need in startup sequential circuit, increase delay circuit, thereby cause the complex structure that starts sequential circuit, in addition, the overall startup time of multiple LDO voltage stabilizers is also longer.
Fig. 9 (A) has shown the sequential chart that the LDO voltage stabilizer of multiple prior aries starts in composite power source module.In Figure 10, LDO1～LDOx represents the output voltage of LDO1～LDOx voltage stabilizer.As shown in figure 10, owing to not knowing the startup end time of each LDO voltage stabilizer, therefore, the startup clock signal that starts sequential circuit output need to be to the default delay time start-up time of each LDO voltage stabilizer, for example, arranged to the delay time of 50 μ s the start-up time of LDO1, arranged to the delay time of 60 μ s the start-up time of LDO2, arranged to delay time of 50 μ s etc. the start-up time of LDO3.That is to say, even if LDO1 has started end in 50 μ s, after the delay time past of the 50 μ s that also must by the time arrange, can make LDO2 start.Like this, not only cause the complex structure that starts sequential circuit, and the overall startup time of multiple LDO voltage stabilizers is also longer.
But, in composite power source module, if adopt LDO voltage stabilizer of the present invention, in the time starting multiple LDO voltage stabilizer, owing to knowing the startup end time of each LDO voltage stabilizer, therefore, need in startup sequential circuit, not increase delay circuit, thereby simplify the structure that starts sequential circuit, in addition, also can greatly shorten the overall startup time of multiple LDO voltage stabilizers.
Fig. 9 (B) has shown the sequential chart that multiple LDO voltage stabilizers of the present invention start in composite power source module.As shown in figure 11, owing to knowing the startup end time of each LDO voltage stabilizer, therefore, the startup clock signal that starts sequential circuit output does not need default delay time, finishes just to make LDO2 to start once LDO1 starts.Like this, not only can simplify the structure that starts sequential circuit, and can greatly shorten the overall startup time of multiple LDO voltage stabilizers.
Although through the present invention is described in conjunction with specific embodiments, for those skilled in the art, will be apparent according to manyly substituting of making after narration above, amendment with variation.Therefore,, during when such substituting, within spirit and scope that modifications and variations fall into attached claim, should be included in the present invention.
Claims (10)
1. a low pressure difference linear voltage regulator, comprises differential amplifier circuit, output-stage circuit, feedback circuit and current-limiting circuit, wherein:
The normal phase input end of described differential amplifier circuit is connected with the output terminal of described feedback circuit, the inverting input input of described differential amplifier circuit has reference voltage, and the output terminal of described differential amplifier circuit and the input end of described output-stage circuit are connected; Be connected with described current-limiting circuit at the input end of described output-stage circuit; The input end of described feedback circuit is connected with the output terminal of described output-stage circuit;
Described differential amplifier circuit, is controlled described output-stage circuit by described feedback circuit, so that the output voltage of described output-stage circuit stable output in normal operating conditions in the situation that at described low pressure difference linear voltage regulator;
Described current-limiting circuit, is controlled described output-stage circuit, to limit the output current of described output-stage circuit in starting state in the situation that at described low pressure difference linear voltage regulator;
It is characterized in that, described low pressure difference linear voltage regulator further comprises that starting end signal produces circuit, described startup end signal produces circuit and is connected with described differential amplifier circuit, or be connected with described current-limiting circuit, for when the start-up course of described low pressure difference linear voltage regulator finishes, produce and start end voltage signal according to the voltage changing with described start-up course in described differential amplifier circuit or described current-limiting circuit, and keep described startup end voltage signal, the time point that described startup end voltage signal produces is corresponding with the time point that described start-up course finishes.
2. low pressure difference linear voltage regulator as claimed in claim 1, is characterized in that, described startup end signal produces circuit the described startup end voltage signal producing is inputed to described feedback circuit.
3. low pressure difference linear voltage regulator as claimed in claim 2, is characterized in that, described feedback circuit comprises speed-up capacitor, and described feedback circuit, according to described startup end voltage signal, is adjusted the capacity of described speed-up capacitor;
In the time that described feedback circuit receives described startup end voltage signal, described feedback circuit is adjusted to the second capacity by the capacity of described speed-up capacitor from the first capacity;
The capability value of described the first capacity is less than the capability value of described the second capacity.
4. low pressure difference linear voltage regulator as claimed in claim 2, is characterized in that, described feedback circuit, according to described startup end voltage signal, is adjusted the feedback voltage of its output;
In the time that described feedback circuit receives described startup end voltage signal, described feedback circuit is adjusted to second voltage by described feedback voltage from the first voltage;
The magnitude of voltage of described the first voltage is greater than the magnitude of voltage of described second voltage.
5. low pressure difference linear voltage regulator as claimed in claim 1, is characterized in that, described startup end signal produces circuit the described startup end voltage signal producing is inputed to described differential amplifier circuit.
6. low pressure difference linear voltage regulator as claimed in claim 5, is characterized in that, described differential amplifier circuit, according to described startup end voltage signal, is adjusted the described reference voltage of input;
In the time that described differential amplifier circuit receives described startup end voltage signal, described differential amplifier circuit is adjusted to second voltage by described reference voltage from the first voltage;
The magnitude of voltage of described the first voltage is less than the magnitude of voltage of described second voltage.
7. the low pressure difference linear voltage regulator as described in any one in claim 1-6, it is characterized in that, described differential amplifier circuit comprises final stage metal-oxide-semiconductor field effect transistor, when described startup end signal generation circuit is connected with the grid of the final stage metal-oxide-semiconductor field effect transistor of described differential amplifier circuit, the voltage that described startup end signal produces the grid of the described final stage metal-oxide-semiconductor field effect transistor changing with described start-up course when circuit finishes according to the start-up course of described low pressure difference linear voltage regulator produces described startup end voltage signal.
8. low pressure difference linear voltage regulator as claimed in claim 7, it is characterized in that, described startup end signal produce circuit comprise the first metal-oxide-semiconductor field effect transistor, the second metal-oxide-semiconductor field effect transistor, the 3rd metal-oxide-semiconductor field effect transistor, the 4th metal-oxide-semiconductor field effect transistor, the 5th metal-oxide-semiconductor field effect transistor, resistance or door, with door and reverser, wherein
The source electrode of described the first metal-oxide-semiconductor field effect transistor is connected with the grid of described final stage metal-oxide-semiconductor field effect transistor, the drain electrode of described the first metal-oxide-semiconductor field effect transistor is connected with the grid of described the 3rd metal-oxide-semiconductor field effect transistor with the drain electrode of described the second metal-oxide-semiconductor field effect transistor, and the grid of described the first metal-oxide-semiconductor field effect transistor is connected with output terminal described or door;
The source electrode of described the second metal-oxide-semiconductor field effect transistor is connected with direct supply, and the grid of described the second metal-oxide-semiconductor field effect transistor is connected with switching signal;
After the source electrode of described the 3rd metal-oxide-semiconductor field effect transistor is connected with the source electrode of described the 4th metal-oxide-semiconductor field effect transistor, be connected with described direct supply, after the drain electrode of described the 3rd metal-oxide-semiconductor field effect transistor is connected with the drain electrode of described the 4th metal-oxide-semiconductor field effect transistor, be connected with the first input end of door with described with the first end of described resistance;
Described the 4th grid of metal-oxide-semiconductor field effect transistor and the output terminal of described reverser are connected with the grid of described the 5th metal-oxide-semiconductor field effect transistor;
The source ground of described the 5th metal-oxide-semiconductor field effect transistor, the drain electrode of described the 5th metal-oxide-semiconductor field effect transistor is connected with the second end of described resistance;
First input end described or door is connected with phase-veversal switch signal, and the second input end described or door is connected with the output terminal of door with described;
Describedly be connected with described switching signal with the second input end of door, the output terminal output startup end voltage signal of described and door;
The input end of described reverser is connected with the output terminal of door with described;
Described first, second, third and the 4th metal-oxide-semiconductor field effect transistor be PMOS field effect transistor, described the 5th metal-oxide-semiconductor field effect transistor is NMOS field effect transistor.
9. the low pressure difference linear voltage regulator as described in any one in claim 1-6, it is characterized in that, described current-limiting circuit comprises final stage metal-oxide-semiconductor field effect transistor, in the time that described startup end signal generation circuit is connected with described current-limiting circuit, the voltage that described startup end signal produces the grid of the described final stage metal-oxide-semiconductor field effect transistor changing with described start-up course when circuit finishes according to the start-up course of described low pressure difference linear voltage regulator produces described startup end voltage signal.
10. low pressure difference linear voltage regulator as claimed in claim 9, it is characterized in that, described startup end signal produces circuit and comprises the first metal-oxide-semiconductor field effect transistor, the second metal-oxide-semiconductor field effect transistor, the 3rd metal-oxide-semiconductor field effect transistor, the 4th metal-oxide-semiconductor field effect transistor, resistance, Sheffer stroke gate, reverser and current source, wherein
The source electrode of described the first metal-oxide-semiconductor field effect transistor is connected with direct supply, and the drain electrode of described the first metal-oxide-semiconductor field effect transistor is connected with the first end of described resistance, and the grid of described the first metal-oxide-semiconductor field effect transistor is connected with phase-veversal switch signal;
The source electrode of described the second metal-oxide-semiconductor field effect transistor is connected with the drain electrode of described the 3rd metal-oxide-semiconductor field effect transistor, the drain electrode of described the second metal-oxide-semiconductor field effect transistor is connected with the second end of described resistance and the first input end of described Sheffer stroke gate, and the grid of described the second metal-oxide-semiconductor field effect transistor is connected with the input end of the output terminal of described Sheffer stroke gate and described reverser;
The source ground of described the 3rd metal-oxide-semiconductor field effect transistor, the grid of described the 3rd metal-oxide-semiconductor field effect transistor is connected with described the 4th drain electrode of metal-oxide-semiconductor field effect transistor and the first end of described current source;
The source electrode of described the 4th metal-oxide-semiconductor field effect transistor is connected with described direct supply, and the grid of described the 4th metal-oxide-semiconductor field effect transistor is connected with the grid of described final stage metal-oxide-semiconductor field effect transistor;
The second end ground connection of described current source, the second input end of described Sheffer stroke gate is connected with switching signal, and the output terminal output of described reverser starts end voltage signal;
Described first and the 4th metal-oxide-semiconductor field effect transistor be PMOS field effect transistor, described second and the 3rd metal-oxide-semiconductor field effect transistor be NMOS field effect transistor.
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| TWI492016B (en) * | 2013-04-03 | 2015-07-11 | Holtek Semiconductor Inc | Low dropout linear regulator |
| CN103336546B (en) * | 2013-07-20 | 2015-07-22 | 福州大学 | Low-voltage difference voltage stabilizing circuit with current-limiting protection function under double high power supply voltage input |
| CN104423407B (en) * | 2013-08-28 | 2016-05-25 | 联发科技（新加坡）私人有限公司 | Low pressure difference linear voltage regulator and starting method thereof, electronic installation and chip |
| CN105446404B (en) * | 2014-08-19 | 2017-08-08 | 无锡华润上华半导体有限公司 | Low differential voltage linear voltage stabilizer circuit, chip and electronic equipment |
| CN107193313B (en) * | 2016-03-15 | 2019-08-09 | 瑞昱半导体股份有限公司 | Voltage-stablizer |
| CN106227282A (en) * | 2016-07-27 | 2016-12-14 | 中国航天科技集团公司第九研究院第七七研究所 | There is multi-mode and control the high-reliability low-pressure difference linear constant voltage regulator circuit of function |
| JP6793772B2 (en) | 2019-03-13 | 2020-12-02 | 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． | Voltage generator |
| CN111766914B (en) * | 2019-04-01 | 2022-07-05 | 华邦电子股份有限公司 | Voltage generator |
| EP3812872B1 (en) | 2019-10-25 | 2023-06-14 | Nxp B.V. | A system comprising a low drop-out regulator |
| CN113093853B (en) * | 2021-04-15 | 2022-08-23 | 东北大学 | Improved LDO circuit for realizing low input/output voltage difference in low-voltage starting process |
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| CN102650893A (en) | 2012-08-29 |
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