CN1825240A - Low voltage difference linear voltage stabilizer circuit - Google Patents

Abstract

The invention relates to a low voltage linear voltage stabilizer circuit that includes reference voltage circuit, error amplifier, and power output tube and load circuit. The feather is that the output end of load circuit directly connects to the power output tube and feedback to the input positive end of error amplifier. The invention could decrease output noise and improve PSRR. The invention generates a current that is direct ratio to temperature. It could compensate the temperature coefficient of resistance to gain a reference voltage that would not alter following the alteration of resistance. The invention could generate agility alterable reference voltage.

Description

A kind of low differential voltage linear voltage stabilizer circuit

Technical field

The present invention relates to the Analogous Integrated Electronic Circuits technology, relate in particular to a kind of low differential voltage linear voltage stabilizer circuit that reduces output noise and improve Power Supply Rejection Ratio.

Background technology

Low pressure difference linear voltage regulator (LDO; Low Dropout Regulator) is a important branch among the power supply IC; with based on pulse-length modulation (PWM; Pulse Width Modulation), pulse frequency modulation (PFM; Pulse Frequency Modulation) the DC-DC converter of principle is compared, and it has low cost, the little and advantage that need not inductance of low noise and quiescent current; in portable type electronic product, use the power supply of LDO as system through regular meeting.

Fig. 1 is basic LDO circuit, and this LDO circuit is made of reference voltage 101, error amplifier 102, output power pipe 103, dividing potential drop sampling network 104 and load 105.

Reference voltage 101 modules produce a reference voltage that changes with conditions of work such as supply voltage, chip temperatures hardly.The generation of reference voltage 101 is to utilize the PN junction forward conduction voltage V with negative temperature coefficient _BEWith two with positive temperature coefficient (PTC) base-emitter voltage difference delta V that are operated in triode under the different current densities _BEThereby stack compensation according to a certain percentage obtains temperature-independent reference voltage, i.e. a V _REF=V _BE+ KV _TLnN, N are the ratio of two current densities between the triode, V _TBe thermal voltage, K is a selectable constant in design, and the benchmark output voltage that this method obtains is also referred to as bandgap voltage reference (Bandgap Reference) about 1.2V.This bandgap voltage reference production method is difficult to satisfy the needs that produce a reference voltage that can change flexibly.

Dividing potential drop sampling network 104 samplings that the output voltage VO UT of LDO forms by resistance R 1, R2, and with the positive input of this sampled voltage signal feedback to error amplifier EA (Error Amplifier) 102.

The reverse input end of error amplifier EA 102 connects reference voltage, the output VG of error amplifier 102 meets an output power pipe MPX 103 with very big breadth length ratio, when external loading 105 variations make that output voltage VO UT changes, by the positive input of dividing potential drop sampling network 104 sampling feedback to error amplifier EA 102, the output VG of departure amplifier EA 102 changes, thereby the conducting degree of control output power pipe MPX 103 makes the voltage of VOUT remain unchanged.

Load capacitance CL is used for auxiliary control makes that a such closed loop feedback system keeps stablizing under various application conditions situations, RL be LDO output with equivalent load.

In application scenarios such as simulation and radio frequency, for noiseproof feature and the Power Supply Rejection Ratio (PSRR that improves LDO, Power-supply Rejection Ratio), can add a RC filtering circuit 106 at the output terminal of reference voltage 101 modules and the reverse input end of error amplifier EA 102.

From whole angle, the noise source of LDO circuit mainly contains three sources, a noise that produces from reference voltage 101 modules, this noise generally directly has been added to the reverse input end of error amplifier EA102 during as the power supply that to noise is not responsive especially digital display circuit at LDO, simultaneously the PSRR of reference voltage 101 modules also has very big influence to the PSRR of whole LDO, so generally all will add noise and the power supply undesired signal that a RC filtering circuit 106 suppresses the generation of reference voltage 101 modules in simulation and radio frequency etc. require than higher occasion to noise and PSRR.The another one noise source is a dividing potential drop sampling network 104, traditional LDO circuit adopts dividing potential drop sampling network 104 sampling and outputting voltages and sampled voltage is fed back to the positive input of error amplifier EA102, output noise can transfer back to the input end of error amplifier EA102 by dividing potential drop sampling network 104 like this, resistance itself in the dividing potential drop sampling network 104 can produce thermonoise simultaneously, the size of thermonoise is 4kTR, here k is a Boltzmann constant, and T is an absolute temperature, and R is a resistance.When the output voltage of LDO was higher than reference voltage, the noise that two input ends of error amplifier EA102 occur was all amplified in proportion, and output voltage is high more, and magnification ratio is big more.The 3rd place that produces noise is exactly error amplifier EA102 itself, and error amplifier EA102 itself can produce certain noise, and the PSRR of error amplifier EA102 itself can have certain contribution to LDO final output noise and PSRR.

So the LDO circuit major defect of this architecture is:

Even 1 has increased RC filtering circuit 106 after reference voltage 101 modules, but under the output voltage of the LDO situation higher than reference voltage, still can be exaggerated by the noise and the power supply undesired signal that are added in error amplifier EA102 negative terminal after 106 filtering of RC filtering circuit, and output voltage is high more, and it is many more that noise that is produced by reference voltage 101 modules and power supply undesired signal are exaggerated.

2, reduce that sampling resistor can reduce the noise that resistance itself is produced in the dividing potential drop sampling network 104, but can increase the electric current on the sampling resistor when reducing noise, increase the power consumption of total system.

Summary of the invention

The object of the present invention is to provide a kind of low differential voltage linear voltage stabilizer circuit that reduces output noise and improve PSRR.

A kind of low differential voltage linear voltage stabilizer circuit provided by the present invention, constitute by reference voltage circuit, error amplifier EA, output power pipe MPX and load circuit, it is characterized in that: the output terminal of described load circuit directly links to each other with output power pipe MPX, and the output terminal of this load circuit also feeds back to the input positive terminal of error amplifier EA.

In above-mentioned low differential voltage linear voltage stabilizer circuit, also comprise a RC filtering circuit that is connected between described reference voltage circuit and the error amplifier EA.

In above-mentioned low differential voltage linear voltage stabilizer circuit, reference voltage circuit is the current source I that has positive temperature coefficient (PTC) by _PTATWith a current source I with negative temperature coefficient _PTVBEThe resistance R of connecting again after the parallel connection 0 constitutes.

In above-mentioned low differential voltage linear voltage stabilizer circuit, resistance R ₀It is adjustable resistance.

In above-mentioned low differential voltage linear voltage stabilizer circuit, has the current source I of positive temperature coefficient (PTC) _PTATOr has a current source I of negative temperature coefficient _PTVBECircuit comprise that two continuous are basic structure current mirroring circuit and current generating circuit, wherein: current generating circuit is to be 1 by two its area ratios that are connected into the diode form: the substrate PNP transistor Q of N ₁, Q ₂With three resistance R ₁, R ₂, R ₃Constitute.

In above-mentioned low differential voltage linear voltage stabilizer circuit, current mirroring circuit is the basic structure current mirror, and it comprises: two have the NMOS pipe M that sets the characteristic dimension proportionate relationship ₁, M ₂Two have and described NMOS pipe M ₁, M ₂The PMOS pipe M of same characteristic features dimension scale relation ₃, M ₄One and described PMOS pipe M ₃Characteristic dimension is than the PMOS pipe M for a ₅, wherein: a is optional constant.

In above-mentioned low differential voltage linear voltage stabilizer circuit, current mirroring circuit is a cascode structure current mirror (303), and it comprises: two have the NMOS pipe M that sets the characteristic dimension proportionate relationship ₁, M ₂Two have and described NMOS pipe M ₁, M ₂The PMOS pipe M of same characteristic features dimension scale relation ₃, M ₄One and described PMOS pipe M ₃Characteristic dimension is than the PMOS pipe M for a ₅, wherein, wherein: a is optional constant; Two NMOS pipe M6, M7 that have the same characteristic features size with described NMOS pipe M1, M2; And: three PMOS pipe M8, M9 and M10 that have the same characteristic features size with described PMOS pipe and M3, M4, M5.

In above-mentioned low differential voltage linear voltage stabilizer circuit, NMOS manages M ₁, M ₂Characteristic dimension ratio and two resistance R ₂, R ₃Ratio opposite.

Owing to adopted above-mentioned technical solution, can fundamentally reduce output noise, improve PSRR simultaneously.In addition, produce (a PTAT that is directly proportional with temperature that temperature coefficient is variable in the present invention, Proportional To the Absolute Temperature) electric current, the temperature coefficient of this PTAT electric current and resistance compensates, on resistance, obtain a temperature-independent reference voltage, after the temperature coefficient match of PTAT electric current and resistance is good, can be very easily the size of resistance size by adjusting resistance or electric current adjust the size of benchmark output voltage, so the present invention can produce the reference voltage of flexibility and changeability.

Description of drawings

Fig. 1 is the schematic diagram of existing basic low differential voltage linear voltage stabilizer circuit;

Fig. 2 is the schematic diagram of low differential voltage linear voltage stabilizer circuit of the present invention;

Fig. 3 is the synoptic diagram of reference voltage circuit among the present invention (201);

Fig. 4 is the fundamental current mirror circuit in the reference voltage circuit among the present invention (201) and the schematic diagram of current generating circuit;

Fig. 5 is in order to improve improved cascode structure (cascoded) current mirroring circuit and the current generating circuit schematic diagram of reference voltage circuit (201) among noise and the present invention of PSRR performance.

Embodiment

As shown in Figure 2, low pressure difference linear voltage regulator LDO circuit of the present invention is made of reference voltage 201, error amplifier EA 102, output power pipe MPX 103, load 105 and RC filtering circuit 106.LDO circuit of the present invention is compared with traditional LDO circuit, cancelled the dividing potential drop sampling network, error amplifier EA 102 and output power pipe MPX 103 have constituted the follower of a unity gain, and this structure has been cancelled the thermonoise that sampling resistor brought in the dividing potential drop sampling network.Because the enlargement factor of follower is 1, the input reference noise of error amplifier EA 102 input ends and the undesired signal of power supply just do not have any amplification at output terminal simultaneously.So the noise that the LDO circuit that the present invention proposes produces is little more a lot of than the noise that traditional LDO circuit produces, the PSRR of whole LDO also is improved simultaneously.Because error amplifier EA 102 and output power pipe MPX103 are connected into the follower of unity gain, so need a new reference voltage generating circuit, no longer the bandgap voltage reference with traditional is the same for the output voltage that it produces, it is the magnitude of voltage about a 1.2V, but the numerical value that can require flexible variation, for example 0.9V, 1.2V, 1.5V, 1.8V, 2.5V, a 3.3V according to the output voltage of actual LDO.

The generation of traditional bandgap voltage reference is to utilize the PN junction forward conduction voltage V with negative temperature coefficient _BEWith two with positive temperature coefficient (PTC) base-emitter voltage difference delta V that are operated in triode under the different current densities _BEThereby stack compensation according to a certain percentage obtains temperature-independent reference voltage, i.e. a V _REF=V _BE+ KV _TLnN, N are the ratio of two current densities between the triode, V _TBe thermal voltage, K is a selectable constant in design, and the benchmark output voltage that this method obtains is about 1.2V.And in the present invention, need to produce the reference voltage that can change flexibly, obviously this traditional bandgap voltage reference production method is undesirable.The method of Cai Yonging is to produce the PTAT electric current that temperature coefficient is variable in the present invention, the temperature coefficient of this PTAT electric current and resistance compensates, on resistance, obtain a temperature-independent reference voltage, after the temperature coefficient match of PTAT electric current and resistance is good, can be very easily the size of resistance size by adjusting resistance or electric current adjust the size of benchmark output voltage.

Fig. 3 is a reference voltage circuit 201 of the present invention.Circuit at first produces the two-way electric current, and one the tunnel is the I with positive temperature coefficient (PTC) _PTATElectric current, the one tunnel is the I with negative temperature coefficient _PTVBEElectric current, this two-way electric current compensates out an I that temperature coefficient is adjustable by the different proportion stack _BGElectric current, this electric current are again and resistance R ₀Temperature coefficient compensate, thereby can obtain a temperature-independent reference voltage.Electric current I _BGAnd resistance R ₀Tc compensation can be after good by adjusting resistance R ₀Size obtain different benchmark output voltages.

Electric current I with positive temperature coefficient (PTC) _PTATWith electric current I with negative temperature coefficient _PTVBECan produce by circuit shown in Figure 4:

As shown in Figure 4, the current source I that has positive temperature coefficient (PTC) _PTATOr has a current source I of negative temperature coefficient _PTVBECircuit comprise two continuous fundamental current mirror circuits 301 and current generating circuit 302.

M among Fig. 4 ₁And M ₂Be the NMOS pipe of optional feature dimension scale relation in the design, M ₃And M ₄Be and M ₁, M ₂PMOS pipe with same characteristic features dimension scale relation, M ₅And M ₃Characteristic dimension than for a, a equally also is an optional constant in design.Q1 and Q2 are two substrate PNP transistors that are connected into the diode form, and its area ratio is 1: N, the characteristic dimension ratio of the ratio of resistance R 2 and R3 and M1, M2 is opposite.Simple for problem analysis, following formula pushes over based on the characteristic dimension ratio of M1 and M2 and selects 1 situation, and does not consider the influence of raceway groove mudulation effect and the limited output impedance of metal-oxide-semiconductor, because M ₃And M ₄The characteristic dimension ratio be 1 also, flow through M ₁And M ₂Electric current I ₁And I ₂Identical, M ₁And M ₂Source voltage terminal also identical.Because R ₂=R ₃, flow through two resistance R like this ₂And R ₃Electric current equate that size equals V _BE2With the ratio of resistance, the electric current that flows through the substrate PNP transistor of two diode connections equates that also size equals the voltage difference delta V of two substrate tube BE knots _BEWith resistance R ₁Ratio, and Δ V _BEFollowing relation is arranged:

$\mathrm{\Δ}{V}_{\mathrm{BE}}=V_{\mathrm{BE}1}-V_{\mathrm{BE}2}=V_T*\ln \left(\frac{J_1}{J_2}\right)=V_T*\ln \left(N\right)$ Formula (1)

$V_T=\frac{\mathrm{kT}}{q},$ J wherein ₁, J ₂Be respectively and stayed Q ₁, Q ₂Current density, N is the area ratio of two substrate tube.The electric current of two-way is like this:

$I_1=I_2=\frac{V_{\mathrm{BE}1}}{R_2}+\frac{V_T*\ln N}{R_1}$ Formula (2)

First on the right of equation is and V in the formula (2) _BE1Proportional I with negative temperature coefficient _PTVBEElectric current.Second on the right of equation is and V _TLnN (is Δ V _BE) proportional I with positive temperature coefficient _PTATCurrent source, two electric currents are superimposed, by adjusting resistance R ₁, R ₂And the substrate PNP transistor area can be adjusted I than N ₁And I ₂Temperature coefficient.

Electric current is mirrored to M through current mirror ₅, its mirror image multiple is a, then the reference voltage that obtains at the output terminal of reference voltage is:

$V_{\mathrm{REF}}=R_0*a*(\frac{V_{\mathrm{BE}1}}{R_2}+\frac{V_T*\ln N}{R_1})$ Formula (3)

We can adjust resistance R very easily like this ₀Size just can obtain the benchmark output voltages of different sizes.

At first consider temperature compensation, simple for problem analysis, only consider the first compensation phase of temperature here, that is to say the linear change of a standard of compensation voltage with temperature, so just has:

$V_T=\frac{\mathrm{kT}}{q}=\frac{k{T}_0}{q}(1+\frac{1}{T_0}\mathrm{\ΔT})=\frac{{\mathrm{kT}}_0}{q}(1+\mathrm{\α}*\mathrm{\ΔT})$ Formula (4)

Here T ₀Be that compensation back coefficient is 0 temperature, and Δ T=T-T ₀, same, resistance R and V _BE1Also can be expressed as:

R=R _T0(1+ γ * Δ T) formula (5)

V _BE1=V _{BE1, T0}(1-β * Δ T) formula (6)

Like this, can obtain the benchmark output voltage by formula (4)～(6):

$V_{\mathrm{REF}}=R_{0,T0}(1+\mathrm{\γ}*\mathrm{\ΔT})*a*[\frac{V_{\mathrm{BE}1,T0}(1-\mathrm{\β}*\mathrm{\ΔT})}{R_{2,T0}(1+\mathrm{\γ}*\mathrm{\ΔT})}+\frac{\frac{k{T}_0}{q}(1+\mathrm{\α}*\mathrm{\ΔT})*\ln N}{R_{1,T0}(1+\mathrm{\γ}*\mathrm{\ΔT})}]$ Formula (7)

If R ₂With R ₁Ratio be m, irrelevant for making reference voltage and temperature single order, should meet the following conditions through derivation m:

$m=\frac{q{V}_{\mathrm{BE}1,T0}}{k{T}_0}*\frac{\mathrm{\β}}{\mathrm{\α}\ln N}$ Formula (8)

Come as can be seen from formula (8), this reference voltage circuit (201) does not require the type of the resistance of employing, so long as same type resistance, its temperature coefficient just can be cancelled out each other to the influence of the reference voltage that produces, the temperature compensation of reference voltage only with two resistance R ₂And R ₁Ratio relevant.

In order to improve the PSRR of output reference voltage, also can adopt the current mirror of cascoded structure, as shown in Figure 5: circuit comprises two continuous cascoded structure current mirror 303 and current generating circuits 302, wherein:

The characteristic dimension with M1, M2 is identical respectively for the characteristic dimension of two NMOS pipes M6, M7; And:

The characteristic dimension with M3, M4, M5 is identical respectively for the characteristic dimension of three PMOS pipe M8, M9 and M10.

(1) Fa Ming advantage

1, the reference voltage circuit (201) that has proposed a brand-new LDO circuit structure and be used for this structure, reference voltage circuit (201) directly produce one that be easy to adjust size with specify the identical reference voltage of output voltage.Can make full use of RC filtering circuit (206) like this curbs noise and the power supply interference that reference voltage (201) module produces.Error amplifier EA (202) and output power pipe MPX (203) are connected into the follower of unity gain in the new LDO circuit, the reference input noise of error amplifier EA (202) input end and power supply undesired signal are not amplified by error amplifier EA (202) like this, even make that LDO exports under the different voltage condition, can both obtain noiseproof feature and PSRR performance preferably.

2, reference voltage (201) module is simple in structure, and scale and quiescent current are all very little, and the temperature compensation of reference voltage do not have harsh requirement to technology, only relevant with the ratio of the resistance of choosing, and has made things convenient for the selection of designer to technology.

Though low differential voltage linear voltage stabilizer circuit of the present invention is described with reference to current instantiation, but those skilled in the art should be realized that, above example only is to be used for illustrating the present invention, also can make the variation and the modification of various equivalences under the situation that does not break away from spirit of the present invention.Therefore, if in connotation scope of the present invention to the variation of above-mentioned example, modification all will drop in the scope of claims of the present invention.

Claims (9)

1. low differential voltage linear voltage stabilizer circuit, constitute by reference voltage circuit (201), error amplifier EA (102), output power pipe MPX (103) and load circuit (105), it is characterized in that: the output terminal of described load circuit (105) directly links to each other with output power pipe MPX (103), and the output terminal of this load circuit (105) also feeds back to the input positive terminal of error amplifier EA (102).

2. low differential voltage linear voltage stabilizer circuit according to claim 1 is characterized in that: it also comprises a RC filtering circuit (106) that is connected between described reference voltage circuit (201) and the error amplifier EA (102).

3. low differential voltage linear voltage stabilizer circuit according to claim 1 and 2 is characterized in that: described reference voltage circuit (201) is the current source I that has positive temperature coefficient (PTC) by _PTATWith a current source I with negative temperature coefficient _PTVBEThe resistance R of connecting again after the parallel connection 0 constitutes.

4. low differential voltage linear voltage stabilizer circuit according to claim 3 is characterized in that: described resistance R ₀It is adjustable resistance.

5. low differential voltage linear voltage stabilizer circuit according to claim 3 is characterized in that: described current source I with positive temperature coefficient (PTC) _PTATOr has a current source I of negative temperature coefficient _PTVBECircuit comprise that two continuous are basic structure current mirroring circuit (301) and current generating circuit (302), wherein:

Described current generating circuit (302) is to be 1 by two its area ratios that are connected into the diode form: the substrate PNP transistor Q of N ₁, Q ₂With three resistance R ₁, R ₂, R ₃Constitute.

6. low differential voltage linear voltage stabilizer circuit according to claim 5 is characterized in that: described current mirroring circuit is basic structure current mirror (301), and it comprises:

Two have the NMOS pipe M that sets the characteristic dimension proportionate relationship ₁, M ₂

Two have and described NMOS pipe M ₁, M ₂The PMOS pipe M of same characteristic features dimension scale relation ₃, M ₄

One and described PMOS pipe M ₃Characteristic dimension is than the PMOS pipe M for a ₅, wherein: a is optional constant.

7. low differential voltage linear voltage stabilizer circuit according to claim 6 is characterized in that: described NMOS pipe M ₁, M ₂Characteristic dimension ratio and two resistance R ₂, R ₃Ratio opposite.

8. low differential voltage linear voltage stabilizer circuit according to claim 5 is characterized in that: described current mirroring circuit is a cascode structure current mirror (303), and it comprises:

Two have the NMOS pipe M that sets the characteristic dimension proportionate relationship ₁, M ₂

Two have and described NMOS pipe M ₁, M ₂The PMOS pipe M of same characteristic features dimension scale relation ₃, M ₄

One and described PMOS pipe M ₃Characteristic dimension is than the PMOS pipe M for a ₅, wherein, wherein: a is optional constant;

Two NMOS pipe M6, M7 that have the same characteristic features size with described NMOS pipe M1, M2; And:

Three PMOS pipe M8, M9 and M10 that have the same characteristic features size with described PMOS pipe and M3, M4, M5.

9. low differential voltage linear voltage stabilizer circuit according to claim 8 is characterized in that: described NMOS pipe M ₁, M ₂Characteristic dimension ratio and two resistance R ₂, R ₃Ratio opposite.

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