CN108319319B - LDO with flow-route and temperature adjust automatically - Google Patents
LDO with flow-route and temperature adjust automatically Download PDFInfo
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- CN108319319B CN108319319B CN201810130031.7A CN201810130031A CN108319319B CN 108319319 B CN108319319 B CN 108319319B CN 201810130031 A CN201810130031 A CN 201810130031A CN 108319319 B CN108319319 B CN 108319319B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
LDO with flow-route and temperature adjust automatically, belongs to integrated circuit fields, and the present invention is to solve the problem of that the common LDO Adjustment precision with flow-route and temperature adjustment is low to change with the variation of flow-route and temperature well.The present invention includes LDO master unit, temperature adjustment circuit and technique adjustment circuit；The temperature adjustment signal of the adjustment terminal cut-in temperature adjustment circuit of LDO master unit and the technique adjustment signal of technique adjustment circuit；When environment temperature is more than temperature threshold, the output voltage of temperature adjustment circuit control LDO master unit increases as the temperature increases；The inverting input terminal of technique adjustment circuit control operational amplifier A1 generates zero-temperature coefficient voltage, and to adjust the deviation of chip integrated artistic, when chip integrated artistic deviation is bigger than normal, the output voltage of LDO master unit is increased with it, otherwise is reduced.
Description
Technical field
The invention belongs to integrated circuit fields, are related to a kind of LDO with flow-route and temperature adjust automatically.
Background technique
Sometimes for using LDO (abbreviation of Low Dropout Regulator, low voltage difference inside IC chip
Linear voltage regulator) supply voltage of standard is converted, reach and stabilize the output voltage, increases the purpose of power supply rejection ratio.And
And chip power-consumption can be reduced and meet transistor and use the requirement of limitation.Temperature is added in special LDO and adjusts module, when integrated
Circuit chip is increased with environment temperature, and when performance declines, the output voltage that temperature adjustment module can adjust LDO is increased, to reach
To the effect for improving chip performance.Technique adjustment module is added in special LDO, when IC chip goes out in the fabrication process
When existing fabrication error, the output voltage of LDO can be adjusted.
Fig. 1 gives the common circuit structure with flow-route and temperature adjustment LDO.In Fig. 1, operational amplifier A3,
PMOS transistor MP8, resistance R5, resistance R6 constitute simple LDO structure.
The reverse inter-input-ing voltage of operational amplifier A3 can indicate are as follows:
Vn=(IPTAT+ICTAT)·R7+Vbe_Q2 (1)
Wherein IPTATFor the electric current increased with increased temperature caused by current source, size of current can be by 2N Sp
Switch Sp1,Sp2,...,Sp2nArtificial control；ICTATTo increase and reduced electric current caused by current source with temperature, electric current is big
It is small can be by 2N ScSwitch Sc1,Sc2,...,Sc2nArtificial control；R7For resistance R7 resistance value；Vbe_Q2For NPN transistor Q2's
Base-emitter voltage；
It can be obtained by formula (1), VnBeing one can artificially can adjust, the voltage with temperature coefficient, and its function
Image is dull linear function；
The normal phase input end voltage of operational amplifier A3 can indicate are as follows:
Vp=IMP8·R6 (2)
Wherein IMP8The electric current flowed through by PMOS transistor PM8, size are controlled by operational amplifier A3 output end；R6
For the resistance value of resistance R6；
The output voltage of LDO can indicate are as follows:
Vout=IMP8·(R6+R5) (3)
Utilize the short principle of void of operational amplifier, it may be assumed that
Vp≈Vn (4)
IMP8·R6=(IPTAT+ICTAT)·R7+Vbe_Q2 (5)
The output voltage of LDO also may indicate that are as follows:
By formula (7) it is found that the output voltage size of LDO can be by IPTAT+ICTATSize of current control, and have single
One slope.
In practical application, common uses after the completion of chip manufacturing with chip with flow-route and temperature adjustment LDO needs
In the process, the output voltage of manual testing LDO passes through setting switch S with the variation of flow-route and temperaturep、ScConducting number adjust
The output voltage of whole LDO.This kind of adjustment mode process is complicated, accuracy is low, is unable to satisfy flexible and changeable power demands.
Summary of the invention
The invention aims to solve the common LDO with flow-route and temperature adjustment, output voltage need to be surveyed manually
It is manually adjusted after examination, and there are process complexity, Adjustment precision is low, cannot become well with the variation of flow-route and temperature
The problem of change, provides a kind of LDO with flow-route and temperature adjust automatically.
LDO of the present invention with flow-route and temperature adjust automatically, including LDO master unit, LDO master unit include operation
Amplifier A1, resistance R2, resistance R3, resistance R4, PMOS transistor MP5, current source I2 and NPN triode Q1；Operational amplifier
The inverting input terminal of A1 is grounded by resistance R2, NPN triode Q1；Power vd D is also connect by current source I2；Operational amplifier A1
Non-inverting input terminal be grounded by resistance R4, output terminal Vout is also connected simultaneously by resistance R3；Operational amplifier A1's is defeated
Outlet is separately connected power vd D and output terminal Vout by PMOS transistor MP5；
It is characterized in that, further including temperature adjustment circuit and technique adjustment circuit；The inverting input terminal of operational amplifier A1,
The negative terminal of current source I2 and the public terminal of resistance R2 are as adjustment terminal, the temperature of the adjustment terminal cut-in temperature adjustment circuit
Spend the technique adjustment signal of adjustment signal and technique adjustment circuit；
When environment temperature is more than temperature threshold, temperature adjustment circuit controls the output voltage of LDO master unit with temperature
Increase and increases；
The inverting input terminal of technique adjustment circuit control operational amplifier A1 generates zero-temperature coefficient voltage, to adjust chip
The deviation of integrated artistic, when chip integrated artistic deviation is bigger than normal, the output voltage of LDO master unit is increased with it, otherwise is reduced.
Preferably, temperature adjustment circuit includes negative temperature parameter current source ICTAT2, positive temperature coefficient current source IPTAT、NMOS
Transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, PMOS transistor MP6 and PMOS transistor
MP7；
The grid of NMOS transistor MN1 connects its drain terminal, the grid of NMOS transistor MN2 and negative temperature parameter current simultaneously
Source ICTAT2Negative terminal；
The drain terminal of NMOS transistor MN2 connects the drain terminal and its grid, NMOS transistor MN4 of NMOS transistor MN3 simultaneously
Grid, positive temperature coefficient current source IPTATNegative terminal；
The drain terminal of NMOS transistor MN4 connects the drain terminal and its grid, PMOS transistor MP7 of PMOS transistor MP6 simultaneously
Grid；
The source of NMOS transistor MN1, MN2, MN3, MN4 connect GND simultaneously；
Negative temperature parameter current source ICTAT2Anode, positive temperature coefficient current source IPTATAnode, PMOS transistor MP6
Source and the source of PMOS transistor MP7 connect power vd D simultaneously；
The adjustment terminal of the drain terminal connection LDO master unit of PMOS transistor MP7.
Preferably, technique adjustment circuit includes operational amplifier A0, negative temperature parameter current source ICTAT1, current source I0, electricity
Stream source I1, current source I3, resistance R1, core Off-chip test resistance REXT, resistance R in chipIN, capacitor C1, PMOS transistor MP2,
PMOS transistor MP3 and PMOS transistor MP4；
It is brilliant that the grid of PMOS transistor MP1 connects the output end of operational amplifier A0, one end of resistance R1 and PMOS simultaneously
The grid of body pipe MP2；One end of the other end connection capacitor C1 of resistance R1；
The drain terminal of PMOS transistor MP1 connects the other end of capacitor C1, the negative terminal of current source I1, resistance R in chip simultaneouslyIN
One end and operational amplifier A0 normal phase input end；
The drain terminal of PMOS transistor MP2 simultaneously connects the grid and drain terminal, PMOS transistor MP4 of PMOS transistor MP3
The anode of grid and current source I3；
The drain terminal of PMOS transistor MP4 connects the adjustment terminal of LDO master unit simultaneously；
The inverting input terminal of operational amplifier A0 connects core Off-chip test resistance R simultaneouslyEXTOne end, negative temperature coefficient electricity
Stream source ICTAT1Negative terminal and current source I0 negative terminal；
Negative temperature parameter current source ICTAT1Anode, the anode of current source I0, the anode of current source I1, PMOS transistor
The source of MP1, MP2, MP3, MP4 connect power vd D simultaneously；
Core Off-chip test resistance REXTThe other end, resistance R in chipINThe other end and the negative terminal of current source I3 connect simultaneously
Meet GND.
Beneficial effects of the present invention: proposing a kind of LDO circuit with flow-route and temperature adjust automatically, changes common have
The LDO of flow-route and temperature adjustment enables to the output voltage of LDO can be certainly using the implementation for manually adjusting output voltage
The dynamic variation with temperature and technique and change, have already been through simulation results show.
Detailed description of the invention
Fig. 1 is the circuit diagram of the common LDO with flow-route and temperature adjust automatically；
Fig. 2 is the LDO functional block diagram with flow-route and temperature adjust automatically of the invention；
Fig. 3 is the LDO circuit schematic diagram with flow-route and temperature adjust automatically of the invention；
Fig. 4 is that LDO output voltage of the invention varies with temperature figure；
Fig. 5 is LDO output voltage of the invention with technique change figure.
Specific embodiment
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, how to apply to the present invention whereby
Technological means solves technical problem, and the realization process for reaching technical effect can fully understand and implement.It needs to illustrate
As long as not constituting conflict, each feature in each embodiment and each embodiment in the present invention can be combined with each other,
It is within the scope of the present invention to be formed by technical solution.
In illustrating the common LDO circuit with flow-route and temperature adjustment, due to using multiple switch S in circuitpControl
I processedPTATSize, ScControl ICTATSize, the final size for controlling LDO output voltage, needs first to test in this process by work
LDO output voltage under skill deviation and required temperature, finally manually adjusts LDO output voltage, the low precision of adjustment and cannot
Moment makes corresponding adjustment.
LDO circuit with flow-route and temperature adjust automatically of the invention can be at the beginning of chip designs referring to Fig. 3
The size of comparison resistance inside and outside reasonable set temperature turning point and piece, with reach can be inclined according to chip operation situation and technique
Difference, constantly adjust automatically LDO is exported, and is greatly reduced the difficulty of adjustment, is more reasonably optimized chip performance.
The specific embodiment for the LDO circuit with flow-route and temperature adjust automatically that Fig. 3 is provided, wherein LDO master unit be
Temperature, technique adjustment object, LDO master unit include operational amplifier A1, resistance R2, resistance R3, resistance R4, PMOS transistor
MP5, current source I2 and NPN triode Q1；The inverting input terminal of operational amplifier A1 is grounded by resistance R2, NPN triode Q1；
Power vd D is also connect by current source I2；The non-inverting input terminal of operational amplifier A1 is grounded by resistance R4, also same by resistance R3
When connect output terminal Vout；The output end of operational amplifier A1 is separately connected power vd D and output by PMOS transistor MP5
Terminal Vout.
The physical circuit of temperature adjustment circuit and technique adjustment circuit is not described further in detail.
The working principle of temperature adjustment circuit:
The electric current I of positive temperature coefficient will be hadPTATWith the electric current I for having negative temperature coefficientCTAT2It is added in certain proportion,
The ratio can design according to demand at the beginning of chip designs, and electric current after being added is injected into the anti-phase input of A1 by mirror image
End generates the input voltage with temperature adjust automatically, therefore the output voltage Vout of LDO also variation with temperature by resistance R2
And change.
1, when LDO work in low-temperature zone, current source ICTAT2Initial current be greater than current source IPATAInitial current,
NMOS transistor MN2 mirror current source ICTAT2Electric current, on the branch road of NMOS transistor MN2, because of current source IPATAElectricity
Stream is less than current source ICTAT2Electric current, therefore flow into NMOS transistor MN3 without extra electric current.PMOS transistor MP7 is also without electricity
Stream outflow.
2, as current source ICTAT2With current source IPATAWhen varying with temperature, there are a temperature breakthrough (temperature threshold), this
When two beam current values it is equal, and the turning point can in advance artificially be arranged.
3, when environment temperature is more than turning point temperature, current source IPATAElectric current be greater than current source ICTAT2Electric current.
NMOS transistor MN3 has extra electric current outflow.PMOS transistor MP7 also has electric current outflow.And the electric current can be with temperature
Increase and increase.
Using and rewrite formula (7), the output voltage relational expression of LDO are as follows:
IMP7Electric current, I are flowed out for PMOS transistor MP72Electric current is flowed out for current source I2.IMP7For piecewise linearity electric current, when
When environment temperature reaches turning point, the output V of LDOoutIt will increase as the temperature increases.
Based on above-mentioned analysis, it is seen that the present embodiment temperature adjustment circuit can be brought the following benefits:
Increasing and raised electric current with temperature for temperature adjustment circuit output, is piecewise function, in a certain temperature breakthrough
Before, electric current keeping parallelism as the temperature rises is exported, i.e., LDO is not adjusted.After a certain temperature breakthrough,
Output electric current increases as the temperature rises, is adjusted to LDO.This method can reach temperature in chip operation environment temperature
Degree turns ability after selecting a little and is constantly adjusted to LDO, substantially reduce the complexity of adjustment, and reasonably optimizing chip performance.
The working principle of technique adjustment module:
The electric current I of negative temperature coefficient will be hadCTAT1The electric current for having positive temperature coefficient is generated by certain mirror-image fashion,
The electric current generates the negative temperature coefficient voltage V of voltage and NPN transistor Q1 with positive temperature coefficient by resistance R2beIt is comprehensive,
Zero-temperature coefficient voltage is generated in the inverting input terminal of A1.Comparable chip internal resistance R is removed by amplifier A0INWith chip testing electricity
Hinder REXTSize, the corresponding Current Voltage for changing PMOS transistor MP4 and being injected into A1 inverting input terminal, so that LDO energy
Enough sizes according to process deviation, voluntarily adjust output voltage Vout。
The inverting input terminal V of operational amplifier A0nIt can indicate are as follows:
Vn=(ICTAT1+I0)·REXT (9)
Wherein ICTAT1For current source ICTAT1Size of current and have negative temperature coefficient, I0For current source I0 size of current, REXT
For core Off-chip test resistance REXTResistance value.
The normal phase input end V of operational amplifier A0pIt can indicate are as follows:
Vp=(IMP1+I1)·RIN (10)
Wherein IMP1For the electric current that PMOS transistor MP1 flows through, I1For current source I1 electric current, RINFor resistance R in chipINResistance
Value.
Utilize the short principle of void of operational amplifier, it may be assumed that
Vp≈Vn (11)
(IMP1+I1)·RIN≈(ICTAT1+I0)·REXT (12)
I is set in formula (13)0=I1, and assume no fabrication error i.e. REXT=RIN, therefore formula (13) can be with
It rewrites are as follows:
IMP1≈ICTAT1 (14)
Therefore electric current IMP1And ICTAT1Negative temperature coefficient having the same.
The electric current that PMOS transistor MP2 mirror image PMOS transistor MP1 is flowed through, with the increase of temperature, the electric current of MP2 by
Decrescence small, the size of current of current source I3 does not vary with temperature, electric current I3-ICTAT1Increase with temperature and increase, the electric current of MP4 is big
It is small also to increase and increase with temperature.
The inverting input terminal V of operational amplifier A1nIt can indicate are as follows:
Vn=(I2+I3-ICTAT1)·R2+Vbe_Q1 (15)
Vbe_Q1Be negative temperaturecoefficient voltage, (I2+I3-ICTAT1)·R2Be positive temperaturecoefficient voltage, and the two addition is rationally set
The size of current in formula (15) is set, V can be obtainednFor zero-temperature coefficient voltage.This zero-temperature coefficient voltage is in operation amplifier
The inverting input terminal of device A1 generates, to prevent from causing the temperature coefficient of image current to change due to process deviation, finally
Zero warm reference voltage can not be generated.
Resistance R is set outside chipEXTResistance value and initial design piece in resistance RINSize is identical, using formula (13),
I is set0=I1。
1, the i.e. resistance R when error occurs in techniqueINGreater than REXT, electric current IMP1It is corresponding to reduce, the branch of PMOS transistor MP2
Road electric current reduces, and the branch current of PMOS transistor MP3, MP4 increases, and the output voltage of LDO can be obtained using formula (8) principle
VoutIt will increase；
2, as resistance RINLess than REXT, electric current IMP1Corresponding to increase, the branch current of PMOS transistor MP2 increases, PMOS
The branch current of transistor MP3, MP4 reduce, and the output voltage V of LDO can be obtained using formula (8) principleoutIt will reduce；
That is RINRepresent the process deviation of chip entirety, RINIncrease, then LDO output voltage Vout increases；RINReduce, then
LDO output voltage Vout reduces.
Fig. 4 is that LDO output voltage varies with temperature figure.The electric current that curve 1 is flowed through by PMOS transistor MP7 in figure turns
Break appears in 59 DEG C of point M2 horizontal axis, and the turning point can self-setting according to demand, when the temperature increases, the electricity flowed through
Stream is gradually increased.Curve 2 is LDO output voltage, and turning point appears in 59 DEG C of point M4 horizontal axis, when the temperature increases, output voltage
It is gradually increased.
Fig. 5 is LDO output voltage with technique change figure.R in figureINAbscissa represents the resistance of technique change.R is setIN=
RRXT=1k, RINWhen > 1k Ω, LDO output voltage Vout increases, RINWhen < 1k Ω, LDO output voltage Vout reduces.
Based on above-mentioned analysis, it is seen that the present embodiment technique adjustment circuit can be brought the following benefits:
Process deviation bring can be prevented to the greatest extent by generating zero-temperature coefficient voltage nearby in A1 inverting input terminal
Non-zero temperature coefficient voltage influence, chip interior resistance RINWith chip testing resistance REXTSize compares the adjust automatically of generation
Current Voltage substantially reduces the complexity of adjustment, and rationally excellent so that LDO output voltage can also be followed by adjust automatically
Chip performance is changed.
LDO proposed by the present invention with flow-route and temperature adjust automatically, which is different from common same type circuit, needs circuit to survey
LDO output voltage is manually adjusted after examination, but can voluntarily be adjusted automatically according to the variation of flow-route and temperature, and adjustment process is reduced
Complexity, improve the precision of output voltage, give chip provide a reasonable supply voltage.
Although disclosed herein embodiment it is as above, the content is only to facilitate understanding the present invention and adopting
Embodiment is not intended to limit the invention.Any those skilled in the art to which this invention pertains are not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and change can be made in the implementing form and in details,
But scope of patent protection of the invention, still should be subject to the scope of the claims as defined in the appended claims.
Claims (1)
1. having the LDO of flow-route and temperature adjust automatically, including LDO master unit, LDO master unit include operational amplifier A1, electricity
Hinder R2, resistance R3, resistance R4, PMOS transistor MP5, current source I2 and NPN triode Q1；The anti-phase input of operational amplifier A1
End is grounded by resistance R2, NPN triode Q1；Power vd D is also connect by current source I2；The non-inverting input terminal of operational amplifier A1
It is grounded by resistance R4, output terminal Vout is also connected by resistance R3 simultaneously；The output end of operational amplifier A1 passes through PMOS
Transistor MP5 is separately connected power vd D and output terminal Vout；
It is characterized in that, further including temperature adjustment circuit and technique adjustment circuit；The inverting input terminal of operational amplifier A1, electric current
The negative terminal of source I2 and the public terminal of resistance R2 are as adjustment terminal, the temperature tune of the adjustment terminal cut-in temperature adjustment circuit
The technique adjustment signal of entire signal and technique adjustment circuit；
When environment temperature is more than temperature threshold, temperature adjustment circuit controls the output voltage of LDO master unit as the temperature increases
And increase；
The inverting input terminal of technique adjustment circuit control operational amplifier A1 generates zero-temperature coefficient voltage, to adjust chip entirety
The deviation of technique, when chip integrated artistic deviation is bigger than normal, the output voltage of LDO master unit is increased with it, otherwise is reduced；
Temperature adjustment circuit includes negative temperature parameter current source ICTAT2, positive temperature coefficient current source IPTAT, NMOS transistor MN1,
NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, PMOS transistor MP6 and PMOS transistor MP7；
The grid of NMOS transistor MN1 connects its drain terminal, the grid of NMOS transistor MN2 and negative temperature parameter current source simultaneously
ICTAT2Negative terminal；
The drain terminal of NMOS transistor MN2 connects the drain terminal of NMOS transistor MN3 and its grid of grid, NMOS transistor MN4 simultaneously
Pole, positive temperature coefficient current source IPTATNegative terminal；
The drain terminal of NMOS transistor MN4 connects the drain terminal of PMOS transistor MP6 and its grid of grid, PMOS transistor MP7 simultaneously
Pole；
The source of NMOS transistor MN1, MN2, MN3, MN4 connect GND simultaneously；
Negative temperature parameter current source ICTAT2Anode, positive temperature coefficient current source IPTATAnode, PMOS transistor MP6 source
Power vd D is connected simultaneously with the source of PMOS transistor MP7；
The adjustment terminal of the drain terminal connection LDO master unit of PMOS transistor MP7；
Technique adjustment circuit includes operational amplifier A0, negative temperature parameter current source ICTAT1, current source I0, current source I1, electric current
Source I3, resistance R1, core Off-chip test resistance REXT, resistance R in chipIN, capacitor C1, PMOS transistor MP2, PMOS transistor MP3
With PMOS transistor MP4；
The grid of PMOS transistor MP1 connects the output end of operational amplifier A0, one end of resistance R1 and PMOS transistor simultaneously
The grid of MP2；One end of the other end connection capacitor C1 of resistance R1；
The drain terminal of PMOS transistor MP1 connects the other end of capacitor C1, the negative terminal of current source I1, resistance R in chip simultaneouslyINOne
The normal phase input end at end and operational amplifier A0；
The drain terminal of PMOS transistor MP2 connects the grid of PMOS transistor MP3 and the grid of drain terminal, PMOS transistor MP4 simultaneously
With the anode of current source I3；
The drain terminal of PMOS transistor MP4 connects the adjustment terminal of LDO master unit simultaneously；
The inverting input terminal of operational amplifier A0 connects core Off-chip test resistance R simultaneouslyEXTOne end, negative temperature parameter current source
ICTAT1Negative terminal and current source I0 negative terminal；
Negative temperature parameter current source ICTAT1Anode, the anode of current source I0, the anode of current source I1, PMOS transistor MP1,
The source of MP2, MP3, MP4 connect power vd D simultaneously；
Core Off-chip test resistance REXTThe other end, resistance R in chipINThe other end and the negative terminal of current source I3 connect simultaneously
GND。
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| US11735902B2 (en) * | 2020-03-24 | 2023-08-22 | Analog Devices International Unlimited Company | Bipolar junction transistor heater circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6969982B1 (en) * | 2003-10-03 | 2005-11-29 | National Semiconductor Corporation | Voltage regulation using current feedback |
| CN1825240A (en) * | 2006-03-24 | 2006-08-30 | 启攀微电子（上海）有限公司 | Low voltage difference linear voltage stabilizer circuit |
| CN102495654A (en) * | 2011-11-25 | 2012-06-13 | 上海艾为电子技术有限公司 | Low-dropout regulator and integrated circuit system |
| CN105739587A (en) * | 2016-02-23 | 2016-07-06 | 无锡中微亿芯有限公司 | Low dropout regulator which can output large current and has adjustable temperature coefficient |
-
2018
- 2018-02-08 CN CN201810130031.7A patent/CN108319319B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6969982B1 (en) * | 2003-10-03 | 2005-11-29 | National Semiconductor Corporation | Voltage regulation using current feedback |
| CN1825240A (en) * | 2006-03-24 | 2006-08-30 | 启攀微电子（上海）有限公司 | Low voltage difference linear voltage stabilizer circuit |
| CN102495654A (en) * | 2011-11-25 | 2012-06-13 | 上海艾为电子技术有限公司 | Low-dropout regulator and integrated circuit system |
| CN105739587A (en) * | 2016-02-23 | 2016-07-06 | 无锡中微亿芯有限公司 | Low dropout regulator which can output large current and has adjustable temperature coefficient |
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