CN108319319A - LDO with flow-route and temperature adjust automatically - Google Patents
LDO with flow-route and temperature adjust automatically Download PDFInfo
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- CN108319319A CN108319319A CN201810130031.7A CN201810130031A CN108319319A CN 108319319 A CN108319319 A CN 108319319A CN 201810130031 A CN201810130031 A CN 201810130031A CN 108319319 A CN108319319 A CN 108319319A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
LDO with flow-route and temperature adjust automatically, belongs to integrated circuit fields, and the present invention is to solve the problem of that the common LDO Adjustment precisions with flow-route and temperature adjustment are low cannot well change with the variation of flow-route and temperature.The present invention includes LDO master units, temperature adjustment circuit and technique adjustment circuit；The technique adjustment signal of temperature the adjustment signal and technique adjustment circuit of the adjustment terminal cut-in temperature adjustment circuit of LDO master units；When environment temperature is more than temperature threshold, the output voltage of temperature adjustment circuit control LDO master units increases with the increase of temperature；The inverting input of technique adjustment circuit control operational amplifier A 1 generates zero-temperature coefficient voltage, and to adjust the deviation of chip integrated artistic, when chip integrated artistic deviation is bigger than normal, the output voltage of LDO master units increases therewith, otherwise reduces.
Description
Technical field
The invention belongs to integrated circuit fields, are related to a kind of LDO with flow-route and temperature adjust automatically.
Background technology
Sometimes for using LDO (abbreviation of Low Dropout Regulator, low voltage difference inside IC chip
Linear voltage regulator) supply voltage of standard is converted, reach and stabilize the output voltage, increases the purpose of power supply rejection ratio.And
And chip power-consumption can be reduced and meet requirement of the transistor using limitation.Temperature is added in special LDO and adjusts module, when integrated
Circuit chip is increased with environment temperature, and when performance declines, the output voltage that temperature adjustment module can adjust LDO increases, to reach
To the effect for improving chip performance.Technique adjustment module is added in special LDO, when IC chip goes out in the fabrication process
When existing fabrication error, the output voltage of LDO can be adjusted.
Fig. 1 gives the common circuit structure with flow-route and temperature adjustment LDO.In Fig. 1, operational amplifier A 3,
PMOS transistor MP8, resistance R5, resistance R6 constitute simple LDO structures.
The reverse inter-input-ing voltage of operational amplifier A 3 can be expressed as：
Vn=(IPTAT+ICTAT)·R7+Vbe_Q2 (1)
Wherein IPTATFor the electric current increased with increased temperature caused by current source, size of current can be by 2N Sp
Switch Sp1,Sp2,...,Sp2nArtificial control；ICTATThe electric current reduced to increase with temperature caused by current source, electric current are big
It is small can be by 2N ScSwitch Sc1,Sc2,...,Sc2nArtificial control；R7For resistance R7 resistance values；Vbe_Q2For NPN transistor Q2's
Base-emitter voltage；
It can be obtained by formula (1), VnBeing one can artificially can adjust, the voltage with temperature coefficient, and its function
Image is dull linear function；
The normal phase input end voltage of operational amplifier A 3 can be expressed as：
Vp=IMP8·R6 (2)
Wherein IMP8The electric current flowed through by PMOS transistor PM8, size are controlled by 3 output end of operational amplifier A；R6
For the resistance value of resistance R6；
The output voltage of LDO can be expressed as：
Vout=IMP8·(R6+R5) (3)
Using the short principle of void of operational amplifier, i.e.,：
Vp≈Vn (4)
IMP8·R6=(IPTAT+ICTAT)·R7+Vbe_Q2 (5)
The output voltage of LDO is also denoted as：
By formula (7) it is found that the output voltage size of LDO can be by IPTAT+ICTATSize of current control, and with single
One slope.
In practical application, common uses after the completion of chip manufacturing with chip with flow-route and temperature adjustment LDO needs
In the process, the output voltage of manual testing LDO passes through setting switch S with the variation of flow-route and temperaturep、ScConducting number adjust
The output voltage of whole LDO.This kind of adjustment mode process is complicated, accuracy is low, cannot be satisfied flexible and changeable power demands.
Invention content
The invention aims to solve the common LDO with flow-route and temperature adjustment, output voltage need to be surveyed manually
It is manually adjusted after examination, and there are process complexity, Adjustment precision is low, cannot become well with the variation of flow-route and temperature
The problem of change, provides a kind of LDO with flow-route and temperature adjust automatically.
LDO of the present invention with flow-route and temperature adjust automatically, including LDO master units, LDO master units include operation
Amplifier A1, resistance R2, resistance R3, resistance R4, PMOS transistor MP5, current source I2 and NPN triode Q1；Operational amplifier
The inverting input of A1 is grounded by resistance R2, NPN triode Q1；Power vd D is also connect by current source I2；Operational amplifier A 1
In-phase input end be grounded by resistance R4, also by resistance R3 simultaneously connect output terminal Vout；Operational amplifier A 1 it is defeated
Outlet is separately connected power vd D and output terminal Vout by PMOS transistor MP5；
It is characterized in that, further including temperature adjustment circuit and technique adjustment circuit；The inverting input of operational amplifier A 1,
The negative terminal of current source I2 and the public terminal of resistance R2 are as adjustment terminal, the temperature of the adjustment terminal cut-in temperature adjustment circuit
The technique adjustment signal of degree adjustment signal and technique adjustment circuit；
When environment temperature is more than temperature threshold, temperature adjustment circuit controls the output voltage of LDO master units with temperature
Increase and increases；
The inverting input of technique adjustment circuit control operational amplifier A 1 generates zero-temperature coefficient voltage, to adjust chip
The deviation of integrated artistic, when chip integrated artistic deviation is bigger than normal, the output voltage of LDO master units increases therewith, otherwise reduces.
Preferably, temperature adjustment circuit includes negative temperature parameter current source ICTAT2, positive temperature coefficient current source IPTAT、NMOS
Transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, PMOS transistor MP6 and PMOS transistor
MP7；
The grid of NMOS transistor MN1 connects its drain terminal, the grid of NMOS transistor MN2 and negative temperature parameter current simultaneously
Source ICTAT2Negative terminal；
The drain terminal of NMOS transistor MN2 connects the drain terminal and its grid, NMOS transistor MN4 of NMOS transistor MN3 simultaneously
Grid, positive temperature coefficient current source IPTATNegative terminal；
The drain terminal of NMOS transistor MN4 connects the drain terminal and its grid, PMOS transistor MP7 of PMOS transistor MP6 simultaneously
Grid；
The source of NMOS transistor MN1, MN2, MN3, MN4 connect GND simultaneously；
Negative temperature parameter current source ICTAT2Anode, positive temperature coefficient current source IPTATAnode, PMOS transistor MP6
Source and the source of PMOS transistor MP7 connect power vd D simultaneously；
The adjustment terminal of the drain terminal connection LDO master units of PMOS transistor MP7.
Preferably, technique adjustment circuit includes operational amplifier A 0, negative temperature parameter current source ICTAT1, current source I0, electricity
Stream source I1, current source I3, resistance R1, core Off-chip test resistance REXT, resistance R in chipIN, capacitance C1, PMOS transistor MP2,
PMOS transistor MP3 and PMOS transistor MP4；
It is brilliant that the grid of PMOS transistor MP1 connects the output end of operational amplifier A 0, one end of resistance R1 and PMOS simultaneously
The grid of body pipe MP2；One end of the other end connection capacitance C1 of resistance R1；
The drain terminal of PMOS transistor MP1 connects the other end of capacitance C1, the negative terminal of current source I1, resistance R in chip simultaneouslyIN
One end and operational amplifier A 0 normal phase input end；
The drain terminal of PMOS transistor MP2 simultaneously connects the grid and drain terminal, PMOS transistor MP4 of PMOS transistor MP3
The anode of grid and current source I3；
The drain terminal of PMOS transistor MP4 connects the adjustment terminal of LDO master units simultaneously；
The inverting input of operational amplifier A 0 connects core Off-chip test resistance R simultaneouslyEXTOne end, negative temperature coefficient electricity
Stream source ICTAT1Negative terminal and current source I0 negative terminal；
Negative temperature parameter current source ICTAT1Anode, the anode of current source I0, the anode of current source I1, PMOS transistor
The source of MP1, MP2, MP3, MP4 connect power vd D simultaneously；
Core Off-chip test resistance REXTThe other end, resistance R in chipINThe other end and the negative terminal of current source I3 connect simultaneously
Meet GND.
Beneficial effects of the present invention：It proposes a kind of LDO circuit with flow-route and temperature adjust automatically, changes common carry
The LDO of flow-route and temperature adjustment enables to the output voltage of LDO can be certainly using the realization method for manually adjusting output voltage
It is dynamic to change with the variation of temperature and technique, have already been through simulation results show.
Description of the drawings
Fig. 1 is the circuit diagram of the common LDO with flow-route and temperature adjust automatically；
Fig. 2 is the LDO functional block diagrams with flow-route and temperature adjust automatically of the present invention；
Fig. 3 is the LDO circuit schematic diagram with flow-route and temperature adjust automatically of the present invention；
Fig. 4 is that the LDO output voltages of the present invention vary with temperature figure；
Fig. 5 is the LDO output voltages of the present invention with technique change figure.
Specific implementation mode
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, how to be applied to the present invention whereby
Technological means solves technical problem, and the realization process for reaching technique effect can fully understand and implement.It needs to illustrate
As long as not constituting conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other,
It is formed by technical solution within protection scope of the present invention.
In illustrating the common LDO circuit with flow-route and temperature adjustment, due to using multiple switch S in circuitpControl
I processedPTATSize, ScControl ICTATSize, the final size for controlling LDO output voltages, needs first to test in this process by work
LDO output voltages under skill deviation and required temperature, finally manually adjust LDO output voltages, the low precision of adjustment and cannot
Moment makes corresponding adjustment.
The LDO circuit with flow-route and temperature adjust automatically of the present invention can be at the beginning of chip designs referring to Fig. 3
The size of comparison resistance inside and outside rational set temperature turning point and piece, with reach can be inclined according to chip operation situation and technique
Difference, constantly adjust automatically LDO outputs, greatly reduce the difficulty of adjustment, more reasonably optimize chip performance.
The specific embodiment for the LDO circuit with flow-route and temperature adjust automatically that Fig. 3 is provided, wherein LDO master units are
Temperature, technique adjustment object, LDO master units include operational amplifier A 1, resistance R2, resistance R3, resistance R4, PMOS transistor
MP5, current source I2 and NPN triode Q1；The inverting input of operational amplifier A 1 is grounded by resistance R2, NPN triode Q1；
Power vd D is also connect by current source I2；The in-phase input end of operational amplifier A 1 is grounded by resistance R4, also same by resistance R3
When connect output terminal Vout；The output end of operational amplifier A 1 is separately connected power vd D and output by PMOS transistor MP5
Terminal Vout.
The physical circuit of temperature adjustment circuit and technique adjustment circuit is not described further in detail.
The operation principle of temperature adjustment circuit：
By the electric current I with positive temperature coefficientPTATWith the electric current I with negative temperature coefficientCTAT2It is added in certain proportion,
The ratio can according to demand design at the beginning of chip designs, and electric current after being added is injected into the anti-phase input of A1 by mirror image
End generates the input voltage with temperature adjust automatically by resistance R2, therefore the output voltage Vout of LDO also variation with temperature
And change.
1, when LDO is operated in low-temperature zone, current source ICTAT2Initial current be more than current source IPATAInitial current,
NMOS transistor MN2 mirror current sources ICTAT2Electric current, on the branch road of NMOS transistor MN2, because of current source IPATAElectricity
Stream is less than current source ICTAT2Electric current, therefore flow into NMOS transistor MN3 without extra electric current.PMOS transistor MP7 is also without electricity
Stream outflow.
2, as current source ICTAT2With current source IPATAWhen varying with temperature, there are a temperature breakthrough (temperature threshold), this
When two beam current values it is equal, and the turning point can in advance artificially be arranged.
3, when environment temperature is more than turning point temperature, current source IPATAElectric current be more than current source ICTAT2Electric current.
NMOS transistor MN3 has extra electric current outflow.PMOS transistor MP7 also has electric current outflow.And the electric current can be with temperature
Increase and increase.
Using and rewrite formula (7), the output voltage relational expression of LDO is：
IMP7Electric current, I are flowed out for PMOS transistor MP72Electric current is flowed out for current source I2.IMP7For piecewise linearity electric current, when
When environment temperature reaches turning point, the output V of LDOoutIt will increase with the increase of temperature.
Based on above-mentioned analysis, it is seen that the present embodiment temperature adjustment circuit can bring following advantageous effect：
Being increased and raised electric current with temperature for temperature adjustment circuit output, is piecewise function, in a certain temperature breakthrough
Before, output current with the raising of temperature keeping parallelism, i.e., LDO is not adjusted.After a certain temperature breakthrough,
Output current is increased with the raising of temperature, is adjusted to LDO.This method can reach temperature in chip operation environment temperature
Degree turns ability after selecting a little and is constantly adjusted to LDO, substantially reduce the complexity of adjustment, and reasonably optimizing chip performance.
The operation principle of technique adjustment module：
By the electric current I with negative temperature coefficientCTAT1The electric current with positive temperature coefficient is generated by certain mirror-image fashion,
The electric current generates the negative temperature coefficient voltage V of voltage and NPN transistor Q1 with positive temperature coefficient by resistance R2beIt is comprehensive,
Zero-temperature coefficient voltage is generated in the inverting input of A1.Comparable chip internal resistance R is removed by amplifier A0INWith chip testing electricity
Hinder REXTSize, the corresponding Current Voltage for changing PMOS transistor MP4 and being injected into A1 inverting inputs, so that LDO energy
Enough sizes according to process deviation voluntarily adjust output voltage Vout。
The inverting input V of operational amplifier A 0nIt can be expressed as：
Vn=(ICTAT1+I0)·REXT (9)
Wherein ICTAT1For current source ICTAT1Size of current and have negative temperature coefficient, I0For current source I0 size of current, REXT
For core Off-chip test resistance REXTResistance value.
The normal phase input end V of operational amplifier A 0pIt can be expressed as：
Vp=(IMP1+I1)·RIN (10)
Wherein IMP1For the electric current that PMOS transistor MP1 flows through, I1For current source I1 electric currents, RINFor resistance R in chipINResistance
Value.
Using the short principle of void of operational amplifier, i.e.,：
Vp≈Vn (11)
(IMP1+I1)·RIN≈(ICTAT1+I0)·REXT (12)
I is set in formula (13)0=I1, and assume no fabrication error i.e. REXT=RIN, therefore formula (13) can be with
It is rewritten as：
IMP1≈ICTAT1 (14)
Therefore electric current IMP1And ICTAT1Negative temperature coefficient having the same.
The electric current that PMOS transistor MP2 mirror image PMOS transistors MP1 is flowed through, with the increase of temperature, the electric current of MP2 by
Decrescence small, the size of current of current source I3 does not vary with temperature, electric current I3-ICTAT1Increase with temperature and increase, the electric current of MP4 is big
It is small also to increase and increase with temperature.
The inverting input V of operational amplifier A 1nIt can be expressed as：
Vn=(I2+I3-ICTAT1)·R2+Vbe_Q1 (15)
Vbe_Q1For negative temperature coefficient voltage, (I2+I3-ICTAT1)·R2For positive temperature coefficient voltage, the two addition is rationally set
The size of current in formula (15) is set, V can be obtainednFor zero-temperature coefficient voltage.This zero-temperature coefficient voltage is in operation amplifier
The inverting input of device A1 generates, to prevent from causing the temperature coefficient of image current to change due to process deviation, finally
Zero warm reference voltage can not be generated.
Resistance R is set outside chipEXTResistance value and initial design piece in resistance RINSize is identical, using formula (13),
I is set0=I1。
1, the i.e. resistance R when error occurs in techniqueINMore than REXT, electric current IMP1It is corresponding to reduce, the branch of PMOS transistor MP2
Road electric current reduces, and the branch current of PMOS transistor MP3, MP4 increases, and the output voltage of LDO can be obtained using formula (8) principle
VoutIt will increase；
2, as resistance RINLess than REXT, electric current IMP1Corresponding to increase, the branch current of PMOS transistor MP2 increases, PMOS
The branch current of transistor MP3, MP4 reduce, and the output voltage V of LDO can be obtained using formula (8) principleoutIt will reduce；
That is RINRepresent the process deviation of chip entirety, RINIncrease, then LDO output voltages Vout increases；RINReduce, then
LDO output voltages Vout reduces.
Fig. 4 is that LDO output voltages vary with temperature figure.The electric current that curve 1 is flowed through by PMOS transistor MP7 in figure turns
Break appears in 59 DEG C of point M2 horizontal axis, and the turning point can be voluntarily arranged according to demand, when the temperature increases, the electricity flowed through
Stream gradually increases.Curve 2 is LDO output voltages, and turning point appears in 59 DEG C of point M4 horizontal axis, when the temperature increases, output voltage
Gradually increase.
Fig. 5 is LDO output voltages with technique change figure.R in figureINAbscissa represents the resistance of technique change.R is setIN=
RRXT=1k, RIN>When 1k Ω, LDO output voltages Vout increases, RIN<When 1k Ω, LDO output voltages Vout reduces.
Based on above-mentioned analysis, it is seen that the present embodiment technique adjustment circuit can bring following advantageous effect：
Generating zero-temperature coefficient voltage nearby in A1 inverting inputs can prevent process deviation from bringing to the greatest extent
Non-zero temperature coefficient voltage influence, chip interior resistance RINWith chip testing resistance REXTSize compares the adjust automatically of generation
Current Voltage so that LDO output voltages can also be followed by adjust automatically, substantially reduce the complexity of adjustment, and rationally excellent
Chip performance is changed.
LDO proposed by the present invention with flow-route and temperature adjust automatically, which is different from common same type circuit, needs circuit to survey
LDO output voltages are manually adjusted after examination, but can voluntarily be adjusted automatically according to the variation of flow-route and temperature, and adjustment process is reduced
Complexity, improve the precision of output voltage, give chip provide a rational supply voltage.
Although disclosed herein embodiment it is as above, the content is only to facilitate understanding the present invention and adopting
Embodiment is not limited to the present invention.Any those skilled in the art to which this invention pertains are not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and change can be made in the implementing form and in details,
But the scope of patent protection of the present invention, still should be subject to the scope of the claims as defined in the appended claims.
Claims (3)
1. the LDO with flow-route and temperature adjust automatically, including LDO master units, LDO master units include operational amplifier A 1, electricity
Hinder R2, resistance R3, resistance R4, PMOS transistor MP5, current source I2 and NPN triode Q1；The anti-phase input of operational amplifier A 1
End is grounded by resistance R2, NPN triode Q1；Power vd D is also connect by current source I2；The in-phase input end of operational amplifier A 1
It is grounded by resistance R4, output terminal Vout is also connected by resistance R3 simultaneously；The output end of operational amplifier A 1 passes through PMOS
Transistor MP5 is separately connected power vd D and output terminal Vout；
It is characterized in that, further including temperature adjustment circuit and technique adjustment circuit；Inverting input, the electric current of operational amplifier A 1
The negative terminal of source I2 and the public terminal of resistance R2 are as adjustment terminal, the temperature tune of the adjustment terminal cut-in temperature adjustment circuit
The technique adjustment signal of entire signal and technique adjustment circuit；
When environment temperature is more than temperature threshold, temperature adjustment circuit controls the output voltage of LDO master units with the increase of temperature
And increase；
The inverting input of technique adjustment circuit control operational amplifier A 1 generates zero-temperature coefficient voltage, to adjust chip entirety
The deviation of technique, when chip integrated artistic deviation is bigger than normal, the output voltage of LDO master units increases therewith, otherwise reduces.
2. carrying the LDO of flow-route and temperature adjust automatically according to claim 1, which is characterized in that temperature adjustment circuit packet
Include negative temperature parameter current source ICTAT2, positive temperature coefficient current source IPTAT, NMOS transistor MN1, NMOS transistor MN2, NMOS
Transistor MN3, NMOS transistor MN4, PMOS transistor MP6 and PMOS transistor MP7；
The grid of NMOS transistor MN1 connects its drain terminal, the grid of NMOS transistor MN2 and negative temperature parameter current source simultaneously
ICTAT2Negative terminal；
The drain terminal of NMOS transistor MN2 connects the drain terminal of NMOS transistor MN3 and its grid of grid, NMOS transistor MN4 simultaneously
Pole, positive temperature coefficient current source IPTATNegative terminal；
The drain terminal of NMOS transistor MN4 connects the drain terminal of PMOS transistor MP6 and its grid of grid, PMOS transistor MP7 simultaneously
Pole；
The source of NMOS transistor MN1, MN2, MN3, MN4 connect GND simultaneously；
Negative temperature parameter current source ICTAT2Anode, positive temperature coefficient current source IPTATAnode, PMOS transistor MP6 source
Power vd D is connected with the source of PMOS transistor MP7 simultaneously；
The adjustment terminal of the drain terminal connection LDO master units of PMOS transistor MP7.
3. the LDO according to claim 1 or claim 2 with flow-route and temperature adjust automatically, which is characterized in that technique adjustment circuit
Including operational amplifier A 0, negative temperature parameter current source ICTAT1, current source I0, current source I1, current source I3, resistance R1, chip
Outer test resistance REXT, resistance R in chipIN, capacitance C1, PMOS transistor MP2, PMOS transistor MP3 and PMOS transistor MP4；
The grid of PMOS transistor MP1 connects the output end of operational amplifier A 0, one end of resistance R1 and PMOS transistor simultaneously
The grid of MP2；One end of the other end connection capacitance C1 of resistance R1；
The drain terminal of PMOS transistor MP1 connects the other end of capacitance C1, the negative terminal of current source I1, resistance R in chip simultaneouslyINOne
The normal phase input end at end and operational amplifier A 0；
The drain terminal of PMOS transistor MP2 connects the grid of the grid and drain terminal, PMOS transistor MP4 of PMOS transistor MP3 simultaneously
With the anode of current source I3；
The drain terminal of PMOS transistor MP4 connects the adjustment terminal of LDO master units simultaneously；
The inverting input of operational amplifier A 0 connects core Off-chip test resistance R simultaneouslyEXTOne end, negative temperature parameter current source
ICTAT1Negative terminal and current source I0 negative terminal；
Negative temperature parameter current source ICTAT1Anode, the anode of current source I0, the anode of current source I1, PMOS transistor MP1,
The source of MP2, MP3, MP4 connect power vd D simultaneously；
Core Off-chip test resistance REXTThe other end, resistance R in chipINThe other end and the negative terminal of current source I3 connect simultaneously
GND。
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810130031.7A CN108319319B (en) | 2018-02-08 | 2018-02-08 | LDO with flow-route and temperature adjust automatically |
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| CN201810130031.7A CN108319319B (en) | 2018-02-08 | 2018-02-08 | LDO with flow-route and temperature adjust automatically |
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| CN108319319B CN108319319B (en) | 2019-10-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI729957B (en) * | 2019-11-05 | 2021-06-01 | 聯發科技股份有限公司 | Reference voltage buffer |
| US20210305804A1 (en) * | 2020-03-24 | 2021-09-30 | Analog Devices International Unlimited Company | Bipolar junction transistor heater circuit |
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| US6969982B1 (en) * | 2003-10-03 | 2005-11-29 | National Semiconductor Corporation | Voltage regulation using current feedback |
| CN1825240A (en) * | 2006-03-24 | 2006-08-30 | 启攀微电子（上海）有限公司 | Low voltage difference linear voltage stabilizer circuit |
| CN102495654A (en) * | 2011-11-25 | 2012-06-13 | 上海艾为电子技术有限公司 | Low-dropout regulator and integrated circuit system |
| CN105739587A (en) * | 2016-02-23 | 2016-07-06 | 无锡中微亿芯有限公司 | Low dropout regulator which can output large current and has adjustable temperature coefficient |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6969982B1 (en) * | 2003-10-03 | 2005-11-29 | National Semiconductor Corporation | Voltage regulation using current feedback |
| CN1825240A (en) * | 2006-03-24 | 2006-08-30 | 启攀微电子（上海）有限公司 | Low voltage difference linear voltage stabilizer circuit |
| CN102495654A (en) * | 2011-11-25 | 2012-06-13 | 上海艾为电子技术有限公司 | Low-dropout regulator and integrated circuit system |
| CN105739587A (en) * | 2016-02-23 | 2016-07-06 | 无锡中微亿芯有限公司 | Low dropout regulator which can output large current and has adjustable temperature coefficient |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI729957B (en) * | 2019-11-05 | 2021-06-01 | 聯發科技股份有限公司 | Reference voltage buffer |
| US11233513B2 (en) | 2019-11-05 | 2022-01-25 | Mediatek Inc. | Reference voltage buffer with settling enhancement |
| US20210305804A1 (en) * | 2020-03-24 | 2021-09-30 | Analog Devices International Unlimited Company | Bipolar junction transistor heater circuit |
| US11735902B2 (en) * | 2020-03-24 | 2023-08-22 | Analog Devices International Unlimited Company | Bipolar junction transistor heater circuit |
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| Publication number | Publication date |
|---|---|
| CN108319319B (en) | 2019-10-15 |
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Inventor after: Zhou Yuanyuan Inventor after: Li Jinghu Inventor after: Chen Fujie Inventor after: Tu Hanghui Inventor after: Luo Zhicong Inventor after: Chen Riqing Inventor before: Zhou Yuanyuan Inventor before: Li Jinghu Inventor before: Chen Fujie Inventor before: Tu Hanghui |