CN105892548B - Reference voltage generation circuit with temperature compensating function - Google Patents
Reference voltage generation circuit with temperature compensating function Download PDFInfo
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- CN105892548B CN105892548B CN201410188122.8A CN201410188122A CN105892548B CN 105892548 B CN105892548 B CN 105892548B CN 201410188122 A CN201410188122 A CN 201410188122A CN 105892548 B CN105892548 B CN 105892548B
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Abstract
A reference voltage generation circuit with a temperature compensating function relates to the reference voltage source technical field; the reference voltage generation circuit comprises a positive temperature coefficient voltage generation circuit and a similar LDO circuit connected in sequence; the positive temperature coefficient voltage generation circuit comprises single-stage or multistage unit circuits, wherein each stage unit circuit comprises a bias current source P using a MOS pipe and two NMOS pipes; unit circuits of various stages are cascaded in sequence; the grid electrode of NMOS pipe A and the grid electrode of NMOS pipe B in each stage unit circuit are connected, and respectively connected with the drain electrode of the NMOS pipe A and the drain electrode of the bias current source P; the source electrode of the NMOS pipe A and the drain electrode of the NMOS pipe B are connected to serve as an output node; the current generated by the bias current source P passes the NMOS pipe A and NMOS pipe B of the same stage, and is connected the source electrode of the NMOS pipe A and drain electrode of the NMOS pipe B of the next stage unit circuit through the source electrode of the NMOS pipe B of the previous stage; the similar LDO circuit comprises an operational amplifier and an output unit; the reference voltage generation circuit can effectively reduce system power consumption without obviously increasing area, and has the temperature compensating function.
Description
Technical field
The present invention relates to reference voltage source technical field, the reference voltage particularly with temperature compensation function produces electric
Road.
Background technology
Voltage reference source is one of component units indispensable in many circuit systems, is usually used in as high performance simulation
Circuit or digital circuit blocks provide the reference voltage of a low-temperature coefficient, to improve the performance of circuit.
In prior art, integrated circuit fields, traditional Voltage Reference source circuit is usually used by classical bipolar transistor
The band-gap reference circuit that pipe is constituted, its ultimate principle is because the base-emitter junction of bipolar transistor has negative temperature characteristic；
On the other hand, when the collector current of bipolar transistor is different, there is difference in the temperature curve of its base-emitter junction,
Base-emitter junction both end voltage when different electric currents flows through two different bipolar transistors, on two transistors
Difference but have positive temperature coefficient.Big ratio is fitted by the voltage amplification that this is had positive temperature coefficient negative with having
The junction voltage of temperature coefficient is added, it is possible to obtain the voltage reference source that a temperature coefficient obtains certain suppression.
However, the band-gap reference circuit that traditional bipolar transistor is constituted is not particularly suited for low power dissipation design.Reason is such as
Under：First, current amplification factor BETA values of traditional bipolar transistor and non-constant, when collector current is less than certain threshold
During value, BETA values can be with the different and dull significant changes of electric current, and this is caused when bias current very little, using different size
The BETA values of two bipolar transistors that electric current is biased there may be dramatically different so that matching becomes very poor；
Secondly, the band-gap reference circuit that traditional bipolar transistor is constituted is usually used operational amplifier by the difference DELTA of junction voltage
VBE takes out, and is placed in sampling resistor two ends, and the electric current for flowing through sampling resistor also constitutes the Static Electro in band-gap reference circuit
Stream, therefore in low power dissipation design, will obtain minimum quiescent current, it is necessary to using great sampling resistor value and more huge
Amplification resistance resistance, occupy huge area while causing the impact increasing of excavating technology gradient and stress；Third, passing
Regiment commander's gap reference circuit can only produce the voltage of 1.25V or so, and be unsatisfactory for actually used needs.
For above reason, have to abandon the use of traditional bandgap reference circuit in existing low power dissipation design, very
To sometimes having to using not temperature compensated voltage reference source, the performance of this circuit on rear class causes impact, increased
The design difficulty of late-class circuit.
The content of the invention
For above-mentioned problems of the prior art, it is an object of the invention to provide a kind of with temperature compensation function
Reference voltage generating circuit.It reduces system power dissipation in the case where area is not dramatically increased, effectively, and with temperature-compensating work(
Energy.
In order to reach foregoing invention purpose, technical scheme is realized as follows：
A kind of reference voltage generating circuit with temperature compensation function, it is structurally characterized in that, it includes what is be sequentially connected
Positive temperature coefficient voltage generation circuit and class LDO circuit.Positive temperature coefficient voltage generation circuit output with positive temperature coefficient
Voltage by class LDO circuit with have negative temperature coefficient voltage be overlapped after, class LDO circuit outfan output it is low
The reference voltage of temperature coefficient.The positive temperature coefficient voltage generation circuit is made up of single-stage or multi-level unit circuit, often
Level element circuit is included using bias current sources P and two NMOS tubes of metal-oxide-semiconductor.Element circuit concatenated in order at different levels, per grade of list
The grid of NMOS tube A in first circuit is respectively connected to the drain electrode of NMOS tube A and bias current after being connected with the grid of NMOS tube B
The drain electrode of source P, the source electrode of NMOS tube A is connected as output node with the drain electrode of NMOS tube B.The electricity that bias current sources P are produced
Flow the source for being connected to NMOS tube A in next stage element circuit by the source electrode of NMOS tube B after this grade of NMOS tube A and NMOS tube B
Pole and the drain electrode of NMOS tube B.The source ground of NMOS tube B in afterbody element circuit, NMOS tube A in first order element circuit
The junction point that source electrode drains with NMOS tube B is used as output node.The class LDO circuit includes operational amplifier and output unit.
Operational amplifier includes transistor zero, transistor one, transistor two, transistor three and transistor four, and output unit includes power
Pipe five, power tube six and power tube seven.The wherein output node of the grid of transistor zero and positive temperature coefficient voltage generation circuit
It is connected, the source electrode of transistor zero is connected with the source electrode of transistor one and is connected to the drain electrode of transistor four.The grid of transistor two
It is connected and is connected to the drain electrode of transistor three with the grid of transistor three, transistor two constitutes self-biasing current mirror with transistor three.
The drain electrode of transistor zero be connected with the drain electrode of transistor two and be connected to output unit power tube six grid, the grid of transistor one
Pole is connected respectively with the drain and gate of output unit power tube five, and the source electrode of power tube five is connected with the drain electrode of power tube six
And using the node as required reference voltage point.The grid of power tube seven is connected to the grid of transistor four, power tube seven
Drain electrode connect the drain electrode of power tube five, the source ground of power tube seven.The multistage element circuit is by except last
The source electrode Jing switches ground connection of NMOS tube B is controlled into the series of whole circuit and to circuit in other element circuits outside one-level
Output is adjusted.
In said reference voltage generation circuit, NMOS tube A and NMOS tube B in every grade of element circuit is operated in
Sub-threshold region.
The present invention as a result of said structure, because NMOS tube A in every grade of element circuit and NMOS tube B are operated in
Sub-threshold region, therefore pass through all very little per the electric current of one-level bias current sources P.And per grade of NMOS tube A is connected with NMOS tube B
Connection, is conducive to optimizing the matching in the case of subthreshold value, is especially suitable for the use of low consumption circuit.Positive temperature coefficient voltage is produced
The voltage with positive temperature coefficient of raw circuit output is overlapped by class LDO circuit with the voltage with negative temperature coefficient
Afterwards, the outfan in class LDO circuit exports the reference voltage Vref of low-temperature coefficient.The present invention compared with the existing technology,
System power dissipation can be effectively reduced, and with temperature compensation function.
With reference to the accompanying drawings and detailed description the invention will be further described.
Description of the drawings
Fig. 1 is the structural representation of the embodiment of the present invention；
Fig. 2 is the single step arrangement schematic diagram of positive temperature coefficient voltage generation circuit in the embodiment of the present invention；
Fig. 3 is output voltage characteristic schematic diagram in the embodiment of the present invention.
Specific embodiment
Reference voltage generating circuit of the present invention with temperature compensation function includes the positive temperature coefficient voltage being sequentially connected
Produce circuit 11 and class LDO circuit 22.The voltage with positive temperature coefficient of the output of positive temperature coefficient voltage generation circuit 11 leads to
Cross class LDO circuit 22 with have negative temperature coefficient voltage be overlapped after, class LDO circuit 22 outfan export low temperature
The reference voltage Vref of coefficient.Positive temperature coefficient voltage generation circuit 11 is made up of single-stage or multi-level unit circuit, per grade
Element circuit is included using bias current sources P and two NMOS tubes of metal-oxide-semiconductor.Element circuit concatenated in order at different levels, every grade of unit
The grid of NMOS tube A in circuit is respectively connected to the drain electrode of NMOS tube A and bias current sources after being connected with the grid of NMOS tube B
The drain electrode of P, the source electrode of NMOS tube A is connected with the drain electrode of NMOS tube B, and the electric current that bias current sources P are produced passes through this grade of NMOS
The leakage of the source electrode of NMOS tube A and NMOS tube B in next stage element circuit is connected to after pipe A and NMOS tube B by the source electrode of NMOS tube B
Pole.The source ground of NMOS tube B in afterbody element circuit, NMOS tube A source electrode leaks with NMOS tube B in first order element circuit
The junction point of pole is used as output node.Class LDO circuit 22 includes operational amplifier and output unit, and operational amplifier includes crystal
The M of pipe zero0, the M of transistor one1, the M of transistor two2, the M of transistor three3With the M of transistor four4, output unit include the M of power tube five5, power
The M of pipe six6With the M of power tube seven7.The wherein M of transistor zero0Grid and positive temperature coefficient voltage generation circuit 11 output node phase
Connection, the M of transistor zero0Source electrode and the M of transistor one1Source electrode be connected and be connected to the M of transistor four4Drain electrode, the M of transistor two2's
Grid and the M of transistor three3Grid be connected and be connected to the M of transistor three3Drain electrode, the M of transistor two2With the M of transistor three3Constitute certainly
Bias current mirror.The M of transistor zero0Drain electrode and the M of transistor two2Drain electrode be connected and be connected to the M of power tube six of output unit6's
Grid, the M of transistor one1Grid respectively with the M of power tube five5Drain and gate be connected.The M of power tube five5Source electrode and power
The M of pipe six6Drain electrode be connected and using the node as required reference voltage point, the M of power tube seven7Grid be connected to transistor
Four M4Grid, the M of power tube seven7Drain electrode meet the M of power tube five5Drain electrode, the M of power tube seven7Source ground.Multistage
Element circuit is whole to control by the way that the source electrode Jing of NMOS tube B is switched into ground connection in other element circuits except the last
The series of individual circuit and circuit output is adjusted.NMOS tube A and NMOS tube B in every grade of element circuit is operated in subthreshold
Value area.
With reference to Fig. 1, positive temperature coefficient voltage generation circuit 11 is by metal-oxide-semiconductor MP0, metal-oxide-semiconductor MP1, metal-oxide-semiconductor MP2, metal-oxide-semiconductor MP3、
Metal-oxide-semiconductor MP4And it is operated in NMOS tube M of sub-threshold regionA0, NMOS tube MA1, NMOS tube MA2, NMOS tube MA3, NMOS tube MA4、
NMOS tube MB0, NMOS tube MB1, NMOS tube MB2, NMOS tube MB3With NMOS tube MB4Composition.Each unit circuit sequence is cascaded, NMOS tube
MA0Grid and NMOS tube MB0Grid be connected after be respectively connected to NMOS tube MA0Drain electrode and metal-oxide-semiconductor MP0Drain electrode, NMOS tube
MA0Source electrode and NMOS tube MB0Drain electrode be connected, bias current sources metal-oxide-semiconductor MP0The electric current of generation is by this grade of NMOS tube MB0Source
Pole is connected to NMOS tube M in next stage element circuitA1Source electrode and NMOS tube MB1Drain electrode.NMOS tube MA1Grid and NMOS
Pipe MB1Grid be connected after be respectively connected to NMOS tube MA1Drain electrode and metal-oxide-semiconductor MP1Drain electrode, bias current sources metal-oxide-semiconductor MP1Produce
Raw electric current is by this grade of NMOS tube MB1Source electrode be connected to NMOS tube M in next stage element circuitA2Source electrode and NMOS tube MB2's
Drain electrode.NMOS tube MA2Grid and NMOS tube MB2Grid be connected after be respectively connected to NMOS tube MA2Drain electrode and metal-oxide-semiconductor MP2's
Drain electrode, bias current sources metal-oxide-semiconductor MP2The electric current of generation is by this grade of NMOS tube MB2Source electrode be connected in next stage element circuit
NMOS tube MA3Source electrode and NMOS tube MB3Drain electrode.NMOS tube MA3Grid and NMOS tube MB3Grid be connected after connect respectively
To NMOS tube MA3Drain electrode and metal-oxide-semiconductor MP3Drain electrode, bias current sources metal-oxide-semiconductor MP3The electric current of generation is by this grade of NMOS tube MB3's
Source electrode is connected to NMOS tube M in next stage element circuitA4Source electrode and NMOS tube MB4Drain electrode.NMOS tube MA4Grid with
NMOS tube MB4Grid be connected after be respectively connected to NMOS tube MA4Drain electrode and metal-oxide-semiconductor MP4Drain electrode, bias current sources metal-oxide-semiconductor
MP4The electric current of generation is by this grade of NMOS tube MB4Source ground.
The M of power tube five in output unit5There is provided the voltage with negative temperature coefficient, the M of transistor one1Grid
Value is fixed on V21Left and right, the M of power tube seven7It is used for the M of power tube five there is provided one5The tail current source of biasing.The M of transistor one1's
The metal-oxide-semiconductor M that grid is connected with output unit diode5Grid leak be connected, the M of power tube five5Grid, drain voltage is also clamped
In voltage V21Value.Due to the M of power tube five5Electric current between upper source electrode, drain electrode is only relevant with tail current source, it is possible to think power
The M of pipe five5Upper source electrode, drain voltage are a voltage Vs unrelated with loadGS5, the voltage is an electricity with negative temperature coefficient
Pressure, and due to the M of power tube five5Source voltage is with positive temperature coefficient voltage V21, by rational setting, V can be madeGS5With
V21Temperature coefficient absolute value approximately equal.And the value of output reference voltage VREF is VGS5With V21Sum, therefore be believed that
We have obtained a temperature independent reference voltage VREF。
The operation principle of circuit of the present invention is specifically described below.
Consider the working condition of positive temperature coefficient voltage generation circuit 11 in Fig. 1.
Referring to shown in Fig. 2, the output V of single-level circuitOSituation.NMOS tube A0MA0With NMOS tube B0MB0It is operated in subthreshold value
Area.Define metal-oxide-semiconductor P0MP0The bias current of generation is I0, then NMOS tube A0M is flow throughA0With NMOS tube B0MB0Electric current IDSAWith
IDSBIt is equal.Define NMOS tube B0MB0Gate source voltage be VGSB, NMOS tube A0MA0Gate source voltage be VGSA, NMOS tube A0MA0's
Breadth length ratio is SA0, NMOS tube B0MB0Breadth length ratio be SB0, can be obtained by the current formula of sub-threshold region,
（1）
（2）
Due to IDSAWith IDSBIt is equal, so
（3）
And VGSA=VGSB-VO, so
（4）
Wherein, t refers to absolute temperature, and n, k are related to technique, so VO is directly proportional to temperature.
Situation when considering that Pyatyi is cascaded.If now switch is turned off, and electric current source size now at different levels is identical, then often
The NMOS tube of the lower floor of one-level I big than the electric current that prime lower floor NMOS tube is flowed through0, and the electric current perseverance for flowing through upper strata NMOS tube is
I0.The breadth length ratio of upper and lower NMOS tubes at different levels is respectively SAWith SB, definition nkT/q is VT, it is easy to get,
（5）
There is the voltage of positive temperature coefficient because VT is one, therefore V21 is the voltage with positive temperature coefficient.Can be with
It is easy to by formula（5）Be generalized to more generally situation, i.e., when positive temperature coefficient voltage generation circuit 11 has n levels, output
Voltage
（6）
By formula（6）Can easily by changing the series for accessing positive temperature coefficient voltage generation circuit 11 come to defeated
Go out voltage to be adjusted on a large scale.
Referring to Fig. 1, due to M0-M4Constitute the effect of operation amplifier circuit, the M of power tube five5Drain electrode be fixed on
On the magnitude of voltage of V21, therefore the voltage for obtaining VREF is,
（7）
Wherein,
VGS5=VTHP+VOV （8）
Under low power consumpting state, VOVVery little, and VTHPTypically there is negative temperature coefficient.By suitable adjustment, make
V21Positive temperature coefficient and VGS5Negative temperature coefficient offset, be obtained a low-temperature coefficient reference voltage VREF, one
Sample result is shown in Fig. 3.Maximum temperature coefficient meets common requirement in 46 PPM or so.
Said method can be generalized to the realization of more stages.
By the reference voltage source of said method realization due to without being biased to bipolar transistor, having avoided using double
Gain mismatch problem under the low current condition occurred during bipolar transistor.On the other hand, because the circuit is adopted completely
Metal-oxide-semiconductor is realized, it is to avoid the use of passive device so that the area under low power consumpting state is unlikely to too big.To sum up, the invention
The use of low-power dissipation system is well suited for, and relatively conventional design is more advantageous on area, with good performance and Jing
Ji effect.
Claims (2)
1. a kind of reference voltage generating circuit with temperature compensation function, it is characterised in that it includes the positive temperature being sequentially connected
Degree coefficient voltages produce circuit（11）With class LDO circuit（22）, positive temperature coefficient voltage generation circuit（11）Output with just
The voltage of temperature coefficient passes through class LDO circuit（22）After being overlapped with the voltage with negative temperature coefficient, in class LDO circuit
（22）Outfan export low-temperature coefficient reference voltage（Vref）；The positive temperature coefficient voltage generation circuit（11）
It is made up of single-stage or multi-level unit circuit, every grade of element circuit is included using bias current sources P and two NMOS tubes of metal-oxide-semiconductor,
Element circuit concatenated in order at different levels, the grid of NMOS tube A in every grade of element circuit is distinguished after being connected with the grid of NMOS tube B
The drain electrode of NMOS tube A and the drain electrode of bias current sources P are connected to, the source electrode of NMOS tube A is connected with the drain electrode of NMOS tube B, are biased
The electric current that current source P is produced is connected to next stage unit electricity after this grade of NMOS tube A and NMOS tube B by the source electrode of NMOS tube B
The drain electrode of the source electrode of NMOS tube A and NMOS tube B in road, the source ground of NMOS tube B in afterbody element circuit, first order list
The junction point that NMOS tube A source electrode drains with NMOS tube B in first circuit is used as output node；The class LDO circuit（22）Including fortune
Amplifier and output unit are calculated, operational amplifier includes transistor zero（M0）, transistor one（M1）, transistor two（M2）, transistor
Three（M3）With transistor four（M4）, output unit include power tube five（M5）, power tube six（M6）With power tube seven（M7）, wherein brilliant
Body pipe zero（M0）Grid and positive temperature coefficient voltage generation circuit（11）Output node be connected, transistor zero（M0）Source
Pole and transistor one（M1）Source electrode be connected and be connected to transistor four（M4）Drain electrode, transistor two（M2）Grid and transistor
Three（M3）Grid be connected and be connected to transistor three（M3）Drain electrode, transistor two（M2）With transistor three（M3）Constitute automatic biasing
Current mirror, transistor zero（M0）Drain electrode and transistor two（M2）Drain electrode be connected and be connected to the power tube six of output unit（M6）
Grid, transistor one（M1）Grid respectively with power tube five（M5）Drain and gate be connected, power tube five（M5）Source
Pole and power tube six（M6）Drain electrode be connected and using the node as required reference voltage point, power tube seven（M7）Grid
It is connected to transistor four（M4）Grid, power tube seven（M7）Drain electrode connect power tube five（M5）Drain electrode, power tube seven
（M7）Source ground, the multistage element circuit is by other element circuits in addition to afterbody and the first order
The source electrode Jing switches ground connection of NMOS tube B is controlled the series of whole circuit and circuit output is adjusted.
2. the reference voltage generating circuit with temperature compensation function according to claim 1, it is characterised in that described every
NMOS tube A and NMOS tube B in level element circuit is operated in sub-threshold region.
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106774594B (en) * | 2017-02-16 | 2018-02-16 | 珠海格力电器股份有限公司 | Low Drift Temperature reference voltage circuit |
| CN107015595A (en) * | 2017-05-03 | 2017-08-04 | 苏州大学 | It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source |
| CN107894803A (en) * | 2017-10-25 | 2018-04-10 | 丹阳恒芯电子有限公司 | A kind of bias-voltage generating circuit in Internet of Things |
| CN107704008A (en) * | 2017-10-25 | 2018-02-16 | 丹阳恒芯电子有限公司 | A kind of low-power consumption reference circuit |
| CN108427471A (en) * | 2018-06-05 | 2018-08-21 | 北京中电华大电子设计有限责任公司 | A kind of zero-temperature coefficient super low-power consumption reference voltage circuit |
| CN112817362B (en) * | 2020-12-31 | 2022-05-24 | 广东大普通信技术股份有限公司 | Low-temperature coefficient reference current and voltage generating circuit |
| CN113311899B (en) * | 2021-08-02 | 2021-11-16 | 四川蕊源集成电路科技有限公司 | Voltage regulator |
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| CN202394144U (en) * | 2011-12-27 | 2012-08-22 | 东南大学 | Low temperature offset CMOS band-gap reference voltage source with index temperature compensation function |
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| CN203825522U (en) * | 2014-05-07 | 2014-09-10 | 北京同方微电子有限公司 | Reference voltage generating circuit with temperature compensating function |
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| KR20120113592A (en) * | 2011-04-05 | 2012-10-15 | 한양대학교 산학협력단 | Reference power source using current compensation |
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| CN202394144U (en) * | 2011-12-27 | 2012-08-22 | 东南大学 | Low temperature offset CMOS band-gap reference voltage source with index temperature compensation function |
| CN203299680U (en) * | 2013-06-01 | 2013-11-20 | 湘潭芯力特电子科技有限公司 | Reference current source circuit of compensation resistor temperature drift coefficient |
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Effective date of registration: 20221229 Address after: 063000 Xinxing Electronic Industrial Park, Yutian County, Tangshan City, Hebei Province Patentee after: TANGSHAN GUOXIN JINGYUAN ELECTRONICS Co.,Ltd. Address before: 100083 18 floor, West Tower, block D, Tongfang science and Technology Plaza, 1 Wang Zhuang Road, Wudaokou, Haidian District, Beijing. Patentee before: ZIGUANG TONGXIN MICROELECTRONICS CO.,LTD. Patentee before: TANGSHAN GUOXIN JINGYUAN ELECTRONICS Co.,Ltd. |