CN105892548A - Reference voltage generation circuit with temperature compensating function - Google Patents
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Abstract
A reference voltage generation circuit with a temperature compensating function relates to the reference voltage source technical field; the reference voltage generation circuit comprises a positive temperature coefficient voltage generation circuit and a similar LDO circuit connected in sequence; the positive temperature coefficient voltage generation circuit comprises single-stage or multistage unit circuits, wherein each stage unit circuit comprises a bias current source P using a MOS pipe and two NMOS pipes; unit circuits of various stages are cascaded in sequence; the grid electrode of NMOS pipe A and the grid electrode of NMOS pipe B in each stage unit circuit are connected, and respectively connected with the drain electrode of the NMOS pipe A and the drain electrode of the bias current source P; the source electrode of the NMOS pipe A and the drain electrode of the NMOS pipe B are connected to serve as an output node; the current generated by the bias current source P passes the NMOS pipe A and NMOS pipe B of the same stage, and is connected the source electrode of the NMOS pipe A and drain electrode of the NMOS pipe B of the next stage unit circuit through the source electrode of the NMOS pipe B of the previous stage; the similar LDO circuit comprises an operational amplifier and an output unit; the reference voltage generation circuit can effectively reduce system power consumption without obviously increasing area, and has the temperature compensating function.
Description
Technical Field
The invention relates to the technical field of reference voltage sources, in particular to a reference voltage generating circuit with a temperature compensation function.
Background
The voltage reference source is one of indispensable constituent units in many circuit systems, and is often used to provide a reference voltage with a low temperature coefficient for high-performance analog circuits or digital circuit modules, so as to improve the performance of the circuit.
In the prior art, in the field of integrated circuits, a conventional voltage reference source circuit generally uses a band-gap reference circuit composed of a classical bipolar transistor, and the basic principle is that a base-emitter junction of the bipolar transistor has a negative temperature characteristic; on the other hand, when the collector currents of the bipolar transistors are different, the temperature curves of the base-emitter junctions of the bipolar transistors are different, and when different currents flow through two different bipolar transistors, the difference of the voltages across the base-emitter junctions of the two transistors has a positive temperature coefficient. By adding the voltage with positive temperature coefficient and the junction voltage with negative temperature coefficient, a voltage reference source with certain suppressed temperature coefficient can be obtained.
However, the conventional bipolar transistor-based bandgap reference circuit is not suitable for low power design. The reason is as follows: firstly, the BETA value of the current amplification factor of the traditional bipolar transistor is not constant, and when the collector current is smaller than a certain threshold value, the BETA value changes monotonously and obviously along with the difference of the current, so that when the bias current is small, the BETA values of two bipolar transistors biased by adopting currents with different magnitudes are possibly different obviously, and the matching property becomes poor; secondly, a band gap reference circuit formed by a traditional bipolar transistor generally uses an operational amplifier to take out a difference value delta VBE of junction voltage and place the difference value delta VBE at two ends of a sampling resistor, and current flowing through the sampling resistor also forms static current in the band gap reference circuit, so that in low-power-consumption design, extremely small static current needs to be obtained, a very large sampling resistance value and a resistance value of a larger amplification resistor need to be adopted, a huge area is occupied, and influence of a process gradient and stress is increased; thirdly, the traditional band-gap reference circuit can only generate about 1.25V voltage and does not meet the requirement of practical use.
For the above reasons, the conventional bandgap reference circuit has to be abandoned in the existing low power consumption design, and even a voltage reference source without temperature compensation has to be adopted sometimes, which affects the performance of the circuit at the subsequent stage and increases the design difficulty of the circuit at the subsequent stage.
Disclosure of Invention
In view of the above problems in the prior art, it is an object of the present invention to provide a reference voltage generating circuit with temperature compensation function. The temperature compensation circuit can effectively reduce the power consumption of the system without increasing the area remarkably, and has a temperature compensation function.
In order to achieve the above object, the technical solution of the present invention is implemented as follows:
a reference voltage generating circuit with a temperature compensation function is structurally characterized by comprising a positive temperature coefficient voltage generating circuit and an LDO-like circuit which are sequentially connected. After the voltage with the positive temperature coefficient output by the positive temperature coefficient voltage generating circuit is superposed with the voltage with the negative temperature coefficient through the LDO-like circuit, the reference voltage with the low temperature coefficient is output at the output end of the LDO-like circuit. The positive temperature coefficient voltage generating circuit consists of a single-stage or multi-stage unit circuit, and each stage of unit circuit comprises a bias current source P adopting an MOS tube and two NMOS tubes. The unit circuits of all stages are sequentially cascaded, the grid electrode of an NMOS tube A in each stage of unit circuit is connected with the grid electrode of an NMOS tube B and then respectively connected to the drain electrode of the NMOS tube A and the drain electrode of a bias current source P, and the source electrode of the NMOS tube A is connected with the drain electrode of the NMOS tube B to serve as an output node. The current generated by the bias current source P passes through the NMOS tube A and the NMOS tube B of the stage and is connected to the source electrode of the NMOS tube A and the drain electrode of the NMOS tube B in the next stage unit circuit by the source electrode of the NMOS tube B. The source electrode of the NMOS tube B in the last stage unit circuit is grounded, and the connection point of the source electrode of the NMOS tube A and the drain electrode of the NMOS tube B in the first stage unit circuit is used as an output node. The LDO-like circuit comprises an operational amplifier and an output unit. The operational amplifier comprises a transistor zero, a transistor I, a transistor II, a transistor III and a transistor IV, and the output unit comprises a power tube five, a power tube six and a power tube seven. The grid electrode of the transistor zero is connected with the output node of the positive temperature coefficient voltage generating circuit, and the source electrode of the transistor zero is connected with the source electrode of the transistor I and connected to the drain electrode of the transistor IV in parallel. And the grid electrode of the second transistor is connected with the grid electrode of the third transistor and is connected to the drain electrode of the third transistor, and the second transistor and the third transistor form a self-bias current mirror. The drain electrode of the transistor zero is connected with the drain electrode of the transistor II and connected to the grid electrode of the power tube six of the output unit, the grid electrode of the transistor I is respectively connected with the drain electrode of the power tube five of the output unit and the grid electrode of the power tube six, the source electrode of the power tube five is connected with the drain electrode of the power tube six, and the node is used as a required reference voltage point. The grid electrode of the power tube seven is connected to the grid electrode of the transistor four, the drain electrode of the power tube seven is connected with the drain electrode of the power tube five, and the source electrode of the power tube seven is grounded. The multi-stage unit circuit controls the stage number of the whole circuit and adjusts the circuit output by grounding the source electrode of the NMOS tube B through a switch in other unit circuits except the last stage.
In the reference voltage generating circuit, the NMOS transistor a and the NMOS transistor B in each stage of unit circuit operate in the sub-threshold region.
Because the structure is adopted, the NMOS tube A and the NMOS tube B in each stage of unit circuit work in the subthreshold region, so that the current passing through each stage of bias current source P is very small. And the NMOS tube A and the NMOS tube B of each stage are connected in series, so that the matching performance under the condition of subthreshold value can be optimized, and the low-power-consumption circuit is very suitable for being used. After the voltage with the positive temperature coefficient output by the positive temperature coefficient voltage generating circuit is superposed with the voltage with the negative temperature coefficient through the LDO-like circuit, the reference voltage Vref with the low temperature coefficient is output at the output end of the LDO-like circuit. Compared with the prior art, the invention can effectively reduce the system power consumption and has the temperature compensation function.
The invention is further described with reference to the following figures and detailed description.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of the present invention;
FIG. 2 is a schematic diagram of a single-stage structure of a PTC voltage generating circuit according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating characteristics of an output voltage according to an embodiment of the present invention.
Detailed Description
The reference voltage generating circuit with the temperature compensation function comprises a positive temperature coefficient voltage generating circuit 11 and an LDO-like circuit 22 which are sequentially connected. Output from the positive temperature coefficient voltage generating circuit 11After the voltage with the positive temperature coefficient is superimposed with the voltage with the negative temperature coefficient through the LDO-like circuit 22, the reference voltage Vref with the low temperature coefficient is output at the output end of the LDO-like circuit 22. The positive temperature coefficient voltage generating circuit 11 is composed of single-stage or multi-stage unit circuits, and each stage of unit circuit includes a bias current source P using a MOS transistor and two NMOS transistors. The unit circuits of all stages are cascaded in sequence, the grid electrode of an NMOS tube A in each stage of unit circuit is connected with the grid electrode of an NMOS tube B and then is connected to the drain electrode of the NMOS tube A and the drain electrode of a bias current source P, the source electrode of the NMOS tube A is connected with the drain electrode of the NMOS tube B, and the current generated by the bias current source P passes through the NMOS tube A and the NMOS tube B of the stage and then is connected to the source electrode of the NMOS tube A and the drain electrode of the NMOS tube B in the next stage of unit circuit. The source electrode of the NMOS tube B in the last stage unit circuit is grounded, and the connection point of the source electrode of the NMOS tube A and the drain electrode of the NMOS tube B in the first stage unit circuit is used as an output node. The LDO-like circuit 22 includes an operational amplifier including a transistor zero M and an output unit0A transistor M1Transistor two M2Transistor III M3And transistor four M4The output unit comprises a power tube five M5Six M power tubes6Seven M of power tube7. Wherein the transistor is zero M0Is connected to the output node of the positive temperature coefficient voltage generating circuit 11, and the transistor is zero M0Source and transistor-M1Is connected to and connected to the transistor quad M4Drain of (1), transistor two M2Gate of and transistor three M3Is connected to the gate of the transistor tri-M3Drain of (1), transistor two M2And transistor three M3Forming a self-biasing current mirror. Transistor zero M0Drain of and transistor two M2The drain electrode of the power transistor is connected and connected to the six M power transistors of the output unit6The gate of (1), the transistor one1Grid of the power transistor is respectively connected with five M of the power transistor5Is connected to the gate. Power tube five M5Six M of source electrode and power tube6Is connected with the drain of the power tube, and takes the node as a required reference voltage point7Is connected to the transistor quad M4Grid of (1), power tube seven M7The drain electrode of the power tube is connected with five M5The drain electrode of the power tube is seven M7Is grounded. The multi-stage unit circuit controls the stage number of the whole circuit and adjusts the circuit output by grounding the source electrode of the NMOS tube B through the switch in other unit circuits except the last stage. And the NMOS transistor A and the NMOS transistor B in each stage of unit circuit work in a subthreshold region.
Referring to fig. 1, the positive temperature coefficient voltage generating circuit 11 is composed of a MOS transistor MP0MOS transistor MP1MOS transistor MP2MOS transistor MP3MOS transistor MP4And NMOS transistor M operating in subthreshold regionA0NMOS transistor MA1NMOS transistor MA2NMOS transistor MA3NMOS transistor MA4NMOS transistor MB0NMOS transistor MB1NMOS transistor MB2NMOS transistor MB3And NMOS transistor MB4And (4) forming. Each unit circuit is cascaded in sequence, and an NMOS tube MA0Grid and NMOS tube MB0The grid electrodes are connected with the NMOS tubes M respectivelyA0Drain electrode of and MOS tube MP0Drain electrode of (1), NMOS tube MA0Source electrode of and NMOS tube MB0Is connected with the drain electrode of the bias current source MOS transistor MP0The generated current is formed by the NMOS tube MB0The source electrode of the NMOS transistor is connected to an NMOS transistor M in a next stage unit circuitA1Source electrode and NMOS transistor MB1Of the substrate. NMOS tube MA1Grid and NMOS tube MB1The grid electrodes are connected with the NMOS tubes M respectivelyA1Drain electrode of and MOS tube MP1Drain electrode of (1), bias current source MOS tube MP1The generated current is formed by the NMOS tube MB1The source electrode of the NMOS transistor is connected to an NMOS transistor M in a next stage unit circuitA2Source electrode and NMOS transistor MB2Of the substrate. NMOS tube MA2Grid and NMOS tube MB2The grid electrodes are connected with the NMOS tubes M respectivelyA2Drain electrode of and MOS tube MP2Drain electrode of (1), bias current source MOS tube MP2The generated current is formed by the NMOS tube MB2The source electrode of the NMOS transistor is connected to an NMOS transistor M in a next stage unit circuitA3Source electrode and NMOS transistor MB3Of the substrate. NMOS tube MA3Grid and NMOS tube MB3After the grid electrodes are connectedAre respectively connected to the NMOS tubes MA3Drain electrode of and MOS tube MP3Drain electrode of (1), bias current source MOS tube MP3The generated current is formed by the NMOS tube MB3The source electrode of the NMOS transistor is connected to an NMOS transistor M in a next stage unit circuitA4Source electrode and NMOS transistor MB4Of the substrate. NMOS tube MA4Grid and NMOS tube MB4The grid electrodes are connected with the NMOS tubes M respectivelyA4Drain electrode of and MOS tube MP4Drain electrode of (1), bias current source MOS tube MP4The generated current is formed by the NMOS tube MB4Is grounded.
Power tube five M in output unit5Providing a voltage having a negative temperature coefficient, a transistor M1The value of the gate is fixed at V21Left and right power tube seven M7Provides a five-M power tube5A biased tail current source. Transistor M1MOS transistor M with grid connected with output unit diode5Is connected with the grid and the drain, and the power tube is five M5Is also clamped at a voltage V21The value is obtained. Because the power tube has five M5The current between the upper source and the drain is only related to the tail current source, so that the power tube can be considered to be five M5The upper source and drain voltage is a voltage V independent of the loadGS5The voltage is a voltage with a negative temperature coefficient, and the power tube is five M5The source voltage is a voltage V with positive temperature coefficient21Through reasonable setting, V can be orderedGS5And V21Are approximately equal in absolute value. And the output reference voltage VREF has a value VGS5And V21Is said to have obtained a temperature independent reference voltage VREF。
The working principle of the circuit of the invention is explained in detail below.
Consider the operation of the positive temperature coefficient voltage generating circuit 11 of fig. 1.
Referring to FIG. 2, the output V of the single stage circuitOThe situation is. NMOS tube A0MA0And NMOS tube B0MB0EquipartitionIs made in the subthreshold region. Definition MOS transistor P0MP0The generated bias current is I0Then flows through the NMOS transistor A0MA0And NMOS tube B0MB0Current of (I)DSAAnd IDSBAre equal. Define NMOS transistor B0MB0Has a gate-source voltage of VGSBNMOS transistor A0MA0Has a gate-source voltage of VGSANMOS transistor A0MA0Has a width-to-length ratio of SA0NMOS tube B0MB0Has a width-to-length ratio of SB0The current formula of the subthreshold region can be obtained,
（1）
（2）
due to IDSAAnd IDSBAre equal to each other, so
（3）
And VGSA=VGSB-VOTherefore, it is
（4）
Where t denotes absolute temperature, n, k are process dependent, so VO is proportional to temperature.
Consider the case when five stages are cascaded. If the switches are all turned off at this time, and the current sources of all the stages are the same at this time, the current flowing through the lower NMOS tube of each stage is larger than the current flowing through the lower NMOS tube of the preceding stage by I0The current flowing through the upper NMOS tube is always I0. The width-length ratio of the upper NMOS tube and the lower NMOS tube at each stage is SAAnd SBDefined as nkT/q isVTThe method has the advantages of easy obtaining,
（5）
since VT is a voltage with a positive temperature coefficient, V21 is a voltage with a positive temperature coefficient. It is easy to generalize from equation (5) to the more general case that when the ptc voltage generating circuit 11 has n stages, the output voltage is
（6）
From equation (6), a wide range of output voltage adjustments can be easily made by varying the number of stages connected to the ptc voltage generating circuit 11.
Referring to FIG. 1, since M0-M4The power tube is five M5The drain of VREF is fixed at the voltage value of V21, so the voltage to obtain VREF,
（7）
wherein,
VGS5=VTHP+VOV（8）
in the low power consumption state, VOVVery small, and VTHPTypically having a negative temperature coefficient. By appropriate adjustment, V is21Positive temperature coefficient and V ofGS5The negative temperature coefficients are offset, and a reference voltage V with a low temperature coefficient can be obtainedREFAn example result is shown in figure 3. The maximum temperature coefficient is about 46 PPM, and the common requirement is met.
The method can be popularized to more levels of implementation.
The reference voltage source realized by the method avoids the problem of gain mismatching in a low current state when the bipolar transistor is adopted because the bipolar transistor is not required to be biased. On the other hand, the circuit is completely realized by adopting the MOS tube, so that the use of a passive device is avoided, and the area under the low power consumption state is not too large. In conclusion, the invention is very suitable for the use of a low-power consumption system, has more advantages in area compared with the traditional design, and has good performance and economic effect.
Claims (2)
1. A reference voltage generating circuit with a temperature compensation function is characterized by comprising a positive temperature coefficient voltage generating circuit (11) and a similar LDO circuit (22) which are sequentially connected, wherein the voltage with the positive temperature coefficient output by the positive temperature coefficient voltage generating circuit (11) is superposed with the voltage with the negative temperature coefficient through the similar LDO circuit (22), and then a reference voltage (Vref) with a low temperature coefficient is output at the output end of the similar LDO circuit (22); the positive temperature coefficient voltage generating circuit (11) is composed of single-stage or multi-stage unit circuits, and each stage of unit circuit adopts MOS (metal oxide semiconductor) tubesThe bias current source P and two NMOS tubes, each stage of unit circuit is cascaded in sequence, the grid electrode of the NMOS tube A in each stage of unit circuit is connected with the grid electrode of the NMOS tube B and then is connected to the drain electrode of the NMOS tube A and the drain electrode of the bias current source P, the source electrode of the NMOS tube A is connected with the drain electrode of the NMOS tube B, the current generated by the bias current source P passes through the NMOS tube A and the NMOS tube B and then is connected to the source electrode of the NMOS tube A and the drain electrode of the NMOS tube B in the next stage of unit circuit by the source electrode of the NMOS tube B, the source electrode of the NMOS tube B in the last stage of unit circuit is grounded, and the connection point of the source electrode of the NMOS tube A and the drain electrode of the NMOS; the LDO-like circuit (22) comprises an operational amplifier and an output unit, the operational amplifier comprises a transistor zero (M)0) Transistor one (M)1) Transistor two (M)2) Transistor three (M)3) And transistor four (M)4) The output unit comprises a power tube five (M)5) Six power tubes (M)6) And power tube seven (M)7) Wherein the transistor is zero (M)0) Is connected to the output node of the positive temperature coefficient voltage generating circuit (11), and the transistor zero (M)0) Source and transistor one (M)1) Is connected to and connected to transistor four (M)4) Drain of (D), transistor two (M)2) Gate of and transistor three (M)3) Is connected to the gate of transistor three (M)3) Drain of (D), transistor two (M)2) And transistor three (M)3) Forming a self-biased current mirror, transistor zero (M)0) Drain of and transistor two (M)2) Is connected to the drain of the power transistor six (M) of the output unit6) Gate of (D), transistor one (M)1) Grid of the power transistor is respectively connected with a power transistor five (M)5) Is connected with the grid, and a power tube five (M)5) Source electrode and power tube six (M)6) Is connected with the drain of the power transistor seven (M) and takes the node as a required reference voltage point7) Is connected to a transistor four (M)4) Grid of (2), power tube seven (M)7) The drain electrode of the power tube is connected with a fifth (M)5) The drain electrode of (1), the power tube seventh (M)7) Source electrode ofAnd the multistage unit circuit controls the stage number of the whole circuit and adjusts the circuit output by grounding the source electrode of the NMOS tube B through a switch in other unit circuits except the last stage.
2. The reference voltage generation circuit with temperature compensation function according to claim 1, wherein both of the NMOS transistor a and the NMOS transistor B in each stage of unit circuit operate in a subthreshold region.
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| CN107015595A (en) * | 2017-05-03 | 2017-08-04 | 苏州大学 | It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source |
| CN107704008A (en) * | 2017-10-25 | 2018-02-16 | 丹阳恒芯电子有限公司 | A kind of low-power consumption reference circuit |
| CN107894803A (en) * | 2017-10-25 | 2018-04-10 | 丹阳恒芯电子有限公司 | A kind of bias-voltage generating circuit in Internet of Things |
| CN108427471A (en) * | 2018-06-05 | 2018-08-21 | 北京中电华大电子设计有限责任公司 | A kind of zero-temperature coefficient super low-power consumption reference voltage circuit |
| WO2018149166A1 (en) * | 2017-02-16 | 2018-08-23 | 珠海格力电器股份有限公司 | Low temperature drift reference voltage circuit |
| CN112817362A (en) * | 2020-12-31 | 2021-05-18 | 广东大普通信技术有限公司 | Low-temperature coefficient reference current and voltage generating circuit |
| CN113311899A (en) * | 2021-08-02 | 2021-08-27 | 四川蕊源集成电路科技有限公司 | Voltage regulator |
| CN114356017A (en) * | 2021-12-27 | 2022-04-15 | 上海贝岭股份有限公司 | LDO module and voltage generating circuit thereof |
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| CN107704008A (en) * | 2017-10-25 | 2018-02-16 | 丹阳恒芯电子有限公司 | A kind of low-power consumption reference circuit |
| CN107894803A (en) * | 2017-10-25 | 2018-04-10 | 丹阳恒芯电子有限公司 | A kind of bias-voltage generating circuit in Internet of Things |
| CN108427471A (en) * | 2018-06-05 | 2018-08-21 | 北京中电华大电子设计有限责任公司 | A kind of zero-temperature coefficient super low-power consumption reference voltage circuit |
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| CN112817362B (en) * | 2020-12-31 | 2022-05-24 | 广东大普通信技术股份有限公司 | Low-temperature coefficient reference current and voltage generating circuit |
| CN113311899A (en) * | 2021-08-02 | 2021-08-27 | 四川蕊源集成电路科技有限公司 | Voltage regulator |
| CN113311899B (en) * | 2021-08-02 | 2021-11-16 | 四川蕊源集成电路科技有限公司 | Voltage regulator |
| CN114356017A (en) * | 2021-12-27 | 2022-04-15 | 上海贝岭股份有限公司 | LDO module and voltage generating circuit thereof |
| CN114356017B (en) * | 2021-12-27 | 2024-07-19 | 上海贝岭股份有限公司 | LDO module and voltage generation circuit thereof |
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