CN112925375A - Low-power-consumption reference voltage generation circuit with temperature compensation function - Google Patents
Low-power-consumption reference voltage generation circuit with temperature compensation function Download PDFInfo
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- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention provides a low-power-consumption reference voltage generating circuit with a temperature compensation function, which comprises a power-on starting and biasing circuit and a temperature compensation reference voltage generating circuit, wherein the power-on starting and biasing circuit is connected with the temperature compensation reference voltage generating circuit; the power-on starting and biasing circuit is used for providing stable bias voltage; the temperature compensation reference voltage generating circuit comprises a positive temperature coefficient reference voltage generating circuit and a negative temperature coefficient reference voltage generating circuit, wherein the positive temperature coefficient reference voltage generating circuit provides positive temperature coefficient reference voltage through cascaded NMOS tubes working in a sub-threshold region, and outputs zero temperature coefficient reference voltage after the positive temperature coefficient reference voltage and the voltage generated by the negative temperature coefficient reference voltage generating circuit are compensated. According to the technical scheme, the stable and accurate positive temperature coefficient reference voltage is generated through coarse adjustment and fine adjustment, the area of a chip is greatly reduced while low power consumption is guaranteed, and the matching problem of the bipolar transistor during small current does not exist.
Description
Technical Field
The invention relates to a low-power-consumption reference voltage generating circuit in the technical field of integrated circuits, in particular to a reference voltage generating circuit which can be started quickly and has a temperature compensation function.
Background
In the field of integrated circuit power supplies, a reference voltage source is used for providing a voltage reference with a low temperature coefficient for analog circuit modules such as a linear voltage stabilizing circuit and a power supply detection circuit. The scale of integrated circuits is increasing, the application environment is more and more complex, and the requirements on the power consumption, the area overhead, the starting speed and the like of a reference voltage source in the aspect of a system are more and more strict.
The conventional reference voltage generating circuit generally uses bipolar transistors to form a band gap reference source, and utilizes the base-emitter voltage difference generated when bipolar transistors with different sizes conduct the same current as the reference voltage of a positive temperature coefficient to compensate with the base-emitter voltage of the bipolar transistor with a negative temperature coefficient, so as to generate the reference voltage with a zero temperature coefficient as the voltage reference of a power supply system.
In a standard CMOS process, a bipolar transistor is usually a lateral parasitic PNP device, the BETA value of the bipolar transistor is small and changes along with the magnitude of emitter current, so that the matching performance of the device is poor, the temperature coefficient of positive temperature coefficient voltage is greatly influenced by a process angle, and the deviation is more obvious particularly in low-power-consumption design; in addition, the current of the conventional reference voltage generation circuit is determined by the ratio of the voltage difference between the base electrode and the emitter electrode of the two bipolar transistors to the sampling resistor, and for low-power-consumption design, larger resistor area overhead is brought.
In the aspect of starting speed, because a traditional reference voltage generating circuit needs a negative feedback loop generated by an error amplifier to ensure that the differential pressure at two ends of a sampling resistor is the differential pressure of base electrodes and emitter electrodes of two bipolar transistors, the stable speed of the error amplifier limits the starting time of a system for low-power consumption application.
For the above reasons, in order to realize a reference voltage generating circuit with low power consumption, chip start-up time is sacrificed and chip area (cost) overhead is increased. Therefore, how to provide a reference voltage generating circuit capable of ensuring the starting speed and effectively reducing the area cost becomes a problem to be solved in the market at present.
Disclosure of Invention
In view of this, the present invention provides a reference voltage generating circuit with temperature compensation function, and specifically, the present invention provides the following technical solutions:
a low-power consumption reference voltage generating circuit with a temperature compensation function comprises a power-on starting and biasing circuit and a temperature compensation reference voltage generating circuit;
the power-on starting and biasing circuit is used for triggering the biasing circuit to exit a zero current state and establishing a biasing voltage to start entering a zero power consumption state when the system is powered on;
the temperature compensation reference voltage generating circuit comprises a positive temperature coefficient reference voltage generating circuit and a negative temperature coefficient reference voltage generating circuit, wherein the positive temperature coefficient reference voltage generating circuit provides positive temperature coefficient reference voltage through a cascaded NMOS tube working in a sub-threshold region, and outputs zero temperature coefficient reference voltage after the positive temperature coefficient reference voltage and the voltage generated by the negative temperature coefficient reference voltage generating circuit are compensated.
Preferably, the positive temperature coefficient reference voltage generating circuit comprises a temperature coefficient coarse adjusting circuit and a temperature coefficient fine adjusting circuit; the temperature coefficient coarse adjustment circuit and the temperature coefficient fine adjustment circuit are both of a multi-stage cascade structure; the temperature coefficient coarse adjustment circuit has the same circuit structure of each stage, and the temperature coefficient fine adjustment circuit has the same circuit structure of each stage.
Preferably, the single-stage structure of the temperature coefficient coarse tuning circuit is as follows:
the source electrode of the PMOS pipe MPC1 serving as a current source is connected with the power voltage, and the grid electrode of the PMOS pipe MPC1 serving as a current source is connected with the bias voltage VBP; the gate and the drain of the NMOS tube MNC1 are in short circuit and are connected with the drain of the MPC1 and the gate of another NMOS tube MNC1 ', and the source of the MNC1 is connected with the drain of the MNC 1'; the source of MNC 1' is connected to one end of switch SW _ C1; the other end of SW _ C1 is grounded; the source electrode of MNCx' in each stage of circuit is connected with the source electrode of MNCx +1 in the next stage; the source of MNC1 is the output VPR of the positive temperature coefficient reference voltage.
Preferably, the single-stage structure of the temperature coefficient fine adjustment circuit is as follows:
the source of PMOS transistor MPF1 as current source is connected to the power voltage, the grid is connected to the bias voltage VBP, the drain is connected to one end of the switch SW _ F1; the other end of SW _ F [1] is connected to the reference voltage VPR with positive temperature coefficient.
Preferably, the negative temperature coefficient reference voltage generating circuit comprises two PMOS tubes, wherein the source electrode of the first PMOS tube MPO1 is connected with the power supply voltage, the grid electrode of the first PMOS tube MPO1 is connected with the bias voltage VBP, and the drain electrode of the first PMOS tube MPO2 is connected with the source electrode of the second PMOS tube MPO2 and serves as the final reference voltage output end VOUT; the gate of MPO2 is connected to positive temperature coefficient reference voltage VPR, and the drain is connected to VSS.
Preferably, the power-on starting and biasing circuit comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a current sampling transistor first NMOS transistor MN1, a second NMOS transistor MN2, a power-on starting transistor fourth NMOS transistor MN4, a charge releasing transistor third NMOS transistor MN3, a coupling capacitor C0 and a sampling resistor R0, which are used as current mirrors.
Preferably, the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to a power supply voltage, and the gate drain of the second PMOS transistor MP2 is shorted and connected to the gate of the first PMOS transistor MP1, the drain of the second NMOS transistor MP2, and the drain of the fourth NMOS transistor MN4, and serves as a bias voltage output terminal VBP; the grid drain of the first NMOS transistor MN1 is connected with the grid electrode of the second NMOS transistor MN2, the grid electrode of the third NMOS transistor MN3 and the drain electrode of the first PMOS transistor MP1, and the source electrode of the first NMOS transistor MN1 is grounded; the source electrode of the second NMOS transistor MN2 is connected with one end of a sampling resistor R0, and the other end of the sampling resistor R0 is grounded; one end of the coupling capacitor C0 is connected with the power supply voltage, and the other end is connected with the drain electrode of the third NMOS tube MN3 and the grid electrode of the fourth NMOS tube MN 4; the sources of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are grounded.
Preferably, the adjusting value of the temperature coefficient coarse adjusting circuit is realized by changing the stage number of the circuit.
Preferably, the voltage regulation range of the positive temperature coefficient reference voltage generating circuit is as follows:
Wherein M is the stage number of the temperature coefficient fine adjustment circuit, N is the stage number of the temperature coefficient coarse adjustment circuit, N is a process-related constant, k is a Boltzmann constant, T is an absolute temperature, q is a unit charge amount, and A is the ratio of the width-length ratio of MNC1 to the width-length ratio of MNC 1'.
Preferably, the adjustment value of the temperature coefficient fine adjustment circuit is realized by adjusting a branch current of the first stage of the temperature coefficient coarse adjustment circuit.
Preferably, the power-on start-up and bias circuit provides a bias voltage VBP for the positive temperature coefficient reference voltage generating circuit.
Compared with the prior art, the technical scheme of the invention replaces a bipolar transistor with an MOS device working in a sub-threshold region, generates a reference voltage with a positive temperature coefficient, and realizes coarse adjustment and fine adjustment of the temperature coefficient by adjusting the circuit stage number and current; the invention does not adopt the mode of setting branch current by a resistor in the traditional structure, the current in each stage is set by external bias, the chip area is greatly reduced while the low power consumption is ensured, and the matching problem of a bipolar transistor in small current is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a power-on start-up and bias circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a reference voltage generating circuit with temperature compensation function according to an embodiment of the present invention;
FIG. 3 is a graph of the positive temperature coefficient voltage, the negative temperature coefficient voltage, and the compensated zero temperature coefficient reference voltage according to the embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be appreciated by those of skill in the art that the following specific examples or embodiments are a series of presently preferred arrangements of the invention to further explain the principles of the invention, and that such arrangements may be used in conjunction or association with one another, unless it is expressly stated that some or all of the specific examples or embodiments are not in association or association with other examples or embodiments. Meanwhile, the following specific examples or embodiments are only provided as an optimized arrangement mode and are not to be understood as limiting the protection scope of the present invention.
First, terms in the specification are explained as follows:
M-Stage Fine Tuning: an M-level fine adjustment structure;
N-Stage Coarse Tuning: and N-stage coarse tuning structure.
The present invention realizes a low power consumption reference voltage generating circuit with temperature compensation function, and fig. 1 and 2 are an embodiment of the present invention. Embodiments include power-up start-up and bias circuits and temperature compensated reference voltage generation circuits. As shown in fig. 1, the power-on start-up circuit provides excitation for the bias circuit when the system is powered on, triggers the bias circuit to exit from a zero-current state, and after the bias voltage is established, the start-up circuit enters a zero-power mode; with reference to fig. 2, the bias circuit provides a current reference for the temperature compensated reference voltage generation circuit that does not vary with the supply voltage; the temperature compensation reference voltage generation circuit provides positive temperature coefficient reference voltage through cascaded NMOS tubes working in a sub-threshold region, and outputs zero temperature coefficient reference voltage after compensating with grid-source voltage of PMOS tubes with negative temperature coefficients.
The power-on starting and biasing circuit comprises a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1 and a second NMOS tube MN2 which are used as current mirrors, a fourth NMOS tube MN4 of the power-on starting tube, a third NMOS tube MN3 of a charge release tube, a coupling capacitor C0 and a sampling resistor R0. The source electrodes of the first PMOS tube MP1 and the second PMOS tube MP2 are connected with a power supply voltage VCC, and the gate drain of the second PMOS tube MP2 is in short circuit connection with the gate electrode of the first PMOS tube MP1, the drain electrode of the second NMOS tube MP2 and the drain electrode of the fourth NMOS tube MN4 and is used as a bias voltage output end VBP; the grid drain of the first NMOS transistor MN1 is connected with the grid electrode of the second NMOS transistor MN2, the grid electrode of the third NMOS transistor MN3 and the drain electrode of the first PMOS transistor MP1, and the source electrode of the first NMOS transistor MN1 is grounded; the source electrode of the second NMOS transistor MN2 is connected with one end of a sampling resistor R0, and the other end of the sampling resistor R0 is connected with VSS; one end of the coupling capacitor C0 is connected with the power supply voltage, and the other end is connected with the drain electrode of the third NMOS tube MN3 and the grid electrode of the fourth NMOS tube MN 4; the sources of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are grounded.
The reference voltage generating circuit with the temperature compensation function comprises a positive temperature coefficient reference voltage generating circuit and a negative temperature coefficient reference voltage generating circuit, wherein the positive temperature coefficient reference voltage generating circuit comprises a temperature coefficient coarse adjusting circuit and a temperature coefficient fine adjusting circuit. The temperature coefficient Coarse Tuning circuit comprises an N-Stage structure, i.e., an N-Stage Coarse Tuning structure (see N-Stage Coarse Tuning in fig. 2), each Stage having the same structure, taking the first Stage as an example, a PMOS transistor MPC1 serving as a current source having a source connected to a power supply voltage and a gate connected to a bias voltage VBP; the gate and the drain of the NMOS tube MNC1 are shorted, and are connected with the drain of the MPC1 and the gate of the MNC1 ', and the source of the MNC1 is connected with the drain of the MNC 1'; the source of MNC 1' is connected to one end of switch SW _ C1; the other end of SW _ C1 is grounded; the source electrode of MNCx' in each stage of circuit is connected with the source electrode of MNCx +1 in the next stage; the source of MNC1 is the output VPR of the positive temperature coefficient reference voltage. The temperature coefficient Fine Tuning circuit comprises M-level structure (M-Stage Fine Tuning in FIG. 2), each level of which is the same, taking the first level as an example, the source of PMOS transistor MPF1 as a current source is connected with the power voltage, the gate is connected with the bias voltage VBP, and the drain is connected with one end of the switch SW _ F1; the other terminal of SW _ F [1] is connected to VPR. The negative temperature coefficient reference voltage generating circuit comprises two PMOS tubes, wherein the source electrode of a first PMOS tube MPO1 is connected with power voltage, the grid electrode of the first PMOS tube MPO1 is connected with bias voltage VBP, and the drain electrode of the first PMOS tube MPO1 is connected with the source electrode of a second PMOS tube MPO2 to be used as a final reference voltage output end VOUT; the gate of MPO2 is connected to positive temperature coefficient reference voltage VPR, and the drain is connected to ground.
In this embodiment, in the coarse tuning circuit and the fine tuning circuit, the current in each stage is set by an external stable bias voltage, so that the chip area is greatly reduced while low power consumption is ensured, and the matching problem of the bipolar transistor in the case of small current does not exist.
The working principle of the circuit of the invention is explained in detail below.
When VCC is powered on, the lower plate voltage of the coupling capacitor C0 rises immediately, MN4 is turned on, the bias circuit exits the zero current state by pulling down the VBP voltage, and the bias current can be obtained by the following formula (1). After the bias state is normally established, the charge of the lower board of the capacitor C0 is discharged through the MN3, and the MN4 is cut off.
In the formula (1), μnIs the carrier mobility of NMOS tube, CoxThe gate oxide capacitance of the unit area of the MOS transistor is W, the channel width of the MOS transistor is L, the channel length of the MOS transistor is L, and the ratio of the width-length ratio of MN2 to the width-length ratio of MN1 is K.
From MPC1, MNC1, MNC 1' and SW _ C [1]]The single-stage positive temperature coefficient voltage generating circuit has the following working principle, SW _ C1]Closed with branch current of IrefWhen the MNC1 and the MNC1 'both work in a subthreshold region, the width-length ratio of the MNC1 is larger than that of the MNC 1', and the ratio of the width-length ratio is set to be A, then the following can be obtained:
VGS,MNC1＝VGS,MNC1'-VVPR (4)
in the above formulas (2), (3) and (4), I0Is a parameter related to the MOS tube process and the width-length ratio, W and L are the channel width and length of the MOS tube, q is unit charge, VGSIs the gate-source voltage of the corresponding MOS transistor, n is a constant related to the process, k is the Boltzmann constant, T is the absolute temperature, VVPRIs the voltage of the VPR node.
In view of the fact that the MNC1 and MNC 1' have equal currents, the formula (2), (3) and (4) are IrefIt is possible to obtain:
in the formula (5), n is a process-related constant, k is a boltzmann constant, T is an absolute temperature, q is a unit charge amount, and a is a ratio of a width-to-length ratio of MNC1 to a width-to-length ratio of MNC 1'.
The coarse adjustment circuit is realized by increasing the stage number, the fine adjustment circuit is realized by increasing the current of the MNC 1', and the derivation can be realized by adding all the stage numbers into the circuit to obtain
Equations (5) and (6) are the adjustment ranges of the positive temperature coefficient voltage. Wherein M is the stage number of the temperature coefficient fine adjusting circuit, and N is the stage number of the temperature coefficient coarse adjusting circuit.
And (3) compensating the VPR voltage with the gate-source voltage of the PMOS tube MPO2 with the negative temperature coefficient to obtain the output reference voltage VOUT with the temperature coefficient close to zero.
When the circuit is used specifically, in the power supply electrifying process, the grid electrode of the MN4 is coupled to a high level through the C0, the MN4 is conducted to pull down the VBP to VSS, the bias circuit exits from a zero current state, the VBP is gradually established, the MN3 is conducted to discharge the C0 lower-level board to VSS, and the VBP is not influenced by the MN4 to be pulled down and is gradually established to a steady-state value.
In the VBP stable establishment process, the current mirror tubes MPC1 to MPCn, MPF1 to MPFm and MPO1 in the reference voltage generating circuit gradually reach the working state of the stable current source, and the reference voltage with the temperature coefficient close to zero is generated by the compensation of the positive temperature coefficient reference voltage generating circuit and the negative temperature coefficient reference voltage generating circuit.
FIG. 3 is a graph showing positive temperature coefficient voltage, negative temperature coefficient voltage, and zero temperature coefficient voltage waveform after compensation, and it can be seen that, after temperature compensation, the temperature coefficient of the output voltage is between-60 PPM and 20PPM within the temperature range of-40 ℃ to 85 ℃, which meets the requirement of most power supply systems for the accuracy of the reference voltage.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A low-power-consumption reference voltage generating circuit with a temperature compensation function is characterized by comprising a power-on starting and biasing circuit and a temperature compensation reference voltage generating circuit;
the power-on starting and biasing circuit is used for triggering the biasing circuit to exit a zero current state and establishing a biasing voltage when the system is powered on;
the temperature compensation reference voltage generating circuit comprises a positive temperature coefficient reference voltage generating circuit and a negative temperature coefficient reference voltage generating circuit, wherein the positive temperature coefficient reference voltage generating circuit provides positive temperature coefficient reference voltage through a cascaded NMOS tube working in a sub-threshold region, and outputs zero temperature coefficient reference voltage after the positive temperature coefficient reference voltage and the voltage generated by the negative temperature coefficient reference voltage generating circuit are compensated.
2. The low power consumption reference voltage generating circuit according to claim 1, wherein the positive temperature coefficient reference voltage generating circuit comprises a temperature coefficient coarse adjusting circuit, a temperature coefficient fine adjusting circuit; the temperature coefficient coarse adjustment circuit and the temperature coefficient fine adjustment circuit are both of a multi-stage cascade structure; the temperature coefficient coarse adjustment circuit has the same circuit structure of each stage, and the temperature coefficient fine adjustment circuit has the same circuit structure of each stage.
3. The low power consumption reference voltage generation circuit of claim 2, wherein the single stage structure of the coarse temperature coefficient adjustment circuit is:
the source electrode of the PMOS pipe MPC1 serving as a current source is connected with the power voltage, and the grid electrode of the PMOS pipe MPC1 serving as a current source is connected with the bias voltage VBP; the gate and the drain of the NMOS tube MNC1 are in short circuit and are connected with the drain of the MPC1 and the gate of another NMOS tube MNC1 ', and the source of the MNC1 is connected with the drain of the MNC 1'; the source of MNC 1' is connected to one end of switch SW _ C [1 ]; the other end of SW _ C1 is grounded; the source electrode of MNCx' in each stage of circuit is connected with the source electrode of MNCx +1 in the next stage; the source of MNC1 is the output VPR of the positive temperature coefficient reference voltage.
4. The low power consumption reference voltage generating circuit according to claim 2, wherein the single-stage structure of the temperature coefficient fine-tuning circuit is:
the source of PMOS transistor MPF1 as current source is connected to the power voltage, the grid is connected to the bias voltage VBP, the drain is connected to one end of switch SW _ F1; the other end of SW _ F [1] is connected to the reference voltage VPR with positive temperature coefficient.
5. The low power consumption reference voltage generation circuit of claim 1, wherein the negative temperature coefficient reference voltage generation circuit comprises two PMOS transistors, the first PMOS transistor MPO1 has its source connected to the power voltage, its gate connected to the bias voltage VBP, and its drain connected to the source of the second PMOS transistor MPO2, as the final reference voltage output terminal VOUT; the gate of MPO2 is connected to positive temperature coefficient reference voltage VPR, and the drain is connected to VSS.
6. The low power consumption reference voltage generation circuit of claim 1, wherein the power-on start-up and bias circuit comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a current sampling transistor first NMOS transistor MN1, a second NMOS transistor MN2, a power-on start-up transistor fourth NMOS transistor MN4, a charge release transistor third NMOS transistor MN3, a coupling capacitor C0 and a sampling resistor R0;
the source electrodes of the first PMOS tube MP1 and the second PMOS tube MP2 are connected with power voltage, and the gate drain of the second PMOS tube MP2 is in short circuit connection with the gate electrode of the first PMOS tube MP1, the drain electrode of the second NMOS tube MP2 and the drain electrode of the fourth NMOS tube MN4 to serve as a bias voltage output end VBP; the grid drain of the first NMOS transistor MN1 is connected with the grid electrode of the second NMOS transistor MN2, the grid electrode of the third NMOS transistor MN3 and the drain electrode of the first PMOS transistor MP1, and the source electrode of the first NMOS transistor MN1 is grounded; the source electrode of the second NMOS transistor MN2 is connected with one end of a sampling resistor R0, and the other end of the sampling resistor R0 is grounded; one end of the coupling capacitor C0 is connected with the power supply voltage, and the other end is connected with the drain electrode of the third NMOS tube MN3 and the grid electrode of the fourth NMOS tube MN 4; the sources of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are grounded.
7. The low power consumption reference voltage generation circuit of claim 2, wherein the adjustment value of the temperature coefficient coarse adjustment circuit is realized by changing the number of stages of the circuit.
8. The low power consumption reference voltage generating circuit according to claim 2, wherein the voltage regulating range of the positive temperature coefficient reference voltage generating circuit is:
Wherein M is the stage number of the temperature coefficient fine adjustment circuit, N is the stage number of the temperature coefficient coarse adjustment circuit, N is a process-related constant, k is a Boltzmann constant, T is an absolute temperature, q is a unit charge amount, and A is the ratio of the width-length ratio of MNC1 to the width-length ratio of MNC 1'.
9. The low power consumption reference voltage generating circuit of claim 2, wherein the adjustment value of the temperature coefficient fine tuning circuit is achieved by adjusting a branch current of the first stage of the temperature coefficient coarse tuning circuit.
10. The low power consumption reference voltage generating circuit of claim 1, wherein the power-on start-up and bias circuit provides a bias voltage VBP for a positive temperature coefficient reference voltage generating circuit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117170453A (en) * | 2023-08-30 | 2023-12-05 | 北京中电华大电子设计有限责任公司 | Reference voltage generating circuit and vehicle-mounted chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117170453A (en) * | 2023-08-30 | 2023-12-05 | 北京中电华大电子设计有限责任公司 | Reference voltage generating circuit and vehicle-mounted chip |
| CN117170453B (en) * | 2023-08-30 | 2024-06-11 | 北京中电华大电子设计有限责任公司 | Reference voltage generating circuit and vehicle-mounted chip |
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