JP2007219856A - Constant voltage power source circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a phase margin even in an area with a small difference between a reference voltage and an output voltage in a constant voltage power source circuit. <P>SOLUTION: A series regulator 1 is provided with a resistor division part 3, a differential amplification part 4 and an output stage 5, the reference voltage Vref1 generated from a reference voltage generation circuit 2 is inputted, and the output voltage Vout is outputted from the output stage 5. The resistor division part 3 comprises cascade-connected resistor R1 and resistor R2, the reference voltage Vref1 inputted to the resistor division part 3 is resistor-divided by the resistor R1 and the resistor R2, and a reference voltage Vref2 obtained by dropping the reference voltage Vref1 is outputted from a part between the resistor R1 and the resistor R2. In the differential amplification part 4, the reference voltage Vref2 is inputted to a (-) side of an input side, a resistor division voltage Va as a feedback voltage outputted from the output stage 5 is inputted to a (+) side of the input side, and a differentially amplified signal is outputted. The output stage 5 comprises an output transistor PT1 that is a Pch MOS transistor, a resistor R3, and a resistor R4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a constant voltage power supply circuit to which a differential input signal is input.

  In recent years, constant voltage power supply circuits such as linear regulators, LDO (Low Drop Out) regulators, and series regulators are mounted on various devices (see, for example, Patent Document 1). In applications such as mobile communication devices, improvement in ripple rejection characteristics and reduction in noise characteristics are required, and a three-stage amplification configuration of the feedback circuit becomes the mainstream in order to cope with an increase in the total loop gain of the feedback circuit. ing. Compared with the two-stage amplification configuration, the three-stage amplification configuration increases the number of pole frequencies and makes phase correction difficult. In addition, with high integration and low power consumption of LSIs mounted on mobile communication devices and the like, constant voltage power supply circuits are required to have low saturation and low output voltage.

However, as the input voltage as the power supply voltage of the constant voltage power supply circuit decreases, the phase margin decreases and the phase correction becomes more difficult when the output voltage of the constant voltage power supply circuit approaches the input reference voltage. There is a point.
US Pat. No. 6,522,112 (Page 2, FIG. 1)

  An object of the present invention is to provide a constant voltage power supply circuit capable of increasing a phase margin even in a region where a difference between a reference voltage and an output voltage is small.

  In order to achieve the above object, a constant voltage power supply circuit according to one embodiment of the present invention receives a first reference voltage output from a reference voltage generation circuit, and outputs a second voltage lower than the first reference voltage. The reference voltage step-down means for generating the reference voltage, and the first and the second are provided between the high-potential side power source and the low-potential side power source, input the second reference voltage to the input side, and form a differential pair And a differential amplifying unit composed of one or a plurality of stages having a differential input stage that performs differential amplifying operation, and provided on the high-potential-side power supply side and output from the differential amplifying unit. An output transistor that performs an amplification operation by inputting a signal, and a plurality of output transistors connected in cascade between the output transistor and the low-potential-side power supply, and output a resistance-divided voltage as a feedback voltage to the input side of the differential input stage A resistor, and the output transistor and the front Characterized by comprising an output stage for outputting an output voltage from between the plurality of resistors.

  Furthermore, in order to achieve the above object, a constant voltage power supply circuit according to another aspect of the present invention receives a first reference voltage output from a reference voltage generation circuit, and has a lower voltage than the first reference voltage. A reference voltage step-down means for generating a second reference voltage; and a first and a second pair that are provided between a high-potential-side power supply and a low-potential-side power supply, input the second reference voltage to the input side, and form a differential pair A second transistor is provided, and is provided between a differential input stage that performs differential amplification operation, and between the high-potential side power supply and the low-potential side power supply, and receives a signal output from the differential input stage. An amplifying stage that performs an amplifying operation, an output transistor that is provided on the high-potential-side power supply side and that amplifies by receiving a signal output from the amplifying stage, and a cascade connection between the output transistor and the low-potential-side power supply The voltage divided by the resistance is input to the input side of the differential input stage. And a plurality of resistors for outputting a feedback voltage, characterized by comprising an output stage for outputting an output voltage from between said plurality of resistors and the output transistor.

  According to the present invention, it is possible to provide a constant voltage power supply circuit capable of increasing the phase margin even in a region where the difference between the reference voltage and the output voltage is small.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a constant voltage power supply circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a series regulator as a constant voltage power supply circuit. In this embodiment, a Pch MOS transistor is used as an output transistor in the output section of the series regulator.

  As shown in FIG. 1, the series regulator 1 is provided with a resistance dividing unit 3, a differential amplifying unit 4, and an output stage 5. The reference voltage Vref1 generated from the reference voltage generating circuit 2 is input, and the output stage 5 outputs an output voltage Vout.

  The reference voltage generation circuit 2 is provided between the high potential side power source Vcc1 and the low potential side power source Vss, and is composed of, for example, a BGR (Band Gap Reference) circuit, which is stable with little voltage fluctuation and little temperature change. For example, a reference voltage Vref1 of 1.2V is generated. Here, during normal use of the series regulator 1, the low-potential-side power supply Vss is generally set to the same potential as the ground potential.

  The resistor dividing unit 3 is arranged between the reference voltage generating circuit 2 and the differential amplifying unit 4 and includes a resistor R1 and a resistor R2 connected in cascade. One end of the resistor R1 is connected to the output side that outputs the reference voltage Vref1 of the reference voltage generating circuit 2, and the other end is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the low potential side power source Vss. The reference voltage Vref1 input to the resistor dividing unit 3 is divided by resistors R1 and R2, and the reference voltage Vref1 is stepped down from between the resistors R1 and R2, for example, 0.6V reference voltage Vref2 (in this case) , Resistor R1 and resistor R2 have the same resistance value). Here, the resistance dividing unit 3 is configured by the resistor R1 and the resistor R2, but may be appropriately configured by a plurality of resistors of three or more.

  The differential amplifying unit 4 is provided between a high potential side power source Vcc2 (Vin) as an input power source and a low potential side power source Vss, and is disposed between the resistance dividing unit 3 and the output stage 5, and (− The reference voltage Vref2 is input to the) side, the resistance division voltage Va as the feedback voltage output from the output stage 5 is input to the (+) side of the input side, and a differentially amplified signal is output. Here, the differential amplifier 4 includes a single stage or a plurality of stages including a differential input stage that performs differential amplification operation.

  The output stage 5 includes an output transistor PT1, which is a Pch MOS transistor, a resistor R3, and a resistor R4. The source of the output transistor PT1 is connected to the high potential side power supply Vcc2 (Vin), and a signal output from the differential amplifier 4 is input to the gate to perform an amplification operation. The resistor R3 has one end connected to the drain of the output transistor PT1, and the other end connected to one end of the resistor R4. The other end of the resistor R4 is connected to the low potential side power source Vss. A resistance division voltage Va is input as a feedback voltage from between the resistors R3 and R4 to the (+) side on the input side of the differential amplifier 4. An output voltage Vout is output from between the drain of the output transistor PT1 and the resistor R3. Here, a stabilizing capacitor Cout for stabilizing the output voltage Vout is provided between the output transistor PT1 and the resistor R3 and between the low-potential-side power supply Vss. Here, the resistance division voltage Va as the feedback voltage is generated using the resistors R3 and R4, but may be configured by a plurality of three or more resistors as appropriate.

The MOS transistor is also called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Here, a MOS transistor in which the gate insulating film is formed of a silicon oxide film is used. However, a SiNxOy film obtained by thermally nitriding a silicon oxide film, a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film laminated film, or a high dielectric A MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a body film (High-K gate insulating film) or the like becomes a gate insulating film may be used.

Here, in general, the relationship between the reference voltage Vref, the output voltage Vout, and the resistors R3 and R4 that generate the resistance divided voltage Va as a feedback voltage is as follows:
R4 / (R3 + R4) ≒ Vref / Vout ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (1)
The output voltage Vout is adjusted by the resistance ratio of the resistors R3 and R4.

  Next, gain and phase characteristics with respect to the frequency of the series regulator will be described with reference to the drawings. FIG. 2 is a diagram showing the relationship between the gain and phase with respect to the frequency of the series regulator of the present embodiment, the solid line (a) in the diagram shows the relationship between the frequency and the gain of the present embodiment, and the broken line (b) in the diagram is this diagram. 3 shows the relationship between the frequency and phase of the embodiment, FIG. 3 shows the relationship between the gain and phase with respect to the frequency of the conventional series regulator, and the solid line (a) in the drawing shows the relationship between the conventional frequency and gain. The broken line (b) indicates the relationship between the conventional frequency and phase. Here, the differential amplifying unit has a two-stage configuration of a differential input stage and an amplifying stage that amplifies and inputs signals from the differential input stage. Further, in the conventional series regulator, the reference voltage output from the reference voltage generation circuit is directly input without providing a resistor divider.

  As shown in FIG. 2, in this embodiment, when the high-potential-side power supply Vcc2 (Vin) voltage specification as the input power supply is reduced and the output voltage Vout specification is reduced from 3 V to 1.5 V, for example, the gain is 0 dB. The phase margin at this frequency is 20 °. This is because the reference voltage Vref1 (1.2V) is stepped down from the reference voltage Vref2 (0.6V) by the resistor divider 3, and the difference between the reference voltage Vref2 and the output voltage Vout can be increased. Even if the regulator 1 has a three-stage configuration, a phase margin can be ensured as in the case where the output voltage Vout is 3V specification. Here, the gain margin when the phase is −180 ° is 30 dB. Note that the illustration and description of the characteristics when the output voltage Vout is 3 V are omitted.

  On the other hand, as shown in FIG. 3, in the conventional case (when the resistance divider 3 is not provided), the high-potential-side power supply Vcc2 (Vin) voltage specification as the input power supply is lowered, and the output voltage Vout specification is, for example, When the voltage drops from 3 V to 1.5 V, the phase margin at a frequency of 0 dB gain is 2 °. This is because the difference between the reference voltage Vref1 (1.2V) and the output voltage Vout (1.5V) is small because the reference voltage Vref1 (1.2V) is used, and the output voltage Vout is 3V specification. When the series regulator 1 has a three-stage configuration, for example, it is difficult to ensure the phase margin. Here, the gain margin when the phase is −180 ° is 20 dB.

  As described above, in the constant voltage power supply circuit of this embodiment, the resistance divider 3, the differential amplifier 4, and the output stage 5 are provided. The reference voltage Vref1 input to the resistor divider 3 is divided by resistors R1 and R2, and a reference voltage Vref2 obtained by stepping down the reference voltage Vref1 from between the resistors R1 and R2 is output. The differential amplifying unit 4 receives the reference voltage Vref2 on the (−) side of the input side, and inputs and amplifies the resistance division voltage Va as a feedback voltage output from the output stage 5 on the (+) side of the input side. Output a signal. The output stage 5 includes an output transistor PT1, which is a Pch MOS transistor, a resistor R3, and a resistor R4. The output transistor PT1 performs an amplification operation by inputting a signal output from the differential amplifier 4 to the gate. A resistance division voltage Va is input as a feedback voltage from between the resistors R3 and R4 to the (+) side on the input side of the differential amplifier 4.

  For this reason, even when the voltage specification of the high potential side power supply Vcc2 (Vin) as the input power supply is lowered and the specification of the output voltage Vout is lowered, the reference voltage Vref1 is stepped down to the reference voltage Vref2 by the resistor divider 3 and used. Therefore, the difference between the reference voltage Vref2 and the output voltage Vout can be increased, and a phase margin can be secured.

  In this embodiment, the series regulator in which the resistance divider is provided on the input side to reduce the reference voltage has been described. However, the present invention can also be applied to a linear regulator, an LDO regulator, or the like.

  Next, a constant voltage power supply circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing a series regulator as a constant voltage power supply circuit. In this embodiment, a three-stage amplification series regulator is formed of MOS transistors.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 4, the series regulator 1 a is provided with a level shift circuit 6, a differential input stage 11, an amplification stage 12, and an output stage 13, and receives a reference voltage Vref 1 generated from the reference voltage generation circuit 2. The output voltage Vout is output from the output stage 13.

  The level shift circuit 6 is disposed between the reference voltage generation circuit 2 and the differential input stage 11, and is provided between the output side of the reference voltage generation circuit 2 that outputs the reference voltage Vref1 and the low potential side power supply Vss. For example, a reference voltage Vref2 of V = 0.6V is generated by stepping down the voltage Vref1.

  The differential input stage 11 is disposed between the level shift circuit 6 and the amplifier stage 12, and is provided between a high potential side power source Vcc2 (Vin) and a low potential side power source Vss as input power sources, and Pch MOS transistors MP1, It comprises a Pch MOS transistor MP2 and Nch MOS transistors MN1 to MN3.

  The Pch MOS transistor MP1 has a source connected to the high potential side power supply Vcc2 (Vin), a gate connected to the drain, and a drain connected to the drain of the Nch MOS transistor MN1. The Pch MOS transistor MP2 has a source connected to the high potential side power supply Vcc2 (Vin), a gate connected to the gate of the Pch MOS transistor MP1, and a drain connected to the drain of the Nch MOS transistor MN2. The Pch MOS transistors MP1 and MP2 constitute a current mirror circuit, and supply a constant current to the Nch MOS transistors MN1 and MN2 as a load.

  The Nch MOS transistor MN1 inputs the reference voltage Vref2 to the gate (input as the (−) side on the input side of the differential input stage 11). The Nch MOS transistor MN2 inputs the voltage obtained by dividing the resistance of the output stage 13 to the gate as a feedback voltage (inputs as the (+) side on the input side of the differential input stage 11). A differentially amplified signal is output from between the drain of the Pch MOS transistor MP2 and the drain of the Nch MOS transistor MN2.

  The Nch MOS transistor MN3 has a drain connected to the sources of the Nch MOS transistors MN1 and MN2, a source connected to the low potential power source Vss, and a bias voltage Vb input to the gate. The bias voltage Vb is set to a predetermined voltage so that the Pch MOS transistor MP1, the Pch MOS transistor MP2, the Nch MOS transistor MN1, the Nch MOS transistor MN2, and the Nch MOS transistor MN3 operate in the saturation region.

  The amplification stage 12 is disposed between the differential input stage 11 and the output stage 13, and is provided between the high potential side power supply Vcc2 (Vin) and the low potential side power supply Vss, and is connected to the Pch MOS transistor MP3 and the Nch MOS transistor MN4. It is configured.

  The source of the Pch MOS transistor MP3 is connected to the high potential side power supply Vcc2 (Vin), and the signal output from the differential input stage 11 is input to the gate to perform an amplification operation. The Nch MOS transistor MN4 has a drain connected to the drain of the Pch MOS transistor MP3, a source connected to the low potential power source Vss, and a bias voltage Vb input to the gate. Here, the bias voltage Vb is set to a predetermined voltage so that the Pch MOS transistor MP3 and the Nch MOS transistor MN4 operate in the saturation region.

  The output stage 13 is provided between the high potential side power supply Vcc2 (Vin) and the low potential side power supply Vss, and includes a Pch MOS transistor MP4, a capacitor C1, and resistors R11 to R13.

  The source of the Pch MOS transistor MP4 is connected to the high potential side power supply Vcc2 (Vin), and the signal output from the amplification stage 12 is input to the gate to perform an amplification operation. The resistor R11 has one end connected to the drain of the Pch MOS transistor MP4 and the other end connected to one end of the resistor R12. The other end of the resistor R12 is connected to the low potential side power source Vss. One end of the capacitor C1 is connected to the drain of the Pch MOS transistor MP4, and the other end is connected to one end of the resistor R13. The other end of the resistor R13 is connected between the resistor R11 and the resistor R12.

  An output voltage VouT is output from between the drain of the Pch MOS transistor MP4 and the resistor R11. A voltage obtained by resistance division between the capacitor C1 and the resistor R13 is input to the gate of the Nch MOS transistor MN2 of the differential input stage 11 as a feedback voltage. Here, the capacitor C1 and the resistor R13 are provided in order to improve the phase margin in the high frequency region of the series regulator 1a. For example, the resistor R13 is a circuit unit including resistors R11 to R13 and the capacitor C1. It serves to separate the frequencies of zero (Zx) and pole (Px).

Next, the relationship between the voltage V1 between the capacitor C1 and the resistor R13 shown in FIG. 1, the voltage V2 between the resistor R11 and the resistor R12, and the output voltage Vout will be described.
The voltage V2 between the resistor R11 and the resistor R12 is
R12 / (R11 + R12) ≒ Vref2 / Vout ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (2)
Is represented by
V2 ≒ Vref2 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (3)
It becomes.

The gain AV of V1 / Vout is
AV = R12 / (R11 + R12) ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (4)
Therefore, the gain AV is the output division resistance ratio. The zero frequency fZ1 and pole frequency fP1 generated by the transfer function of V1 / Vout is the capacitance between the V1 and the low-potential power source Vss is set sufficiently smaller than the _{C 1} is a capacitance of the capacitor C1, Respectively,
fZ1 = R12 / {2πC ₁ (R11 · R12 + R12 · R13 + R11 · R13)} ... (5)
fP1 = (R11 + R12) / {2πC ₁ (R11 · R12 + R12 · R13 + R11 · R13)} ··· Equation (6)
From the equations (5) and (6),
fZ1 / fP1 = R12 / (R11 + R12) ........... Formula (7)
The relationship between the zero frequency fZ1 and the pole frequency fP1 is
fZ1 <fP1 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Equation (8)
It can be seen that it is. In addition, in the case of the low output voltage Vout, it can be seen from the equation (7) that fZ1 / fP1 approaches 1.

  Next, phase characteristics with respect to frequency of the series regulator will be described with reference to the drawings. FIG. 5 is a diagram showing the V1 / Vout phase characteristics with respect to the frequency of the series regulator, the solid line (a) in the figure shows the characteristics of this example, and the broken line (b) in the figure shows the conventional characteristics. Here, in the conventional series regulator, the reference voltage output from the reference voltage generation circuit is directly input without providing the level shift circuit.

  As shown in FIG. 5, in the conventional case (when the level shift circuit 6 is not provided), the high-potential-side power supply Vcc2 (Vin) voltage specification as the input power supply is lowered, and the specification of the output voltage Vout is, for example, from 3V When it drops to 1.5V, the phase recovery is only 7.8 °. This is because the capacitor C1 and the resistor R13 are provided to improve the phase margin, but the reference voltage Vref1 (1.2V) is used, so the reference voltage Vref1 (1.2V) and the output voltage Vout ( 1.5V) is small, and it can be seen that the effect of phase correction is small.

  On the other hand, in this embodiment, even when the high-potential-side power supply Vcc2 (Vin) voltage specification as the input power supply decreases and the output voltage Vout specification decreases from 3 V to 1.5 V, for example, the phase recovery is 26.5. There is ゜. This is because the reference voltage Vref1 (1.2V) is stepped down from the reference voltage Vref2 (0.6V) by the level shift circuit 6 so that the difference between the reference voltage Vref2 and the output voltage Vout can be increased. It can be seen that even if the regulator 1 has a three-stage configuration, the effect of phase correction can be increased as in the case where the output voltage Vout is 3 V specification.

  As described above, in the constant voltage power supply circuit of this embodiment, the level shift circuit 6, the differential input stage 11, the amplification stage 12, and the output stage 13 are provided. The reference voltage Vref1 input to the level shift circuit 6 is stepped down and the reference voltage Vref2 is output. The differential input stage 11 receives a reference voltage Vref2 on the (−) side of the input side, and inputs a resistance division voltage as a feedback voltage output from the output stage 13 on the (+) side of the input side, thereby performing differential amplification. Output the signal. The amplification stage 12 receives the signal output from the differential input stage 11 and outputs the amplified signal. The output stage 13 includes a Pch MOS transistor MP4, a capacitor C1, and resistors R11 to R13. The Pch MOS transistor MP4 receives the signal output from the amplification stage 12 and outputs the amplified signal.

  For this reason, even when the voltage specification of the high potential side power supply Vcc2 (Vin) as the input power supply is lowered and the specification of the output voltage Vout is lowered, the reference voltage Vref1 is stepped down to the reference voltage Vref2 by the level shift circuit 6 and used. Therefore, the difference between the reference voltage Vref2 and the output voltage Vout can be increased, and a phase margin can be ensured as in the first embodiment. Further, since the reference voltage Vref1 is stepped down by the level shift circuit 6, the phase recovery can be made larger than when the capacitor C1 and the resistor R13 are provided and the level shift circuit 6 is not provided.

  In this embodiment, the series regulator has a three-stage amplification configuration, but may have a two-stage amplification configuration or a four-stage amplification configuration. Further, although the phase correcting capacitor C1 and the resistor R13 are provided in the output stage 13, they may be provided in the amplification stage 12 or in the amplification stage 12 only.

  Next, a constant voltage power supply circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing a series regulator as a constant voltage power supply circuit. In this embodiment, the series regulator is composed of bipolar transistors.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the series regulator 1b is provided with a resistance divider 3, a differential amplifier 4a, and an output stage 5a. The series regulator 1b receives the reference voltage Vref1 generated from the reference voltage generation circuit 2, and outputs the output stage. The output voltage Vout is output from 5a.

  The differential amplifying unit 4a is composed of a bipolar transistor (not shown), and is provided between a high potential side power source Vcc2 (Vin) as an input power source and a low potential side power source Vss, and between the resistance dividing unit 3 and the output stage 5a. The reference voltage Vref2 is input to the (−) side on the input side, the resistance divided voltage Va as the feedback voltage output from the output stage 5a is input to the (+) side on the input side, and the amplified signal is input Output. Here, the differential amplifying unit 4a includes one or a plurality of stages including a differential input stage that performs a differential amplification operation.

  The output stage 5a includes an output transistor BPT1, which is a PNP transistor, a resistor R3, and a resistor r4. The output transistor BPT1 has an emitter connected to the high potential side power supply Vcc2 (Vin), and amplifies the signal by inputting the signal output from the differential amplifier 4a to the base. The resistor R3 has one end connected to the collector of the output transistor BPT1 and the other end connected to one end of the resistor R4. The other end of the resistor R4 is connected to the low potential side power source Vss. An output voltage Vout is output from between the collector of the output transistor BPT1 and the resistor R3.

  Here, the differential amplifying unit 4a and the output stage 5a of the series regulator 1b are composed of bipolar transistors, and the bipolar transistor can suppress the characteristic variation of the transistor more than the MOS transistor. The circuit area can be reduced.

  As described above, the constant voltage power supply circuit according to the present embodiment includes the resistance divider 3, the differential amplifier 4a, and the output stage 5a. The reference voltage Vref1 input to the resistor divider 3 is divided by resistors R1 and R2, and a reference voltage Vref2 obtained by stepping down the reference voltage Vref1 from between the resistors R1 and R2 is output. The differential amplifying unit 4a is composed of a bipolar transistor, and a reference voltage Vref2 is input to the (−) side on the input side, and a resistance division voltage as a feedback voltage output from the output stage 5a to the (+) side on the input side. Va is input and an amplified signal is output. The output stage 5 includes an output transistor BPT1, which is a PNP transistor, a resistor R3, and a resistor R4. The output transistor BPT1 performs an amplification operation by inputting the signal output from the differential amplifier 4a to the base. A resistance division voltage Va is input as a feedback voltage from between the resistors R3 and R4 to the (+) side on the input side of the differential amplifier 4.

  For this reason, even when the voltage specification of the high potential side power supply Vcc2 (Vin) as the input power supply is lowered and the specification of the output voltage Vout is lowered, the reference voltage Vref1 is stepped down to the reference voltage Vref2 by the resistor divider 3 and used. Therefore, the difference between the reference voltage Vref2 and the output voltage Vout can be increased, and a phase margin can be ensured as in the first embodiment.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the second embodiment, the series regulator as a constant voltage power supply circuit has a CMOS configuration, and in the third embodiment, the series regulator as a constant voltage power supply circuit is configured by a bipolar transistor. The series regulator may have a BiCMOS configuration or a junction transistor (J-FET) configuration. Further, it can be applied to an amplifier such as an operational amplifier or a comparator.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A plurality of cascade-connected resistors are provided for inputting a first reference voltage output from a reference voltage generation circuit and generating a second reference voltage lower than the first reference voltage. The first and second Nch MOS transistors are provided between the resistor divider and the high potential side power source and the low potential side power source, input the second reference voltage to the input side, and form a differential pair. A differential input stage that performs differential amplification operation, and a Pch MOS transistor that is provided between the high-potential-side power supply and the low-potential-side power supply and that amplifies by inputting a signal output from the differential input stage An output stage, an output Pch MOS transistor provided on the high potential side power supply side and performing an amplification operation by inputting a signal output from the amplification stage, the output Pch MOS transistor, and the low potential side power supply Cascade between A first resistor and a second resistor connected in series; a capacitor and a third resistor connected in cascade between the output Pch MOS transistor and the first resistor and between the first and second resistors; A voltage obtained by resistance division between the capacitor and the third resistor is output as a feedback voltage to the input side of the differential input stage, and an output voltage is obtained between the output Pch MOS transistor and the first resistor. A constant voltage power supply circuit comprising an output stage for outputting.

1 is a circuit diagram showing a series regulator as a constant voltage power supply circuit according to Embodiment 1 of the present invention. The figure which shows the relationship of the gain with respect to the frequency of a series regulator which concerns on Example 1 of this invention, and a phase. The figure which shows the relationship of the gain with respect to the frequency of the conventional series regulator which concerns on Example 1 of this invention, and a phase. The circuit diagram which shows the series regulator as a constant voltage power supply circuit which concerns on Example 2 of this invention. The figure which shows the V1 / Vout phase characteristic of the series regulator which concerns on Example 2 of this invention. The circuit diagram which shows the series regulator as a constant voltage power supply circuit which concerns on Example 3 of this invention.

Explanation of symbols

1, 1a, 1b Series regulator 2 Resistance divider 3 Reference voltage generation circuit 4, 4a Differential amplifier 5, 5a, 13 Output stage 6 Level shift circuit 11 Differential input stage 12 Amplification stage BPT1 Output transistor C1 Capacitor Cout Stabilization Capacitors MN1 to MN4 Nch MOS transistors MP1 to MP4 Pch MOS transistor PT1 Output transistors R1 to R4, R11 to R13 Resistor V1 Voltage V2 between C1 and R13 Va Voltage between R11 and R12 Va Resistance divided voltage Vb Bias voltage Vcc1, Vcc2 (Vin) High Potential side power supply Vout Output voltage Vref1, Vref2 Reference voltage Vss Low potential side power supply

Claims (5)

A reference voltage step-down means for inputting a first reference voltage output from a reference voltage generating circuit and generating a second reference voltage lower than the first reference voltage;
A differential input provided between a high-potential-side power supply and a low-potential-side power supply, which inputs the second reference voltage on the input side and is provided with first and second transistors forming a differential pair, and performs an amplification operation A differential amplifying unit composed of one or more stages having stages;
An output transistor that is provided on the high potential side power supply side and that performs an amplification operation by inputting a signal output from the differential amplifier, and is cascaded between the output transistor and the low potential side power source, and is divided in resistance. A plurality of resistors that output voltages as feedback voltages to the input side of the differential input stage, and an output stage that outputs an output voltage from between the output transistor and the plurality of resistors;
A constant voltage power supply circuit comprising: A reference voltage step-down means for inputting a first reference voltage output from a reference voltage generating circuit and generating a second reference voltage lower than the first reference voltage;
A difference between the high potential side power source and the low potential side power source, wherein the second reference voltage is input to the input side and the first and second transistors forming a differential pair are provided, and the differential amplification operation is performed. Dynamic input stage;
An amplification stage that is provided between the high-potential-side power supply and the low-potential-side power supply and that performs an amplification operation by inputting a signal output from the differential input stage;
An output transistor provided on the high-potential side power supply side and performing an amplification operation by inputting a signal output from the amplification stage, and cascaded between the output transistor and the low-potential side power supply, A plurality of resistors that output feedback voltages on the input side of the differential input stage, and an output stage that outputs an output voltage from between the output transistor and the plurality of resistors;
A constant voltage power supply circuit comprising:   3. The constant voltage power supply circuit according to claim 1, wherein the reference voltage step-down means is composed of a plurality of cascade-connected resistors.   3. The constant voltage power supply circuit according to claim 1, wherein the reference voltage step-down means is composed of a level shift circuit. A level shift circuit that inputs a first reference voltage output from a reference voltage generation circuit and generates a second reference voltage that is lower than the first reference voltage;
Provided between a high potential side power source and a low potential side power source, the second reference voltage is input to the input side, and first and second Nch MOS transistors forming a differential pair are provided, and a differential amplification operation Differential input stage to
An amplification stage provided between the high-potential-side power supply and the low-potential-side power supply and provided with a Pch MOS transistor that performs an amplification operation by inputting a signal output from the differential input stage;
An output Pch MOS transistor provided on the high potential side power supply side and performing an amplification operation by inputting a signal output from the amplification stage, and a cascade connected between the output Pch MOS transistor and the low potential side power supply 1 and a second resistor, and a capacitor and a third resistor cascaded between the output Pch MOS transistor and the first resistor and between the first and second resistors, An output stage that outputs a voltage divided between the third resistors as a feedback voltage to the input side of the differential input stage and outputs an output voltage between the output Pch MOS transistor and the first resistor. When,
A constant voltage power supply circuit comprising:

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