JP2005316788A - Power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure the stabilization of output voltage while using a ceramic capacitor with low equivalent series resistance as an output stabilizing capacitor. <P>SOLUTION: This power supply circuit comprises a phase compensating transistor 4 having a source and a gate connected to an output transistor 3, and a phase compensating first register 11 provided between its drain and a ground. The voltage of the first register 11 is superposed, as phase compensating signal, on feedback signal voltage obtained by dividing the output voltage by third and fourth registers 13 and 14 through a first capacitor 21 to compensate phase delay, so that a stabilizing capacitor 22 with low equivalent series resistance can be used. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power supply circuit, and more particularly to a power supply circuit configured to output a stabilized voltage, and a capacitor having a low equivalent series resistance can be used as a capacitor for stabilizing an output voltage.

As this type of power supply circuit, for example, a power supply circuit (hereinafter referred to as an “LDO regulator circuit”) that can perform a low saturation operation (LDO) and outputs a stabilized voltage is known and well known ( For example, refer to Patent Document 1) and FIG. 7 shows an example of the circuit configuration of such an LDO regulator circuit.
The LDO regulator circuit includes a reference voltage source 40 that outputs a reference voltage VREF. The reference voltage VREF and a feedback signal voltage obtained by dividing the output voltage by resistors R3 and R4. The difference is amplified by the difference error amplifier OP and applied to the output transistor Tr1, so that the output voltage becomes a predetermined value.
Here, the output voltage Vout at the output terminal 41 is expressed by the following equation.

  Vout = VREF {(R3 + R4) / R4} Equation 1

In Equation 1, for convenience, R3 is the resistance value of the resistor R3, and R4 is the resistance value of the resistor R4.
In such a conventional LDO regulator circuit, an output voltage stabilization capacitor CL is provided between the output terminal 41 and the ground, thereby stabilizing the output voltage using the pole generated at the output terminal 41. At the same time, the output voltage is smoothed against sudden load fluctuations. In FIG. 7, ESR is an equivalent series resistance of the stabilization capacitor CL.

However, the frequency of the pole generated at the output terminal 41 changes depending on the resistance value of the load resistor RL serving as a load.
Here, assuming that the output impedance of the output transistor Tr1 is sufficiently larger than the impedance of the load resistor RL serving as a load, the frequency fp1 of the pole generated by the stabilizing capacitor CL and the load resistor RL is expressed by the following equation: 2 is represented.

  fp1 = 1 / (2π × CL × RL) Equation 2

In Equation 2, for convenience, CL is a capacitance value of the stabilization capacitor CL, and RL is a resistance value of the load resistor RL.
According to Equation 2, it can be seen that the frequency of the pole changes depending on the value of the load resistance, and moves to a lower frequency side when the resistance value is large.
On the other hand, since there are poles generated by the error amplifier OP and the output transistor Tr1, when the resistance value of the load resistance is large, the frequencies of these two poles are very close to each other, and the feedback signal voltage is reduced at a low frequency. The phase is delayed by 180 °, so the LDO regulator circuit may oscillate.

This phenomenon becomes a problem particularly when a ceramic capacitor having a low equivalent series resistance is used as the stabilization capacitor CL.
That is, normally, a capacitor has an equivalent series resistance, and a zero point occurs at a frequency determined by this resistance component and the capacitance of the capacitor. For example, assuming that the resistance value of the equivalent resistance ESR in the configuration example of FIG. 7 is RESR and the capacitance value of the stabilization capacitor CL is CL, the zero-point frequency fz1 is expressed by the following Equation 3.

  fz1 = 1 / (2π × CL × RESR) Equation 3

  Therefore, if the component of the equivalent series resistance is large, the frequency at the zero point is lowered, so that the pole described above caused by the stabilization capacitor CL is canceled and the output voltage Vout is stabilized, but the equivalent series When the resistance is small, the effect of canceling the pole due to the zero point cannot be obtained. In particular, when the resistance value of the load resistor RL is large, the output voltage Vout tends to become unstable.

JP 2002-32133 A (page 3-5, FIGS. 1 to 5)

By the way, along with the downsizing and high performance of communication devices such as mobile phones, the power supply circuit part is required to be downsized and high performance more than ever. As explained above, the output voltage is stable. A capacitor having a large equivalent series resistance is desired as a capacitor for the use of capacitors. However, there is an increasing demand for using a multilayer ceramic capacitor that is superior to others in terms of small size although the equivalent series resistance is small.
The present invention has been made in view of the above circumstances, and provides a power supply circuit that can use a ceramic capacitor having a low equivalent series resistance as a capacitor for stabilizing an output voltage and that can ensure stabilization of the output voltage. Is.

In order to achieve the above object of the present invention, a power supply circuit according to the present invention comprises:
A power supply circuit configured to obtain a stabilized output voltage such that a difference between a reference voltage and a voltage obtained by dividing the output voltage becomes zero,
A first MOS transistor for output that obtains the output voltage is provided, and a second MOS for phase compensation in which a gate and a source are connected to a gate and a source of the first MOS transistor for output, respectively. A transistor is provided, and a first resistor for phase compensation is provided between the drain of the second MOS transistor and the ground, and the voltage of the first resistor is connected to the reference voltage via a capacitor. The output voltage to be compared is configured to be superimposed on a voltage obtained by dividing the output voltage.

  According to the present invention, a voltage for phase compensation is applied to a feedback signal voltage obtained by dividing an output voltage to be compared with a reference voltage in order to stabilize the output voltage. The phase lag is compensated, and even if a low equivalent series resistance ceramic capacitor is used to stabilize the output voltage, unlike the conventional case, there is no phase lag of 180 ° at a low frequency, and a stable output voltage is obtained. There is an effect that it is possible.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first configuration example of the power supply circuit according to the embodiment of the present invention will be described with reference to FIG.
This power supply circuit has a reference voltage source 1 that outputs a reference voltage VREF, and the difference between the reference voltage VREF and a feedback signal voltage obtained by resistance division of the output voltage as described later is an error amplifier (see FIG. 1 is expressed as “OP” 2, and is applied to an output transistor (indicated as “Tr 1” in FIG. 1) 3 so that the output voltage becomes a predetermined value, so-called low saturation. This is a stabilized power supply circuit (LDO regulator circuit) for operation (LDO).

Hereinafter, the circuit configuration will be specifically described.
First, a reference voltage source 1 that outputs a reference voltage VREF is provided, and the reference voltage VREF is applied to an inverting terminal of an error amplifier 2 that uses an operational amplifier.
The output terminal of the error amplifier 2 is connected to the gate of the output transistor 3 and the gate of the phase compensation transistor (denoted as “Tr2” in FIG. 1) 4. In the embodiment of the present invention, the output transistor 3 and the phase compensation transistor 4 are both P-channel MOS field effect transistors.

The sources of the output transistor 3 and the phase compensation transistor 4 are both connected to the power supply terminal 32 so that the power supply voltage Vcc is applied.
The drain of the output transistor 3 is connected to the output terminal 31, and the third and fourth resistors (in FIG. 1, "R3" and "R4" are respectively connected between the drain and the ground. And 14) are connected in series.

On the other hand, the drain of the phase compensation transistor 4 is connected to the ground via a phase compensation first resistor (denoted as “R1” in FIG. 1) 11 and the drain and the first resistor 11. A first capacitor 21 (denoted as “C1” in FIG. 1) 21 is connected between the connection point between the first and third resistors 13 and 14.
The connection point between the third and fourth resistors 13 and 14 and the first capacitor 21 is connected to the non-inverting input terminal of the error amplifier 2 described above.

Further, a stabilization capacitor (indicated as “CL” in FIG. 1) 22 is connected between the output terminal 31 and the ground. The stabilizing capacitor 22 has an equivalent series resistance (indicated as “ESR” in FIG. 1) 22a.
A load resistor (indicated as “RL” in FIG. 1) 16 is connected to the output terminal 31 so that the output voltage Vout is output.

Next, the operation in this configuration will be described. First, the output voltage Vout is divided by the third and fourth resistors 13 and 14 and applied to the non-inverting input terminal of the error amplifier 2 as a feedback signal voltage. Then, the difference from the reference voltage VREF of the inverting input terminal is output by the error amplifier 2 and applied to the gate of the output transistor 3 so that the output voltage Vout is controlled to be a predetermined value. The operation is the same as that of the conventional circuit.
In the power supply circuit according to the embodiment of the present invention, unlike the prior art, the first resistor 11 for phase compensation is connected to the connection point of the third and fourth resistors 13 and 14 via the first capacitor 21. The phase compensation signal generated by is added.

  Here, the relationship between the phase compensation transistor 4 and the phase compensation first resistor 11 is basically the same as the relationship between the output transistor 3 and the load resistor 16. Is provided with a stabilizing capacitor 22 having a large capacity in parallel, whereas the first capacitor 21 connected to the first resistor 11 has a sufficiently small value as compared with the stabilizing capacitor 22. The difference is that things are selected. This is because, at the output terminal 31, as in the output terminal of the conventional circuit, from the values of the load resistor 16 and the stabilizing capacitor 22, as described above in the description of the conventional circuit, fp1 = 1. A pole is generated at a frequency represented by / (2π × CL × RL).

  On the other hand, from the first resistor 11 and the first capacitor 21 for phase compensation, the capacitance of the first capacitor 21 is set to a sufficiently small value as compared with the stabilization capacitor 22. The above-mentioned pole as in the output terminal 31 does not occur, and the occurrence of phase delay is avoided up to a high frequency. Then, the voltage in the first resistor 11 is connected to the third and fourth resistors 13 and 14 via the first capacitor 21, that is, in other words, the non-inverting input of the error amplifier 2. By being applied to the terminal, the frequency characteristic at the non-inverting input terminal of the error amplifier 2 acts to cancel the phase delay to zero, and is generated by the stabilizing capacitor 22 connected to the output terminal 31. Acts to cancel the pole.

As a result, the loop reaching the non-inverting input terminal of the error amplifier 2 again through the path of the non-inverting input terminal of the error amplifier 2 → the output of the error amplifier 2 → the output transistor 3 → the output terminal 31 → the third resistor 13. Unlike the conventional case, the frequency characteristic in FIG. 3 is such that the phase is not delayed by 180 ° at a low frequency, and the output voltage Vout is stabilized even if the equivalent resistance of the stabilizing capacitor 22 is small.
The values of the first capacitor 21, the first resistor 11, the third and fourth resistors 13 and 14 need to be set to appropriate values so that a stable output voltage can be obtained.

Next, a second configuration example will be described with reference to FIG. The same components as those in the configuration example shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
In the second configuration example, in particular, the first resistor 11 for phase compensation in the configuration example shown in FIG. 1 is replaced with a semiconductor active element, that is, specifically, a bipolar transistor, a diode, and a MOS. FIG. 2 shows a configuration to be replaced with a transistor or the like. In the configuration example shown in FIG. 2, an N-channel MOS field effect transistor is used as an active element.

That is, the third transistor (indicated as “Tr3” in FIG. 2) is an N-channel MOS field effect transistor, and its drain is connected to the drain of the phase compensation transistor 4 while its source is Connected to ground. The gate of the third transistor 5 is connected to the drain, and the third transistor 5 is in a so-called diode connection state.
Even in such a configuration, as described in the configuration example shown in FIG. 1, the phase compensation signal fed back through the first capacitor 21 causes a phase delay of 180 ° at a low frequency. The absence is the same as that described in the first configuration example shown in FIG. 1, and detailed description thereof will be omitted here.

Next, a third configuration example will be described with reference to FIG. The same components as those in the configuration example shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
Similarly to the second configuration example, the third configuration example is also an example in which the first resistor 11 for phase compensation in the configuration example shown in FIG. 1 is replaced with a semiconductor active device. As an example, a diode 7 (indicated as “D1” in FIG. 3) is used.
In other words, the diode 7 has an anode connected to the drain of the phase compensation transistor 4 and a cathode connected to the ground. The voltage drop generated in the diode 7 is applied to the non-inverting input terminal of the error amplifier 2 via the first capacitor 21 as a phase compensation signal, and the phase delay of 180 ° at a low frequency is eliminated in FIG. This is the same as that described in the first configuration example shown, and detailed description thereof is omitted here.

Next, a fourth configuration example will be described with reference to FIG. The same components as those in the configuration example shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
In the fourth configuration example, a second resistor (indicated as “R 2” in FIG. 1) 12 is connected between the source of the phase compensation transistor 4 and the source of the output transistor 3, and also for phase compensation. The substrate of the transistor 4 is connected to the source of the output transistor 3.

In such a configuration, the ratio of the drain currents of the output transistor 3 and the phase compensation transistor 4 varies depending on the output current value of the output transistor 3. Therefore, the magnitude of the phase compensation signal applied to the non-inverting input terminal of the error amplifier 2 through the first capacitor 21 is in accordance with the drain current ratio.
Except for this point, the point that the phase delay of 180 ° at the low frequency is eliminated is the same as that described in the first configuration example shown in FIG. 1, and detailed description thereof is omitted here. I will do it.

Next, a fifth configuration example will be described with reference to FIG. The same components as those in the configuration example shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
In the fifth configuration example, the first capacitor 21 in the configuration example shown in FIG. 1 is replaced by a fifth resistor (indicated as “R5” in FIG. 5) 15 and the first capacitor 21. The configuration is replaced with series connection.

That is, one end of the fifth resistor 15 is connected to the connection point between the phase compensation transistor 4 and the first resistor 11, and the other end of the fifth resistor 15 is connected to the first capacitor 21. It is connected to one end. The other end of the first capacitor 21 is connected to the connection point of the third and fourth resistors 13 and 14.
In such a configuration, there is a phase delay of 180 ° at a low frequency except that the phase compensation signal is applied to the non-inverting input terminal of the error amplifier 2 via the fifth resistor 15 and the first capacitor 21. The point of disappearance is the same as that described in the first configuration example shown in FIG. 1, and detailed description thereof is omitted here.

Finally, a sixth configuration example will be described with reference to FIG. The same components as those in the configuration example shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
This sixth configuration example has a configuration in which a current limiting circuit 101 for limiting the current of the output transistor 3 is added to the configuration example shown in FIG.
More specifically, the current limiting circuit 101 in this configuration example includes an operational amplifier (indicated as “OP2” in FIG. 6) 8 and a fourth transistor (indicated as “Tr4” in FIG. 6). The fourth transistor 6 is a P-channel MOS field effect transistor.

The source of the fourth transistor 6 is connected to the sources of the output transistor 3 and the phase compensation transistor 4 while the drain is connected to the gates of the output transistor 3 and the phase compensation transistor 4. It has become a thing. The output terminal of the operational amplifier 8 is connected to the gate of the fourth transistor 6.
The inverting input terminal of the operational amplifier 8 is connected to the connection point between the phase compensation transistor 4 and the first resistor 11, while the reference voltage VREF of the reference voltage source 1 is applied to the non-inverting input terminal. It is like that.

In such a configuration, the drain current of the phase compensating transistor 4 is detected as a voltage drop of the first resistor 11 and applied to the inverting input terminal of the operational amplifier 8, whereby the voltage of the first resistor 11 is detected. When the drop exceeds the reference voltage VREF (in other words, the drain current of the phase compensation transistor 4 becomes equal to or higher than a predetermined value), the fourth transistor 6 transitions to a conductive state, and thereby the drain current of the output transistor 3 Is now restricted.
Except for this point, the point that the phase delay of 180 ° at the low frequency is eliminated is the same as that described in the first configuration example shown in FIG. 1, and detailed description thereof is omitted here. I will do it.

  In the above-described configuration example, a MOS field effect transistor is used as a transistor. However, of course, the present invention is not limited to this, and a bipolar transistor may be used.

FIG. 3 is a circuit diagram illustrating a first configuration example of a power supply circuit according to the embodiment of the present invention. It is a circuit diagram which shows the 2nd structural example of the power supply circuit in embodiment of this invention. It is a circuit diagram which shows the 3rd structural example of the power supply circuit in embodiment of this invention. It is a circuit diagram which shows the 4th structural example of the power supply circuit in embodiment of this invention. It is a circuit diagram which shows the 5th structural example of the power supply circuit in embodiment of this invention. It is a circuit diagram which shows the 6th structural example of the power supply circuit in embodiment of this invention. It is a circuit diagram which shows an example of a conventional circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Reference voltage source 2 ... Error amplifier 3 ... Output transistor 4 ... Phase compensation transistor 11 ... 1st resistor 12 ... 2nd resistor 13 ... 3rd resistor 14 ... 4th resistor 15 ... 5th resistor 16 ... load resistor 22 ... stabilizing capacitor

Claims (6)

A power supply circuit configured to obtain a stabilized output voltage such that a difference between a reference voltage and a voltage obtained by dividing the output voltage becomes zero,
A first MOS transistor for output that obtains the output voltage is provided, and a second MOS for phase compensation in which a gate and a source are connected to a gate and a source of the first MOS transistor for output, respectively. A transistor is provided, and a first resistor for phase compensation is provided between the drain of the second MOS transistor and the ground, and the voltage of the first resistor is connected to the reference voltage via a capacitor. A power supply circuit configured to be superimposed on a voltage obtained by dividing the output voltage to be compared.   2. The power supply circuit according to claim 1, wherein a semiconductor active element is provided in place of the first resistor for phase compensation.   A second resistor is provided between the source of the first MOS transistor for output and the source of the second MOS transistor for phase compensation, and the drain current of the first MOS transistor for output The ratio of the drain current of the second MOS transistor for phase compensation is configured to be changeable with a change in the drain current of the first MOS transistor for output. Power supply circuit.   4. The power supply circuit according to claim 1, wherein a series connection of a resistor and a capacitor is provided in place of the capacitor.   The drain current of the first MOS transistor for output is limited according to the comparison result between the voltage corresponding to the drain current of the second MOS transistor for phase compensation and the reference voltage. The power supply circuit according to any one of claims 1, 2, 3 and 4.   6. The power supply circuit according to claim 1, wherein a bipolar transistor is used in place of the first and second MOS transistors.

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