CN103019291B - Low differential voltage linear voltage stabilizer circuit - Google Patents
Low differential voltage linear voltage stabilizer circuit Download PDFInfo
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- CN103019291B CN103019291B CN201210564196.8A CN201210564196A CN103019291B CN 103019291 B CN103019291 B CN 103019291B CN 201210564196 A CN201210564196 A CN 201210564196A CN 103019291 B CN103019291 B CN 103019291B
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Abstract
A kind of low differential voltage linear voltage stabilizer circuit, an auxiliary circuit is connected with at the output terminal of described low pressure difference linear voltage regulator, described auxiliary circuit comprises the first resistance, first electric capacity and pulling up transistor, due to described first resistance, the RC oscillatory circuit that first electric capacity is formed, make the voltage when the output terminal of low pressure difference linear voltage regulator occur negative pulse and low pressure difference linear voltage regulator be not able to do in time response time, RC oscillatory circuit is utilized to make to pull up transistor and open, utilizing pulls up transistor holds the voltage of the output terminal of low pressure difference linear voltage regulator, make the voltage drop amplitude of output terminal less, finally utilize low pressure difference linear voltage regulator again by output voltage that the voltage resume of output terminal is original.Because the voltage drop amplitude of described output terminal is less, the device cisco unity malfunction of load can not be made, the reliability of circuit in load can not be affected.And under normal circumstances, described auxiliary circuit does not need to produce power consumption, can not affect the normal work of power supply.
Description
Technical field
The present invention relates to integrated circuit fields, particularly a kind of low differential voltage linear voltage stabilizer circuit.
Background technology
Low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) has that structure is simple, low noise, low-power consumption and the advantage such as small package and less peripheral applications device, be widely used in portable type electronic product.Low pressure difference linear voltage regulator belongs to the step-down transformer in DC/DC transducer, when load is certain, its output voltage in certain scope, therefore, low differential voltage linear voltage stabilizer circuit system can ensure the stable of the output voltage of power supply, is conducive to improving power source life.
Please refer to Fig. 1, is the structural representation of existing low differential voltage linear voltage stabilizer circuit.Described low pressure difference linear voltage regulator 10 comprises: error amplifier 11, voltage-reg-ulator tube 12, second resistance 13, the 3rd resistance 14; The reverse input end of described error amplifier 11 is connected with voltage reference signal Vref, the output terminal of described error amplifier 11 is connected with the grid of described voltage-reg-ulator tube 12, the source electrode of described voltage-reg-ulator tube 12 meets high level Vdd, the drain electrode of described voltage-reg-ulator tube 12 is connected with one end of the second resistance 13, the other end of described second resistance 13, one end of the 3rd resistance 14 are connected with the positive input of error amplifier 11, the other end ground connection of described 3rd resistance 14; Wherein, described voltage reference signal Vref is as the input signal of low pressure difference linear voltage regulator, and one end that the drain electrode of described voltage-reg-ulator tube 12 is connected with the second resistance R2 is as the output end vo ut of low pressure difference linear voltage regulator.
Because the equivalent resistance of the output terminal of described low pressure difference linear voltage regulator can change along with the change of load, the voltage of output terminal can be changed a lot, produce overshoot (overshoot) or lose punching (undershoot).Such as when the load current of the load be connected with output terminal becomes large suddenly, the voltage of the output terminal of low pressure difference linear voltage regulator can diminish suddenly, produce and lose punching (undershoot), and need the regular hour because low pressure difference linear voltage regulator responds, before voltage-reg-ulator tube 12 is not completely by the voltage resume of output terminal to original output voltage, the voltage of described output terminal has a negative pulse.When originally stable output voltage is 3.3V, the voltage being dragged down rear output terminal by described negative pulse only has 1V even lower, may make part of devices cisco unity malfunction, can have a strong impact on the reliability of circuit in load.
Therefore, please refer to Fig. 1, usually can add an output capacitance 15 at the output end vo ut of described low pressure difference linear voltage regulator 10, described output capacitance 15 has an equivalent series resistance 16.Utilize described output capacitance 15 to compensate the electric current increased suddenly, thus reduce negative pulse.But owing to being subject to the consideration of technique and cost of manufacture, the electric capacity of described output capacitance 15 is usually less, effectively can not compensate the electric current increased suddenly, still can form larger negative pulse, still can be down to 1.5V by the voltage that described negative pulse drags down rear output terminal even lower.
More information about low pressure difference linear voltage regulator, please refer to the Chinese patent literature that application publication number is CN102200791A.
Summary of the invention
The problem that the present invention solves is to provide a kind of low differential voltage linear voltage stabilizer circuit, and when making load current become large suddenly, the negative pulse that the output terminal of low pressure difference linear voltage regulator produces is less.
For solving the problem, technical solution of the present invention provides a kind of low differential voltage linear voltage stabilizer circuit, comprising: low pressure difference linear voltage regulator and the auxiliary circuit be connected with the output terminal of described low pressure difference linear voltage regulator; Wherein, described auxiliary circuit comprises the first resistance, the first electric capacity and pulls up transistor, described one end of first resistance is connected with the output terminal of low pressure difference linear voltage regulator, the other end of described first resistance, one end of the first electric capacity are connected with the grid pulled up transistor, the described drain electrode pulled up transistor is connected with the first high level, the described source electrode pulled up transistor is connected with the output terminal of low pressure difference linear voltage regulator, and the other end of described first electric capacity is connected with the second high level.
Optionally, pull up transistor described in as nmos pass transistor.
Optionally, the breadth length ratio of the grid of described nmos pass transistor is more than or equal to 100.
Optionally, the threshold voltage of described nmos pass transistor is greater than 0V, is less than or equal to 1V.
Optionally, the time constant of the RC oscillatory circuit of described first resistance, the first electric capacity formation is more than or equal to the response time of low pressure difference linear voltage regulator.
Optionally, also comprise: the output capacitance be connected with the output terminal of described low pressure difference linear voltage regulator.
Optionally, described output capacitance is ceramic electrical perhaps tantalum electric capacity.
Optionally, described voltage difference linear voltage regulator comprises: error amplifier, voltage-reg-ulator tube, the second resistance, the 3rd resistance, and described second resistance, the 3rd resistance are as feedback network; The reverse input end of described error amplifier is connected with voltage reference signal, the output terminal of described error amplifier is connected with the control end of described voltage-reg-ulator tube, the first end of described voltage-reg-ulator tube is connected with third high level, second end of described voltage-reg-ulator tube is connected with one end of the second resistance, the other end of described second resistance, one end of the 3rd resistance are connected with the positive input of error amplifier, the other end ground connection of described 3rd resistance; Wherein, described voltage reference signal is as the input signal of low pressure difference linear voltage regulator, and the second end of described voltage-reg-ulator tube is as the output terminal of low pressure difference linear voltage regulator.
Optionally, described voltage-reg-ulator tube is NPN Darlington transistor, NPN pipe, PNP pipe, nmos pass transistor or PMOS transistor.
Optionally, when described voltage-reg-ulator tube is PMOS transistor, the output terminal of described error amplifier is connected with the grid of described PMOS transistor, and the source electrode of described PMOS transistor is connected with third high level, and the drain electrode of described PMOS transistor is connected with one end of the second resistance.
Optionally, also comprise: the impact damper between the output terminal and the control end of described voltage-reg-ulator tube of described error amplifier.
Optionally, described impact damper is source follower or CMOS buffer.
Optionally, described error amplifier has thermal-shutdown circuit, overvoltage crowbar, current foldback circuit, under-voltage protecting circuit or reverse-connection protection circuit wherein one or more.
Optionally, the concrete structure of described error amplifier comprises: the source electrode of the first PMOS transistor, the second PMOS transistor, the 3rd PMOS transistor, the 4th PMOS transistor is connected with supply voltage; The grid of the first PMOS transistor, the second PMOS transistor is connected with the drain electrode of the drain electrode of the second PMOS transistor, the second nmos pass transistor, and the grid of described 3rd PMOS transistor, the 4th PMOS transistor is connected with the drain electrode of the drain electrode of the 3rd PMOS transistor, the 3rd nmos pass transistor; The drain electrode of described first PMOS transistor is connected with the drain electrode of the first nmos pass transistor, grid, the drain electrode of described 4th PMOS transistor is connected with the drain electrode of the 4th nmos pass transistor, and described first nmos pass transistor is connected with the grid of the 4th nmos pass transistor; The grid of described second nmos pass transistor, as the reverse input end of error amplifier, is connected with voltage reference signal; The grid of described 3rd nmos pass transistor, as the positive input of error amplifier, is connected with described second resistance, the 3rd resistance; The source ground of described first nmos pass transistor, the 4th nmos pass transistor, the source electrode of described second nmos pass transistor, the 3rd nmos pass transistor is connected with one end of current source, and the other end ground connection of described current source.
Compared with prior art, the present invention has the following advantages:
The embodiment of the present invention is connected with an auxiliary circuit at the output terminal of described low pressure difference linear voltage regulator, described auxiliary circuit comprises the first resistance, first electric capacity and pulling up transistor, due to described first resistance, the RC oscillatory circuit that first electric capacity is formed, make the voltage when the output terminal of low pressure difference linear voltage regulator occur negative pulse and low pressure difference linear voltage regulator be not able to do in time response time, described RC oscillatory circuit is utilized to make to pull up transistor and open, pull up transistor described in utilization and the voltage of the output terminal of low pressure difference linear voltage regulator drawn high, make the voltage drop amplitude of output terminal less, finally utilize low pressure difference linear voltage regulator again by output voltage that the voltage resume of output terminal is original.Because the voltage drop amplitude of described output terminal is less, the device cisco unity malfunction of load can not be made, the reliability of circuit in load can not be affected.And under normal circumstances, described auxiliary circuit does not need to produce power consumption, can not affect the normal work of power supply.
Further, the timeconstantτ of the RC oscillatory circuit that described first resistance, the first electric capacity are formed is more than or equal to the response time of low pressure difference linear voltage regulator, response time regardless of low pressure difference linear voltage regulator is longer or shorter, in a timeconstantτ, the described grid voltage fall pulled up transistor is little, and intermediate voltage output also can not be declined a lot.Timeconstantτ is less than or equal to when the response time of described low pressure difference linear voltage regulator, intermediate voltage output fall too low before, described low pressure difference linear voltage regulator by the voltage resume of output terminal to normal output voltage, the normal work of load circuit can not be affected.
Accompanying drawing explanation
Fig. 1 is the structural representation of the low differential voltage linear voltage stabilizer circuit of prior art;
Fig. 2 to Fig. 5 is the structural representation of the low differential voltage linear voltage stabilizer circuit of the embodiment of the present invention;
Fig. 6 is the change comparison diagram of the voltage of the output terminal of the low pressure difference linear voltage regulator of the embodiment of the present invention and prior art.
Embodiment
Due to when load current becomes large suddenly, the output terminal of the low differential voltage linear voltage stabilizer circuit of prior art can produce a negative pulse, and described negative pulse can make part of devices cisco unity malfunction, can have a strong impact on the reliability of circuit in load.Even if be connected with an output capacitance at the output terminal of low pressure difference linear voltage regulator, owing to being subject to the consideration of technique and cost of manufacture, the electric capacity of described output capacitance is usually less, and the final negative pulse produced is still larger.
For this reason, embodiments provide a kind of low differential voltage linear voltage stabilizer circuit, an auxiliary circuit is connected with at the output terminal of described low pressure difference linear voltage regulator, described auxiliary circuit comprises the first resistance, first electric capacity and pulling up transistor, due to described first resistance, the RC oscillatory circuit that first electric capacity is formed, make the voltage when the output terminal of low pressure difference linear voltage regulator occur negative pulse and low pressure difference linear voltage regulator be not able to do in time response time, described RC oscillatory circuit is utilized to make to pull up transistor and open, pull up transistor described in utilization and the voltage of the output terminal of low pressure difference linear voltage regulator held, make the voltage drop amplitude of output terminal less, finally utilize low pressure difference linear voltage regulator again by output voltage that the voltage resume of output terminal is original.Because the voltage drop amplitude of described output terminal is less, the device cisco unity malfunction of load can not be made, the reliability of circuit in load can not be affected.And under normal circumstances, described auxiliary circuit does not need to produce power consumption, can not affect the normal work of power supply.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
The embodiment of the present invention provide firstly a kind of low differential voltage linear voltage stabilizer circuit, please refer to Fig. 2, for the structural representation of the low differential voltage linear voltage stabilizer circuit of the embodiment of the present invention, specifically comprise: low pressure difference linear voltage regulator 110, the output terminal of described low pressure difference linear voltage regulator 110 is connected with an auxiliary circuit 130, described auxiliary circuit 130 comprises the first resistance R1, first electric capacity C1 and pull up transistor 135, described one end of first resistance R1 is connected with the output end vo ut of low pressure difference linear voltage regulator 110, the other end of described first resistance R1, one end of first electric capacity C1 with pull up transistor 135 grid be connected, described pull up transistor 135 drain electrode be connected with the first high level Vdd1, the described source electrode of 135 that pulls up transistor is connected with the output end vo ut of low pressure difference linear voltage regulator 110, the output end vo ut of described low pressure difference linear voltage regulator 110 is connected with load (not shown), the other end of described first electric capacity C1 is connected with the second high level Vdd2.
In the present embodiment, the voltage of described first high level Vdd1 and the second high level Vdd2 is equal, and be all 6V, the output voltage of described low pressure difference linear voltage regulator 110 is 3.3V under normal circumstances.The output voltage of described low pressure difference linear voltage regulator is less than the voltage of the first high level Vdd1 and the second high level Vdd2.In other embodiments, the voltage of described first high level Vdd1 and the second high level Vdd2 also can be unequal, the scope of the voltage of described first high level Vdd1 and the second high level Vdd2 is 2V ~ 6V, when making to form negative pulse, the voltage of the output end vo ut of described low pressure difference linear voltage regulator 110 is at least greater than 2V, avoids the brownout of the output end vo ut of low pressure difference linear voltage regulator 110 to affect the stability of the circuit of load.
In the present embodiment, 135 are pulled up transistor described in for nmos pass transistor.In the present embodiment, the breadth length ratio of the grid of described nmos pass transistor is more than or equal to 100, and larger breadth length ratio is conducive to the pull-up speed of quickening first high level to output end voltage.And the threshold voltage of described nmos pass transistor is greater than 0V and is less than or equal to 1V, less threshold voltage is conducive to improving the response time pulled up transistor, the voltage of output end vo ut is made just to have started to reduce, pull up transistor and will open, thus utilize the first high level to carry out pull-up to the voltage of output end vo ut.
In other embodiments, the breadth length ratio of the grid of described nmos pass transistor also can be less than 100, and the threshold voltage of described nmos pass transistor also can be greater than 1V.
In the present embodiment, the time constant of the RC oscillatory circuit of described first resistance R1, the first electric capacity C1 formation is more than or equal to the response time of low pressure difference linear voltage regulator 110.Response time of described low pressure difference linear voltage regulator 110 is the voltage of the output terminal of low pressure difference linear voltage regulator 110 when changing, and utilizes described low pressure difference linear voltage regulator 110 by the time of the voltage resume of output terminal.The response time of different low pressure difference linear voltage regulators 110 is different, and when the described response time is long, the duration that the voltage of output terminal changes is longer, and the step-down that negative pulse causes is larger, more easily makes device cisco unity malfunction.In order to be shortened the response time of low pressure difference linear voltage regulator 110, need to redesign the circuit of low pressure difference linear voltage regulator 110, increase many devices, make the circuit of low pressure difference linear voltage regulator 110 more complicated, power consumption is higher.And utilize the auxiliary circuit of the embodiment of the present invention, no matter the response time of low pressure difference linear voltage regulator 110 is shorter or longer, and the output voltage that can effectively suppress negative pulse to cause declines, and avoids the stability of the circuit affecting load.
Please refer to Fig. 3, be the electrical block diagram of the low pressure difference linear voltage regulator 110 in Fig. 2, described low pressure difference linear voltage regulator 110 comprises: error amplifier 111, voltage-reg-ulator tube 112, second resistance R2, the 3rd resistance R3; The reverse input end of described error amplifier 111 is connected with voltage reference signal Vref, the output terminal of described error amplifier 111 is connected with the control end of described voltage-reg-ulator tube 112, the first end of described voltage-reg-ulator tube 112 is connected with third high level Vdd3, second end of described voltage-reg-ulator tube 112 is connected with one end of the second resistance R2, the other end of described second resistance R2, one end of the 3rd resistance R3 are connected with the positive input of error amplifier 111, the other end ground connection of described 3rd resistance R3; Wherein, described voltage reference signal Vref is as the input signal of low pressure difference linear voltage regulator 110, and one end that the second end of described voltage-reg-ulator tube 112 is connected with the second resistance R2 is as the output end vo ut of low pressure difference linear voltage regulator; Described second resistance R2, the 3rd resistance R3 form feedback network 115, utilize described feedback network the situation of change of the voltage of output end vo ut to be fed back to the positive input of low pressure error amplifier 111 by sampling voltage.
In the present embodiment, please refer to Fig. 4, for the structural representation of the described error amplifier 111 in Fig. 3, comprise: the first PMOS transistor MP1, the second PMOS transistor MP2, the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the first nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4 and current source, the source electrode of described first PMOS transistor MP1, the second PMOS transistor MP2, the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4 is connected with supply voltage; The grid of the first PMOS transistor MP1, the second PMOS transistor MP2 is connected with the drain electrode of the drain electrode of the second PMOS transistor MP2, the second nmos pass transistor MN2, and the grid of described 3rd PMOS transistor MP3, the 4th PMOS transistor MP4 is connected with the drain electrode of the drain electrode of the 3rd PMOS transistor MP3, the 3rd nmos pass transistor MN3; The drain electrode of described first PMOS transistor MP1 is connected with the drain electrode of the first nmos pass transistor MN1, grid, the drain electrode of described 4th PMOS transistor MP4 is connected with the drain electrode of the 4th nmos pass transistor MN4, and the grid of described first nmos pass transistor MN1 is connected with the grid of the 4th nmos pass transistor MN4; The grid of described second nmos pass transistor MN2, as the reverse input end of error amplifier, is connected with voltage reference signal; The grid of described 3rd nmos pass transistor MN3, as the positive input of error amplifier, is connected with described feedback network 115; The source electrode of described first nmos pass transistor MN1 and the source ground of the 4th nmos pass transistor MN4, the source electrode of described second nmos pass transistor MN2 is connected with one end of current source with the source electrode of the 3rd nmos pass transistor MN3, and the other end ground connection of described current source.
The magnitude of voltage of the sampling voltage that described feedback network 115 provides by described error amplifier 111 and voltage reference signal compares, when both occur deviation, after described deviation is amplified by error amplifier 111, and the pressure drop of control voltage Correctional tube 112.In the present embodiment, the sampling voltage value being input to positive input when feedback network 115 reduces, difference between the magnitude of voltage of voltage reference signal Vref and the sampling voltage value of positive input increases, both differences are after error amplifier 111 amplifies, the drive current of error amplifier 111 output terminal increases, the voltage of the control end being applied to voltage-reg-ulator tube 112 is increased, conducting resistance between voltage-reg-ulator tube 112 first end and the second end reduces, the pressure drop at voltage-reg-ulator tube 112 two ends reduces, thus the voltage of the output terminal of low pressure difference linear voltage regulator 110 is raised, return to normal output voltage.
In other embodiments, described error amplifier can also adopt other circuit structure.Due to the integrated circuit unit that error amplifier is this area routine, concrete circuit structure is a lot, and therefore not to repeat here.
In the present embodiment, described voltage-reg-ulator tube 112 is PMOS transistor, the grid of described PMOS transistor is connected with the output terminal of error amplifier 111, the source electrode of described PMOS transistor is connected with third high level Vdd3, and the drain electrode of described PMOS transistor is connected with one end of the second resistance R2.By controlling the grid voltage of described PMOS transistor, control the source and drain resistance of PMOS transistor, thus control the pressure drop at described PMOS transistor source and drain two ends.
In other embodiments, described voltage-reg-ulator tube can also be NPN Darlington transistor, NPN pipe, PNP pipe, nmos pass transistor.
In the present embodiment, the voltage of described third high level Vdd3 is identical with the voltage of the first high level Vdd1, the second high level Vdd2.In other embodiments, the voltage of described third high level Vdd3 is different from the voltage of the first high level Vdd1, the second high level Vdd2, and the voltage of described third high level Vdd3 is greater than the output voltage of low pressure difference linear voltage regulator 110 output end vo ut under normal circumstances.
In other embodiments, impact damper can also be had between the output terminal of described error amplifier and the control end of voltage-reg-ulator tube, for the larger stray capacitance over the ground of the grid of the output terminal and voltage-reg-ulator tube of isolating error amplifier, and make described grid capacitance have Slew Rate driving faster, the response time of low pressure difference linear voltage regulator can be improved, thus reduce overshoot or lose punching.Wherein in an embodiment, described impact damper is source follower, CMOS buffer or other suitable impact dampers.
In other embodiments, described low pressure difference linear voltage regulator can also have thermal-shutdown circuit, overvoltage crowbar, current foldback circuit, under-voltage protecting circuit or reverse-connection protection circuit wherein one or more.
In other embodiments, please refer to Fig. 5, output capacitance C can also be connected with at the output terminal 110 of described low pressure difference linear voltage regulator 110
l, described output capacitance C
lthere is an equivalent series resistance R
eSR, utilize described output capacitance C
lsuddenly the electric current increased is compensated, thus reduces negative pulse.Described output capacitance C
lfor ceramic electrical perhaps tantalum electric capacity.
When not forming negative pulse, the voltages keep constant of the output terminal of described low pressure difference linear voltage regulator 110, corresponding, described pull up transistor 135 grid voltage and source voltage keep constant, in the present embodiment, the output voltage of described low pressure difference linear voltage regulator 110 is 3.3V, and the magnitude of voltage of described voltage reference signal Vref is equal with the sampling voltage value that feedback network 115 is input to positive input.
When load causes load current to increase suddenly, the voltage being applied to voltage-reg-ulator tube 112 two ends increases suddenly, and the voltage of the output end vo ut of low pressure difference linear voltage regulator is reduced suddenly, forms negative pulse.Simultaneously, described pull up transistor 135 source voltage reduce suddenly, but due to the effect of the RC oscillatory circuit that the first resistor R1, the first electric capacity C1 are formed, described pull up transistor 135 grid voltage can't reduce at once, therefore, described pull up transistor 135 gate source voltage become large, make to pull up transistor 135 channel region open, utilize the voltage of the first high level Vdd1 to the output terminal of described low pressure difference linear voltage regulator 110 to boost, the voltage of the output terminal of described low pressure difference linear voltage regulator 110 only can slightly be reduced.And when described in pull up transistor 135 gate source voltage again diminish, be less than pull up transistor 135 threshold voltage time, described pull up transistor 135 channel region close, first high level Vdd1 does not continue to boost to the voltage of the output terminal of described low pressure difference linear voltage regulator 110, make the voltage stabilization of the output terminal of final low pressure difference linear voltage regulator 110 at an intermediate voltage output, the output end voltage that described intermediate voltage output causes much larger than negative pulse in prior art, until later use low pressure difference linear voltage regulator again by the voltage resume of the output terminal of low pressure difference linear voltage regulator 110 to original output voltage.The voltage that described intermediate voltage output approximates the second high level Vdd1 deduct pull up transistor 135 threshold voltage.By control described second high level Vdd1 voltage and pull up transistor 135 threshold voltage, namely described intermediate voltage output can be controlled, described intermediate voltage output is far longer than in prior art because of very little output end voltage that negative pulse causes, close to original output voltage, ensure stability and the reliability of power supply and load.And under normal circumstances, pulling up transistor of described auxiliary circuit 135 is not opened, and can not produce extra power consumption, can not affect the normal use of power supply.
In the present embodiment, the timeconstantτ of the RC oscillatory circuit of described first resistance R1, the first electric capacity C2 formation is more than or equal to the response time of low pressure difference linear voltage regulator 110.Response time regardless of low pressure difference linear voltage regulator 110 is longer or shorter, in a timeconstantτ, described pull up transistor 135 grid voltage fall little, make intermediate voltage output also can not decline a lot, timeconstantτ is less than or equal to when the response time of described low pressure difference linear voltage regulator, intermediate voltage output fall too low before, described low pressure difference linear voltage regulator by the voltage resume of output terminal to normal output voltage, by the capacitance of the resistance value and the first electric capacity C2 that adjust the first resistance R1, just can ensure that the voltage of output terminal can not decline too low, can not impact load circuit.And be generally tens microseconds to hundreds of microsecond due to the response time of low pressure difference linear voltage regulator 110, the capacitance of described first electric capacity C2 is usually less, the order of magnitude is generally nanofarad or pico farad rank, and the order of magnitude of the output capacitance of prior art is generally microfarad rank, therefore the chip area shared by described auxiliary circuit is very little, and cost is lower.
Please refer to Fig. 6, be the change comparison diagram of the voltage of the output terminal of the low pressure difference linear voltage regulator of the embodiment of the present invention and prior art, horizontal ordinate is the time, and ordinate is the magnitude of voltage of output terminal.At the time point of T1, the voltage of the output terminal of described low pressure difference linear voltage regulator reduces suddenly due to the impact of load, at the time point of T2, utilize described low pressure difference linear voltage regulator that the magnitude of voltage of output terminal is reverted to original output voltage again, time between described T1 and T2 is response time of low pressure difference linear voltage regulator, and dotted line represents the situation of change of the magnitude of voltage causing output terminal in prior art because of negative pulse, solid line represents the situation of change causing the magnitude of voltage of output terminal because of negative pulse of the embodiment of the present invention.Because the unlatching pulled up transistor can make the voltage of the first high level Vdd1 to output terminal draw high, thus the intermediate voltage output that formation one is more stable, described intermediate voltage output is far longer than the voltage of the very little output terminal caused because of negative pulse in prior art, ensures stability and the reliability of power supply and load.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (14)
1. a low differential voltage linear voltage stabilizer circuit, is characterized in that, comprising:
Low pressure difference linear voltage regulator and the auxiliary circuit be connected with the output terminal of described low pressure difference linear voltage regulator;
Wherein, described auxiliary circuit comprises the first resistance, the first electric capacity and pulls up transistor, described one end of first resistance is connected with the output terminal of low pressure difference linear voltage regulator, the other end of described first resistance, one end of the first electric capacity are connected with the grid pulled up transistor, the described drain electrode pulled up transistor is connected with the first high level, the described source electrode pulled up transistor is connected with the output terminal of low pressure difference linear voltage regulator, and the other end of described first electric capacity is connected with the second high level.
2. low differential voltage linear voltage stabilizer circuit as claimed in claim 1, is characterized in that, described in pull up transistor as nmos pass transistor.
3. low differential voltage linear voltage stabilizer circuit as claimed in claim 2, it is characterized in that, the breadth length ratio of the grid of described nmos pass transistor is more than or equal to 100.
4. low differential voltage linear voltage stabilizer circuit as claimed in claim 2, it is characterized in that, the threshold voltage of described nmos pass transistor is greater than 0V, and is less than or equal to 1V.
5. low differential voltage linear voltage stabilizer circuit as claimed in claim 1, is characterized in that, the time constant of the RC oscillatory circuit that described first resistance, the first electric capacity are formed is more than or equal to the response time of described low pressure difference linear voltage regulator.
6. low differential voltage linear voltage stabilizer circuit as claimed in claim 1, is characterized in that, also comprise: the output capacitance be connected with the output terminal of described low pressure difference linear voltage regulator.
7. low differential voltage linear voltage stabilizer circuit as claimed in claim 6, it is characterized in that, described output capacitance is ceramic electrical perhaps tantalum electric capacity.
8. low differential voltage linear voltage stabilizer circuit as claimed in claim 1, it is characterized in that, described low pressure difference linear voltage regulator comprises: error amplifier, voltage-reg-ulator tube, the second resistance, the 3rd resistance, and described second resistance, the 3rd resistance are as feedback network; The reverse input end of described error amplifier is connected with voltage reference signal, the output terminal of described error amplifier is connected with the control end of described voltage-reg-ulator tube, the first end of described voltage-reg-ulator tube is connected with third high level, second end of described voltage-reg-ulator tube is connected with one end of the second resistance, the other end of described second resistance, one end of the 3rd resistance are connected with the positive input of error amplifier, the other end ground connection of described 3rd resistance; Wherein, described voltage reference signal is as the input signal of low pressure difference linear voltage regulator, and the second end of described voltage-reg-ulator tube is as the output terminal of low pressure difference linear voltage regulator.
9. low differential voltage linear voltage stabilizer circuit as claimed in claim 8, it is characterized in that, described voltage-reg-ulator tube is NPN Darlington transistor, NPN pipe, PNP pipe, nmos pass transistor or PMOS transistor.
10. low differential voltage linear voltage stabilizer circuit as claimed in claim 9, it is characterized in that, when described voltage-reg-ulator tube is PMOS transistor, the output terminal of described error amplifier is connected with the grid of described PMOS transistor, the source electrode of described PMOS transistor is connected with third high level, and the drain electrode of described PMOS transistor is connected with one end of the second resistance.
11. low differential voltage linear voltage stabilizer circuits as claimed in claim 8, is characterized in that, also comprise: the impact damper between the output terminal and the control end of described voltage-reg-ulator tube of described error amplifier.
12. low differential voltage linear voltage stabilizer circuits as claimed in claim 11, it is characterized in that, described impact damper is source follower or CMOS buffer.
13. low differential voltage linear voltage stabilizer circuits as claimed in claim 8, it is characterized in that, described error amplifier has thermal-shutdown circuit, overvoltage crowbar, current foldback circuit, under-voltage protecting circuit or reverse-connection protection circuit wherein one or more.
14. low differential voltage linear voltage stabilizer circuits as claimed in claim 8, it is characterized in that, the concrete structure of described error amplifier comprises: the first PMOS transistor MP1, the second PMOS transistor MP2, the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the first nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4 and current source, and the source electrode of described first PMOS transistor, the second PMOS transistor, the 3rd PMOS transistor, the 4th PMOS transistor is connected with supply voltage; The grid of the first PMOS transistor, the second PMOS transistor is connected with the drain electrode of the drain electrode of the second PMOS transistor, the second nmos pass transistor, and the grid of described 3rd PMOS transistor, the 4th PMOS transistor is connected with the drain electrode of the drain electrode of the 3rd PMOS transistor, the 3rd nmos pass transistor; The drain electrode of described first PMOS transistor is connected with the drain electrode of the first nmos pass transistor, grid, the drain electrode of described 4th PMOS transistor is connected with the drain electrode of the 4th nmos pass transistor, and described first nmos pass transistor is connected with the grid of the 4th nmos pass transistor; The grid of described second nmos pass transistor, as the reverse input end of error amplifier, is connected with voltage reference signal; The grid of described 3rd nmos pass transistor, as the positive input of error amplifier, is connected with described second resistance, the 3rd resistance; The drain electrode of described 4th PMOS transistor is connected with the control end of described voltage-reg-ulator tube with the output terminal of the tie point of the drain electrode of the 4th nmos pass transistor as described error amplifier; The source ground of described first nmos pass transistor, the 4th nmos pass transistor, the source electrode of described second nmos pass transistor, the 3rd nmos pass transistor is connected with one end of current source, and the other end ground connection of described current source.
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| CN103019291B true CN103019291B (en) | 2015-10-21 |
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| CN103970171A (en) * | 2013-11-26 | 2014-08-06 | 苏州贝克微电子有限公司 | CMOS voltage stabilizing circuit |
| CN103970176B (en) * | 2014-05-26 | 2015-12-30 | 万高(杭州)科技有限公司 | A kind of low-dropout linear voltage-regulating circuit and application system thereof |
| CN104020811B (en) * | 2014-06-11 | 2016-03-02 | 深圳市威益德科技有限公司 | Plurality of voltages regulator circuit |
| US9893757B2 (en) * | 2016-02-11 | 2018-02-13 | Texas Instruments Incorporated | Pulse-shaping LDO provides first and second slew-rate increases in amplitude |
| CN105652945B (en) * | 2016-04-01 | 2017-05-03 | 电子科技大学 | Low dropout regulator |
| CN106708151B (en) * | 2016-12-26 | 2018-02-06 | 上海迦美信芯通讯技术有限公司 | A kind of low-power consumption low pressure difference linear voltage regulator system |
| US10025334B1 (en) * | 2016-12-29 | 2018-07-17 | Nuvoton Technology Corporation | Reduction of output undershoot in low-current voltage regulators |
| JP7031983B2 (en) * | 2018-03-27 | 2022-03-08 | エイブリック株式会社 | Voltage regulator |
| CN108616260B (en) * | 2018-04-02 | 2022-05-10 | 广州慧智微电子股份有限公司 | Power supply circuit of power amplifier |
| US10795392B1 (en) * | 2019-04-16 | 2020-10-06 | Novatek Microelectronics Corp. | Output stage circuit and related voltage regulator |
| CN112667018B (en) * | 2020-12-14 | 2022-12-02 | 思瑞浦微电子科技（苏州）股份有限公司 | Power supply electrifying overshoot-prevention circuit based on LDO (Low dropout regulator) |
| CN113342115B (en) * | 2021-06-30 | 2022-12-20 | 上海料聚微电子有限公司 | LDO circuit |
| CN114740939B (en) * | 2022-04-19 | 2024-01-19 | 海光信息技术股份有限公司 | Power supply generating circuit, chip and voltage detecting and compensating method |
| CN117270619B (en) * | 2023-11-17 | 2024-02-09 | 苏州贝克微电子股份有限公司 | Circuit structure for improving stability of output voltage |
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