CN102096434B - High-slew-rate error amplifier-based high-accuracy and high-speed low dropout (LDO) regulator circuit - Google Patents

Abstract

The invention discloses a high-slew-rate error amplifier-based high-accuracy and high-speed low dropout (LDO) regulator circuit, which comprises an over-the-air (OTA) circuit, a second-stage push-pull output circuit, a Miller compensation and dynamic zero compensation circuit, a load current detection circuit, a super source-level follower, a dynamic offset pipe, a feedback network and an output and load circuit. By the LDO circuit, the problems of low gain, low accuracy, low power supply suppression ratio and low response speed of the conventional LDO are solved.

Description

A kind of based on the high-precision high-speed LDO circuit of putting on the rate error amplifier

Technical field

The present invention relates to a kind of high-precision high-speed low pressure difference linear voltage regulator (LDO) circuit, belong to power management chip analoglike technical field of integrated circuits based on height pendulum rate error amplifier.

Background technology

Low pressure difference linear voltage regulator LDO is a kind of step-down type dc linear voltage regulator, along with the widespread use of portable equipment, and the developing rapidly of computing machine, communication and automobile and other industries, power management class chip technology constantly develops.Compare with the DC-DC switching voltage converter because have that cost is low, circuit structure is simple, chip occupying area is little, advantages such as low noise and high ripple inhibition ability, LDO has become one type of important circuit in the power management chip.Along with the raising of electronic system to power requirement, traditional LDO can not satisfy the requirement of people to indexs such as chip efficient, noise, precision, mappings.Thereby the research of high-performance LDO has become the power management chip hot research fields.

Tradition LDO pressurizer system block diagram is as shown in Figure 1, and system is by two trsanscondutance amplifier g _M1, g _MP, buffer and feedback network constitute.For stronger carrying load ability is arranged, the area of general adjustment pipe MP is bigger, and the grid of managing in adjustment forms the input capacitance up to tens of pF.Utilize the buffer circuit, can isolate g _M1The big input capacitance of the high output impedance of level and adjustment tube grid, the low output resistance of buffer will produce a high frequency poles with the big input capacitance of adjustment tube grid, thereby has improved the bandwidth of system, has guaranteed the stability of loop.Cc in the block diagram is a miller compensation electric capacity, and the effect of Rc is to be used for eliminating the RHP zero point that produces owing to feedforward path.This moment, total system also had two limits in unity gain bandwidth:

${\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA0000040212300000042.png"\; state="\{\{state\}\}">p</figure-callout>}1}=\frac{1}{r_1{g}_{\mathrm{mp}}{r}_{\mathrm{out}}{C}_c},$ ${\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000040212300000022.png"\; state="\{\{state\}\}">p</figure-callout>}2}=\frac{g_{\mathrm{MP}}}{C_L}---\left(1\right)$

R in the formula _Out=(R _F1+ R _F2The R of) // _L//r _DsMPBe to guarantee the stability of system, just must choose appropriate C c and make ω _P2＞ω _P1, but when load current increases, inferior gain per stage g _MPr _OutReduce, Miller effect weakens, and will cause ω like this _P1To ω _P2Near, cause the system stability variation.For guaranteeing the stability of system under the heavy load condition, just need to increase Miller capacitance, this will cause the increase of system bandwidth reduction and chip area.Because this system has only a constant main amplifier stage g _MP, cause the open-loop voltage gain of system very little, cause the load regulation of system and line regulation relatively poor, can not be applied to the occasion very high to power requirement.

Summary of the invention

The present invention seeks to provides a kind of based on the high-precision high-speed LDO circuit of putting on the rate error amplifier to the defective that prior art exists; Employing is based on the system architecture of height pendulum rate error amplifier and compensation of load detection dynamic self-adapting and super source class follower; Solved the low gain of traditional LDO, low precision, low PSRR and the slow problem of response speed, the voltage overshoot that the system that effectively reduced produces when load changing with owe to dash.

The present invention adopts following technical scheme for realizing above-mentioned purpose:

The present invention is a kind of based on the high-precision high-speed LDO circuit of putting on the rate error amplifier; Comprise OTA circuit, second level push-pull output circuit, miller compensation and dynamic zero compensation circuit, load current detection circuit, super source class follower, dynamic bias pipe, feedback network and output and load circuit; The output terminal of OTA circuit connects the input end of second level push-pull output circuit and miller compensation and dynamic zero compensation circuit respectively; The input end of the super source class follower of output termination of second level push-pull output circuit; The input end of the miller compensation and the output termination load current detection circuit of dynamic zero compensation circuit; Super source class follower output terminal connects grid and drain electrode, the output terminal of load current detection circuit and the input end of output and load circuit of dynamic bias pipe respectively; The input end of the output termination feedback network of output and load circuit; OTA circuit, second level push-pull output circuit, miller compensation and dynamic zero compensation circuit, load current detection circuit, super source class follower, dynamic bias pipe and output and load circuit be external power source altogether, and OTA circuit, second level push-pull output circuit, load current detection circuit, super source class follower, feedback network are connected with output and load circuit altogether.

Said OTA circuit comprise tail current source, input difference to the load current mirror; Wherein load current mirror transmission output stage is made up of eight N type metal-oxide-semiconductor NM3 to NM10; The drain electrode of N type metal-oxide-semiconductor NM3 connects output terminal and N type metal-oxide-semiconductor NM5, the NM8 of differential input stage, the grid of NM9 respectively; The drain electrode of N type metal-oxide-semiconductor NM3 connects another output terminal and N type metal-oxide-semiconductor NM6, the NM7 of differential input stage, the grid of NM10 respectively; The source electrode of N type metal-oxide-semiconductor NM3 connects the drain electrode of N type metal-oxide-semiconductor NM5, NM7 respectively; The source electrode of N type metal-oxide-semiconductor NM4 connects the drain electrode of N type metal-oxide-semiconductor NM6, NM8 respectively; The source electrode of N type metal-oxide-semiconductor NM5, NM6, NM7, NM8, NM9, NM10 connects ground connection respectively, and N type metal-oxide-semiconductor NM9 drain electrode constitutes first output terminal of load current mirror transmission output stage, and N type metal-oxide-semiconductor NM10 drain electrode constitutes second output terminal of load current mirror transmission output stage.

With respect to traditional LDO; The present invention is through adopting OTA based on the high-speed, high precision of self-adaptation nonlinear current mirror, second level Push-Pull structure, super source class follower and the dynamic method that combines of zero compensation and miller compensation; The system stability of at first guaranteeing is wherein dynamically followed the tracks of compensation output limit, Miller capacity effect compression dominant pole and bandwidth zero point; The expansion second level time limit; Super impact damper extended power level input limit only keeps a dominant pole, system stability thereby make in the unity gain bandwidth; Secondly, because of adopting novel low-power consumption high-gain, broadband high pendulum rate OTA, add the gain-adjusted effect of Push-Pull CS in the circuit, efficiently solve traditional LDO low gain, low precision, low PSRR and the slow problem of response speed.

Description of drawings

Fig. 1 is traditional LDO system chart.

Fig. 2 is a LDO system chart of the present invention.

Fig. 3 is the high-speed, high precision OTA circuit that the present invention adopted.

Fig. 4 is integrated circuit figure of the present invention.

Fig. 5 is the gain phase curve figure under the 5V heavy duty situation.

Fig. 6 is the gain phase curve figure under the 5V underloading situation.

Fig. 7 is 5V load lus is jumped heavy duty by underloading transient response figure.

Fig. 8 is 5V load lus is jumped underloading by heavy duty transient response figure.

Fig. 9 is the power supply rejection ratio characteristics figure of system under the 5V heavy duty situation.

Embodiment

Describe below in conjunction with the technical scheme implementation method of accompanying drawing invention:

System chart of the present invention is as shown in Figure 2, and error amplifier is a two-layer configuration, and output is leaked full swing and driven, and the high pendulum rate of input stage self-adaptation structure, output stage drive and adopt the Push-Pull structure; Because the ESR effect at zero point is not considered in compensation, ESR resistance is got 5m Ω, at C _LZero frequency under=4.7 μ F is 6.78MHz, and generally much larger than the loop unity gain bandwidth, its influence can be ignored.

The differential input stage of error amplifier adopts OTA system architecture as shown in Figure 3, has adopted the improvement structure of two pairs of self-adaptation nonlinear current mirrors, constitutes one group by M3, M5 and M9, and M4, M6 and M10 constitute other one group.In the situation of static small-signal operation, two pairs of current mirrors are as linear current source, and the shunting action of M7/M8 has improved the small-signal gain of error amplifier; Under dynamic large signal operation situation, M5 or M6 get into linear zone, and its source-drain current is approximately the tail current of MA1, make M9 or M10 under large-signal conditions, flow through bigger electric current like this, and corresponding large-signal output pendulum rate also is improved.Solved the contradiction between high pendulum rate of traditional error amplifier and the little gain (big electric current).

The second level of error amplifier adopts Push-Pull to recommend common source (CS) gaining structure of driving, in order to improve the gain of error amplifier (EA), improves system power supply rejection ratio (PSRR) performance.But second level gain stage has increased a low-frequency pole newly, needs increase to compensate a corresponding zero point more.Circuit adopts the miller compensation structure to eliminate the influence of this low-frequency pole; Simultaneously, for further reducing the output impedance of voltage buffer stage, adopt the voltage buffer stage of negative feedback structure, thereby isolate high output resistance of error amplifier and the big stray capacitance of power tube better.Like Fig. 2 and shown in Figure 4; Adopt the super source class follower configuration that constitutes by MBF1, MBF2, MBF3 and MBF4 the third level; The output impedance of this type of follower is lower than the output impedance that tradition is total to the drain voltage follower; The pole frequency that produces with the big input capacitance of adjustment tube grid is pushed to high band, has reduced the influence to system bandwidth.

Can be known that by Fig. 2 and Fig. 4 system comprises 4 limits and 1 ESR zero point before the compensation, wherein the low frequency dominant pole frequency of first order error amplifier does

$P_{\mathrm{OTA}}=\frac{1}{r_1{C}_1}---\left(2\right)$

The low frequency pole frequency of Push-Pull amplifier does

$P_{\mathrm{pushpull}}=\frac{1}{r_2{C}_2}---\left(3\right)$

Voltage follower is that the high frequency poles frequency of impact damper output is:

$P_{\mathrm{buffer}}=\frac{1}{r_3{C}_3}---\left(4\right)$

The LDO output stage with the pole frequency of load variations is:

$P_{\mathrm{out}}=\frac{1}{R_L{C}_L}---\left(5\right)$

ESR high frequency zero frequency is:

$Z_{\mathrm{esr}}=\frac{1}{R_{\mathrm{ESR}}{C}_L}---\left(6\right)$

Follow with device P owing to adopt super source class _BufferOutside GBW, Resr=5m Ω, the Zesr of generation is also outside GBW.At this moment, 3 limits are arranged in the GBW.Add building-out capacitor C _C1, C _C2Behind Mc1, the system zero limit is:

$P_{\mathrm{OTA}}=\frac{1}{r_1(\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="HDA0000040212300000042.png"\; state="\{\{state\}\}">C</figure-callout>}1+{{\mathrm{<figure-callout\; id="1"\; label="C\; C"\; filenames="HDA0000040212300000042.png"\; state="\{\{state\}\}">C</figure-callout>}}_C}^{\&prime;})}\&ap;\frac{1}{r_1{A}_m{A}_{V2}{C}_{C1}}---\left(7\right)$

A in the formula _mBe the voltage gain of current detection circuit under the electric current linear transfer, AV2 is a time utmost point CS yield value, that is:

$A_m=\frac{g_{{\mathrm{mM}}_{C2}}}{{\mathrm{<figure-callout\; id="3"\; label="g\; mM\; C"\; filenames="HDA0000040212300000022.png"\; state="\{\{state\}\}">g</figure-callout>}}_{{\mathrm{mM}}_C}}\&times;\frac{g_{{\mathrm{mM}}_{C4}}}{{\mathrm{<figure-callout\; id="1"\; label="g\; mM\; C"\; filenames="HDA0000040212300000042.png"\; state="\{\{state\}\}">g</figure-callout>}}_{{\mathrm{mM}}_C}}\&ap;\sqrt{\frac{{(W/L)}_{\mathrm{MC}2}}{{(W/L)}_{\mathrm{<figure-callout\; id="3"\; label="MC"\; filenames="HDA0000040212300000022.png"\; state="\{\{state\}\}">MC</figure-callout>}3}}\&times;\frac{{(W/L)}_{\mathrm{MC}4}}{{(W/L)}_{\mathrm{MC}1}}}---\left(8\right)$

Under the effect of Miller capacity effect, Push-Pull amplifier pole frequency is P _Pushpull≈ g _M2/ C _C2, C wherein _C2≈ 0.6pF, dynamically zero frequency is approximately:

$Z_c=\frac{g_{\mathrm{mcl}}}{C_{C1}}---\left(9\right)$

Constitute dynamic zero compensation circuit by Mc1～Mc4 and Cc1, utilize the variation of the relation track output terminal limit of the Mc1 Diode tube impedance 1/gm be operated in the saturation region and output current.The tracking output limit that is operated in the linear zone metal-oxide-semiconductor than traditional utilization is technological, and the tracking compensation effect that the saturation region state is provided with is better.If power tube all is operated in the saturation region under all load current condition, the output terminal limit is with the load current linear change so.Show through simulating, verifying, if the Mc1 pipe is operated in zone of saturation, g _Mc1∝ (I _o) ^1/2After getting into subthreshold region, g _Mc1∝ I _o, control capacittance C _C1With the sampling coefficient of load current, make dynamic zero point Zc can in GBW, follow the tracks of LDO output limit; Simultaneously because C _C1Miller effect, the low-frequency pole of original Push-Pull amplifier stage is become a high frequency poles, release outside the bandwidth, current detection circuit has been eliminated feedforward, so RHP is cancelled zero point.Add little capacitor C _C2Be because source follower can produce complex pole under high frequency and different loads situation, on the gain-frequency characterisitic curve, produce spike, before follower, add this electric capacity and can eliminate this spike, help the stable of holding circuit.Table 1 has provided the situation of change at dynamic zero point when load current changes, and reflects the tracking performance of dynamic zero point to LDO output limit with this.

Follow the tracks of situation dynamic zero point when table 1, different loads

?I load(mA)	The compensating pipe mutual conductance	Dynamically zero point theoretical value	Simulation value
				200	3.0μ	104KHz	100KHz
100	2.2μ	76KHz	71KHz
				50	1.6μ	55KHz	53KHz
25	1.2μ	42KHz	40KHz
				10	804n	27.7KHz	27.2KHz
5	586n	20.3KHz	19.9KHz

1	245n	8.5KHz	8.4KHz
				0.1	51n	1.8KHz	1.8KHz
0	4.8n	166Hz	164Hz

Last table explanation can change with load current this zero point, is not linear but change, because the Mc1 pipe is in the saturation region all the time, the mutual conductance gm and the electric current of saturation region are not linear relationship.When load current reduces the electric current make the induction of Mc1 pipe when very little, dynamically induction tube will get into sub-threshold region, and the linearity improves, but effective following range is very little.Consider wide dynamic range requirement, in most of electric current variation range that watt current is followed the tracks of, induction tube is arranged on the strong inversion saturation region, can satisfy stability requirement this dynamic zero point.

The present invention adopts CSMC0.5 μ m standard CMOS process design, carries out simulating, verifying through the eda tool of Cadence, and the LDO input voltage of invention is 3.5V-5V; Output 3.3V; Quiescent current 40 μ A, voltage difference is 200mV under the 200mA load current condition providing, when load transient changes maximum output voltage to cross when being punched in the 5V supply voltage be 16mV, when the 3.5V supply voltage, be 30mV; Load regulation and line regulation are respectively 0.009%/A and 0.012%/V; Being 102dB during the PSRR low frequency, is 97dB during 10kHz, is 58dB during 1MHz.

Power adjustment pipe is usually operated at the linear resistance district under the low pressure differential condition, have:

$I_{\mathrm{SD}}=\frac{k_p^{\&prime;}}{2}(W/L)[2(V_{\mathrm{SG}}-V_{\mathrm{TP}})V_{\mathrm{SD}}-V_{\mathrm{SD}}^2]---\left(10\right)$

Work as V _SG-V _TP＞＞V _SD, pipe is in degree of depth linear zone, and formula can be reduced to:

I _SD≈k′ _p(W/L)(V _SG-V _TP)V _SD (11)

Conducting resistance Ron is:

$R_{\mathrm{on}}\&ap;\frac{1}{k_p^{\&prime;}(W/L)}\frac{1}{V_{\mathrm{SG}}-V_{\mathrm{TP}}}---\left(12\right)$

Then breadth length ratio is:

${\left(\frac{W}{L}\right)}_{\mathrm{Mp}}=\frac{1}{k_p^{\&prime;}{R}_{\mathrm{on}}}\frac{1}{V_{\mathrm{SG}}-V_{\mathrm{TP}}}---\left(13\right)$

By maximum current 200mA, minimum differntial pressure 200mV gets R _On≈ 1 Ω.If the V of MA16 pipe _DS≈ 200mV, then V _SGBe 3.5-(0.95+0.2+0.2) ≈ 2.15V.The breadth length ratio that obtains thus is about 13K, after ghost effect and certain surplus are considered in debugging repeatedly, the power tube breadth length ratio is decided to be 30K.

As shown in Figure 4, error amplifier is recommended output (MA15, MA16) formation by the OTA and the one-level of a high pendulum rate, and MBF1-MBF4 constitutes super source follower, and MDBF is a dynamic bias.Mc2, Mc3, Mc4 are current sampling circuit.Mc1 is a compensating pipe, and Cc1 and Cc2 are building-out capacitor.

The design of induction current detection and compensating circuit: power taking stream detector tube Mc2 is 1/20000 with the breadth length ratio of adjustment pipe; Mc2 all flows through the electric current of 10 μ A under heavy duty like this; Mc4 is again by 1/5 sampling, so Mc3 gets and MA11, W/L that MA12 is identical, and Mc4 is 1/5 of Mc3.Under the underloading condition of 1mA, the induction branch current drops to 10nA and 2nA, and each responds to metal-oxide-semiconductor must get into sub-threshold region.Therefore heavy duty is the saturation region down, then gets into sub-threshold region near unloaded underloading.Mc1 should keep the state variation with its excess-three pipe near-synchronous, considers the needs of compensation simultaneously, suitably reduces W/L, increases resistance, alleviates C _C1 excessive demand.

Through circuit simulation, the gain phase curve of the LDO of invention such as Fig. 5, shown in Figure 6, transient response such as Fig. 7, shown in Figure 8, the power supply rejection ratio characteristics curve of system is as shown in Figure 9.

Can obtain the design's Specifeca tion speeification through above-mentioned emulation; And the design and relevant design compared; As shown in table 3; Wherein the 3rd classify the design as Specifeca tion speeification, first classifies the performance parameter that people such as Mohammad Al-Shyoukh adopts miller compensation and the design of buffer stage output impedance decay technique as, second classifies people such as Yi Wang as adopts the nested type Miller compensation to add the performance parameter of transient response intensifier circuit design.But owe all to improve significantly in line regulation, load regulation, transient response overshoot voltage, transient response towards aspects such as voltage and PSRR PSRR through the invention of contrast knowledge capital.

Table 2LDO performance gathers and compares

Claims (2)

1. one kind based on the high-precision high-speed LDO circuit of putting on the rate error amplifier; It is characterized in that comprising OTA circuit (1), second level push-pull output circuit (2), miller compensation and dynamic zero compensation circuit (3), load current detection circuit (4), super source class follower (5), dynamic bias pipe (6), feedback network (7) and output and load circuit; The output terminal of OTA circuit (1) connects the input end of second level push-pull output circuit (2) and miller compensation and dynamic zero compensation circuit (3) respectively; The input end of the super source class follower of the output termination of second level push-pull output circuit (2) (5); The input end of the miller compensation and the output termination load current detection circuit (4) of dynamic zero compensation circuit (3); Super source class follower (5) output terminal connects grid and drain electrode, the output terminal of load current detection circuit (4) and the input end of output and load circuit of dynamic bias pipe (6) respectively; The input end of the output termination feedback network (7) of output and load circuit; OTA circuit (1), second level push-pull output circuit (2), miller compensation and dynamic zero compensation circuit (3), load current detection circuit (4), super source class follower (5), dynamic bias pipe (6) and output and load circuit be external power source altogether, and OTA circuit (1), second level push-pull output circuit (2), load current detection circuit (4), super source class follower (5), feedback network (7) are connected with output and load circuit altogether.

2. according to claim 1 a kind of based on the high-precision high-speed LDO circuit of putting on the rate error amplifier, it is characterized in that said OTA circuit (1) comprises tail current source (101), input difference to (102) and load current mirror (103),

Wherein load current mirror transmission output stage is made up of eight N type metal-oxide-semiconductor NM3 to NM10; The drain electrode of N type metal-oxide-semiconductor NM3 connects output terminal and N type metal-oxide-semiconductor NM5, the NM8 of differential input stage, the grid of NM9 respectively; The drain electrode of N type metal-oxide-semiconductor NM4 connects another output terminal and N type metal-oxide-semiconductor NM6, the NM7 of differential input stage, the grid of NM10 respectively; The source electrode of N type metal-oxide-semiconductor NM3 connects the drain electrode of N type metal-oxide-semiconductor NM5, NM7 respectively; The source electrode of N type metal-oxide-semiconductor NM4 connects the drain electrode of N type metal-oxide-semiconductor NM6, NM8 respectively; The source electrode of N type metal-oxide-semiconductor NM5, NM6, NM7, NM8, NM9, NM10 connects ground connection respectively, and N type metal-oxide-semiconductor NM9 drain electrode constitutes first output terminal of load current mirror transmission output stage, and N type metal-oxide-semiconductor NM10 drain electrode constitutes second output terminal of load current mirror transmission output stage.

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