CN103838290B - Ldo circuit - Google Patents
Ldo circuit Download PDFInfo
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- CN103838290B CN103838290B CN201410098539.5A CN201410098539A CN103838290B CN 103838290 B CN103838290 B CN 103838290B CN 201410098539 A CN201410098539 A CN 201410098539A CN 103838290 B CN103838290 B CN 103838290B
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Abstract
The invention provides a kind of LDO circuit, described LDO circuit includes: difference amplifier, power output PMOS transistor, current lens unit, the first resistance and the second resistance；Wherein, described first resistance and the second resistant series are between drain electrode and the ground of described power output PMOS transistor, the positive input of described difference amplifier is connected between described first resistance and the second resistance, grid all outfans with described difference amplifier of described current lens unit and described power output PMOS transistor are connected, the drain electrode of described power output PMOS transistor is connected with described first resistance, secondary nodal point is formed between drain electrode and described first resistance of described power output PMOS transistor, described secondary nodal point is connected with the outfan of described LDO circuit.In the LDO circuit that the present invention provides, zero point can be orthokinetic with the second limit when load current changes to make described LDO circuit by increase current lens unit, thereby guarantees that the stability of described LDO circuit.
Description
Technical field
The present invention relates to linear voltage regulator technical field, particularly to a kind of LDO circuit.
Background technology
Low pressure difference linear voltage regulator (lowdropoutregulator is called for short LDO) can produce the output voltage through overregulating provides power supply for chip, is now widely used in system level chip (System-on-a-Chip is called for short SoC).Low pressure difference linear voltage regulator can be divided into plain edition LDO circuit and without capacitor type LDO circuit (capacitorlessLDO) according to it the need of shunt capacitance, plain edition LDO circuit is it is generally required to one or two shunt capacitance, and typically need not shunt capacitance without capacitor type LDO circuit.Traditional capacitorlessLDO circuit is typically made up of parts such as difference amplifier, power MOS pipe and resistance, and the feedback circuit of difference amplifier, power MOS pipe and resistance composition is used for keeping stablizing of output voltage.Common, traditional LDO circuit also includes that the compensation resistance for realizing compensation effect and Miller capacitance are to ensure the stability of LDO circuit.
Refer to Fig. 1, it is the structural representation of capacitorlessLDO circuit of prior art.nullAs shown in Figure 1，Existing capacitorlessLDO circuit 100 includes difference amplifier A1、Power output PMOS transistor mp10、Compensate resistance Rm1、Miller capacitance Cc1、Feedback resistance R11 and R12，Wherein，The source electrode of power output PMOS transistor mp10 is connected with supply voltage VDD，Feedback resistance R11 and R12 is connected between drain electrode and the ground of power output PMOS transistor mp10，The reverse input end of difference amplifier A1 connects a reference voltage Vref，The positive input of difference amplifier A1 is connected between described feedback resistance R11 and R12，The outfan of difference amplifier A1 is connected with the grid of power output PMOS transistor mp10，The drain electrode of power output PMOS transistor mp10 is connected with feedback resistance R11，Secondary nodal point N2 is formed between drain electrode and the feedback resistance R11 of power output PMOS transistor mp10，Compensate resistance Rm1 and Miller capacitance Cc1 is serially connected and between described secondary nodal point N2 and the outfan of difference amplifier A1，Described secondary nodal point N2 is connected with the outfan of described capacitorlessLDO circuit 100，The outfan of described capacitorlessLDO circuit 100 is generally connected with load capacitance CL1，The capacitance of described load capacitance CL1 can be 0.
The operation principle of described capacitorlessLDO circuit 100 is as follows: capacitorlessLDO circuit 100 produces output voltage VO UT according to the reference voltage Vref of input, output voltage VO UT after feedback resistance R11 and R12 dividing potential drop for difference amplifier A1 input in the same direction provide feedback voltage V FB, the expression formula of described feedback voltage V FB is:
VFB=(R12 ÷ (R11+R12)) × VOUT；
Reference voltage Vref and feedback voltage V FB are compared after obtaining difference DELTA V and difference DELTA V being amplified and obtain Δ Vmax by difference amplifier A1, Δ Vmax is for driving the grid of described power output PMOS transistor mp10, thus change the electric current by power output PMOS transistor mp10, make reference voltage Vref and feedback voltage V FB approximately equal, and then make the magnitude of voltage of output voltage VO UT tend to constant.
But, described capacitorlessLDO circuit 100 finds in application process, its unstable properties when load current occurs bigger change.The reason of described capacitorlessLDO circuit 100 unstable properties is, when load current occurs bigger change, the zero point of described capacitorlessLDO circuit 100 is not along with the second limit is orthokinetic, owing to zero point could not well follow the tracks of the change of the second limit, therefore harmful effect is caused for stability.As shown in Figure 1, when load current occurs bigger change the second limit will be moved to high frequency by low frequency, and the zero point of described capacitorlessLDO circuit 100 does not change, therefore, the second limit is made the bad stability of described capacitorlessLDO circuit 100 by low-frequency transfer to high frequency.If load current was increased dramatically in moment, the normal work of described capacitorlessLDO circuit 100 can be directly affected.
Therefore, how to solve existing capacitorlessLDO circuit problem of unstable properties when load current drastically changes to become currently to need badly and solve the technical problem that.
Summary of the invention
It is an object of the invention to provide a kind of LDO circuit, to solve existing capacitorlessLDO circuit problem of unstable properties when load current drastically changes.
For solving above-mentioned technical problem, the present invention provides a kind of LDO circuit, and described LDO circuit includes: difference amplifier, power output PMOS transistor, current lens unit, the first resistance and the second resistance；
Wherein, described first resistance and the second resistant series are between drain electrode and the ground of described power output PMOS transistor, the positive input of described difference amplifier is connected between described first resistance and the second resistance, grid all outfans with described difference amplifier of described current lens unit and described power output PMOS transistor are connected, the drain electrode of described power output PMOS transistor is connected with described first resistance, secondary nodal point is formed between drain electrode and described first resistance of described power output PMOS transistor, described secondary nodal point is connected with the outfan of described LDO circuit.
Preferably, in described LDO circuit, described current lens unit includes the first PMOS transistor, the second PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor；
nullDescribed first PMOS transistor、The drain electrode of the grid of the 4th nmos pass transistor and the 5th nmos pass transistor and described 3rd PMOS transistor and the 5th nmos pass transistor all outfans with described difference amplifier are connected，Described first nmos pass transistor、The drain electrode of the second nmos pass transistor and the grid of the 3rd nmos pass transistor and described first nmos pass transistor all drain electrodes with described first PMOS transistor are connected，Described first nmos pass transistor、Second nmos pass transistor and the source grounding of the 3rd nmos pass transistor，The drain electrode of described second PMOS transistor and the grid of the 3rd PMOS transistor and described second PMOS transistor all drain electrodes with described 4th nmos pass transistor are connected，The drain electrode of described second nmos pass transistor is connected with the source electrode of described 4th nmos pass transistor，The drain electrode of described 3rd nmos pass transistor is connected with the source electrode of described 5th nmos pass transistor.
Preferably, in described LDO circuit, the size of described first nmos pass transistor, the second nmos pass transistor and the 3rd nmos pass transistor is the most equal.
Preferably, in described LDO circuit, described 4th nmos pass transistor and the 5th nmos pass transistor equal sized, described second PMOS transistor and the 3rd PMOS transistor equal sized.
Preferably, in described LDO circuit, also include: compensate resistance and Miller capacitance；
Described compensation resistance and Miller capacitance are connected and between the outfan of described secondary nodal point and described difference amplifier；
Primary nodal point is formed between grid and the described compensation resistance of described power output PMOS transistor.
Preferably, in described LDO circuit, described compensation resistance is in parallel with described 5th nmos pass transistor.
Preferably, in described LDO circuit, the reverse input end of described difference amplifier connects a reference voltage, and the source electrode of described power output PMOS transistor, the first PMOS transistor, the second PMOS transistor and the 3rd PMOS transistor is all connected with a supply voltage.
Preferably, in described LDO circuit, described LDO circuit is without capacitor type LDO circuit.
In the LDO circuit that the present invention provides, zero point can be orthokinetic with the second limit when load current changes to make described LDO circuit by increase current lens unit, thereby guarantees that the stability of described LDO circuit.
Accompanying drawing explanation
Fig. 1 is the structural representation of the capacitorlessLDO circuit of prior art；
Fig. 2 is the structural representation of the LDO circuit of the embodiment of the present invention.
Detailed description of the invention
The LDO circuit proposed the present invention below in conjunction with the drawings and specific embodiments is described in further detail.According to following explanation and claims, advantages and features of the invention will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non-ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
Refer to Fig. 2, it is the structural representation of LDO circuit of the embodiment of the present invention.nullAs shown in Figure 2，Described LDO circuit 200 includes: difference amplifier A2、Power output PMOS transistor mp20、Current lens unit 20、First resistance R21 and the second resistance R22，Wherein，Described first resistance R21 and the second resistance R22 is series between drain electrode and the ground of described power output PMOS transistor mp20，The positive input of described difference amplifier A2 is connected between described first resistance R21 and the second resistance R22，Grid all outfans with described difference amplifier A2 of described current lens unit 20 and described power output PMOS transistor mp20 are connected，The drain electrode of described power output PMOS transistor mp20 is connected with described first resistance R21，Secondary nodal point Q2 is formed between drain electrode and the described first resistance R21 of described power output PMOS transistor mp20，Described secondary nodal point Q2 is connected with the outfan of described LDO circuit 200.
nullConcrete，Described current lens unit 20 includes 5 nmos pass transistors and 3 PMOS transistor，In described 5 nmos pass transistors and 3 PMOS transistor，First PMOS transistor mp1、The drain electrode of the 4th nmos pass transistor mn4 and the grid of the 5th nmos pass transistor mn5 and the 3rd PMOS transistor mp3 and the 5th nmos pass transistor mn5 all outfans with described difference amplifier A2 are connected，First nmos pass transistor mn1、The drain electrode of the second nmos pass transistor mn2 and the grid of the 3rd nmos pass transistor mn3 and the first nmos pass transistor mn1 all drain electrodes with the first PMOS transistor mp1 are connected，First nmos pass transistor mn1、Second nmos pass transistor mn2 and the source grounding of the 3rd nmos pass transistor mn3，The drain electrode of the second PMOS transistor mp2 and the grid of the 3rd PMOS transistor mp3 and the second PMOS transistor mp2 all drain electrodes with the 4th nmos pass transistor mn4 are connected，The drain electrode of the second nmos pass transistor mn2 is connected with the source electrode of the 4th nmos pass transistor mn4，The drain electrode of the 3rd nmos pass transistor mn3 and the source electrode of the 5th nmos pass transistor mn5 connect.
Described current lens unit 20 includes reference arm, the first output branch road and the second output branch road, described reference arm includes the first nmos pass transistor mn1 and the first PMOS transistor mp1, first output branch road includes that the second PMOS transistor mp2, the second nmos pass transistor mn2 and the 4th nmos pass transistor mn4, the second output branch road include the 3rd PMOS transistor mp3, the 3rd nmos pass transistor mn3 and the 5th nmos pass transistor mn5.
Wherein, first nmos pass transistor mn1, the second nmos pass transistor mn2 and the 3rd nmos pass transistor mn3 size the most equal, 4th nmos pass transistor mn4's and the 5th nmos pass transistor mn5 is equal sized, the second PMOS transistor mp2 and the 3rd PMOS transistor mp3 equal sized.Visible, in described current lens unit 20, the first output branch road and the second output branch structure are symmetrical.
Owing to the grid of the first nmos pass transistor mn1, the second nmos pass transistor mn2 and the 3rd nmos pass transistor mn3 is connected, the grid voltage of the first nmos pass transistor mn1, the second nmos pass transistor mn2 and the 3rd nmos pass transistor is identical, simultaneously because the first nmos pass transistor mn1, the second nmos pass transistor mn2's and the 3rd nmos pass transistor mn3 is equivalently-sized, therefore the first electric current I1, the second electric current I2 and the 3rd electric current I3 are equal.
Please continue to refer to Fig. 2, described LDO circuit 200 also includes compensating resistance Rm2 and Miller capacitance Cc2, described compensation resistance Rm2 and Miller capacitance Cc2 are serially connected, primary nodal point Q1 is formed between grid and the compensation resistance Rm2 of power output PMOS transistor mp20, forming secondary nodal point Q2 between drain electrode and the first resistance R21 of power output PMOS transistor mp20, described compensation resistance Rm2 and Miller capacitance Cc2 are between described secondary nodal point Q2 and the outfan of difference amplifier A2.Wherein, described compensation resistance Rm2 and the 5th nmos pass transistor mn5 is in parallel.
In the present embodiment, described LDO circuit 200 is to connect without capacitor type LDO circuit (capacitorlessLDO), the outfan of described LDO circuit 200 and load capacitance CL2, and the capacitance of described load capacitance CL2 can be 0.
When described LDO circuit 200 works, the reverse input end input reference voltage Vref of difference amplifier A2, the equal input supply voltage VDD of the source electrode of power output PMOS transistor mp20, the first PMOS transistor mp1, the second PMOS transistor mp2 and the 3rd PMOS transistor mp3.
The operation principle of described LDO circuit 200 is as follows: LDO circuit 200 produces output voltage VO UT according to reference voltage Vref, output voltage VO UT after the first resistance R21 and the second resistance R22 dividing potential drop for difference amplifier A2 input in the same direction provide feedback voltage V FB, the expression formula of feedback voltage V FB is:
VFB=(R22 ÷ (R21+R22)) × VOUT；
Reference voltage Vref and feedback voltage V FB are compared after obtaining difference DELTA V and difference DELTA V being amplified and obtain Δ Vmax by difference amplifier A2, Δ Vmax is for driving the grid of power output PMOS transistor mp20, thus change the electric current by power output PMOS transistor mp20, make reference voltage Vref and feedback voltage V FB approximately equal, and then make the magnitude of voltage of output voltage VO UT tend to constant.
When the load current of described LDO circuit 200 rises, the second limit is moved to high frequency by low frequency.Meanwhile, the voltage Vg of primary nodal point Q1 declines, Vg decline makes the grid voltage of the first PMOS transistor mp1 decline, so that the first electric current I1 of described current lens unit 20 increases, the second electric current I2 and the 3rd electric current I3 increases to equal with the first electric current I1 the most therewith.3rd electric current I3 increases, it is meant that the resistance of the 5th nmos pass transistor mn5 drain-to-source diminishes, and compensates resistance Rm2 and the 5th nmos pass transistor mn5 parallel resistance diminishes the most therewith.Therefore, the zero point of described LDO circuit 200 is also to high-frequency mobile, zero point and the orthokinetic stability that ensure that described LDO circuit 200 of the second limit.
To sum up, in the LDO circuit that the embodiment of the present invention provides, zero point can be orthokinetic with the second limit when load current changes to make described LDO circuit by increase current lens unit, ensure that described LDO circuit also is able to steady operation when load current changes, even if load current was increased dramatically in moment, do not interfere with the normal work of described LDO circuit yet.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, any change that the those of ordinary skill in field of the present invention does according to the disclosure above content, modification, belongs to the protection domain of claims.
Claims (7)
1. a LDO circuit, it is characterised in that including: difference amplifier, power output PMOS transistor, current lens unit, the first resistance and the second resistance；
Wherein, described first resistance and the second resistant series are between drain electrode and the ground of described power output PMOS transistor, the positive input of described difference amplifier is connected between described first resistance and the second resistance, grid all outfans with described difference amplifier of described current lens unit and described power output PMOS transistor are connected, the drain electrode of described power output PMOS transistor is connected with described first resistance, secondary nodal point is formed between drain electrode and described first resistance of described power output PMOS transistor, described secondary nodal point is connected with the outfan of described LDO circuit；
Described current lens unit includes the first PMOS transistor, the second PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor；nullDescribed first PMOS transistor、The drain electrode of the grid of the 4th nmos pass transistor and the 5th nmos pass transistor and described 3rd PMOS transistor and the 5th nmos pass transistor all outfans with described difference amplifier are connected，Described first nmos pass transistor、The drain electrode of the second nmos pass transistor and the grid of the 3rd nmos pass transistor and described first nmos pass transistor all drain electrodes with described first PMOS transistor are connected，Described first nmos pass transistor、Second nmos pass transistor and the source grounding of the 3rd nmos pass transistor，The drain electrode of described second PMOS transistor and the grid of the 3rd PMOS transistor and described second PMOS transistor all drain electrodes with described 4th nmos pass transistor are connected，The drain electrode of described second nmos pass transistor is connected with the source electrode of described 4th nmos pass transistor，The drain electrode of described 3rd nmos pass transistor is connected with the source electrode of described 5th nmos pass transistor；Described current lens unit makes described LDO circuit, and when load current changes, zero point can be orthokinetic with the second limit, it is ensured that the stability of described LDO circuit.
2. LDO circuit as claimed in claim 1, it is characterised in that the size of described first nmos pass transistor, the second nmos pass transistor and the 3rd nmos pass transistor is the most equal.
3. LDO circuit as claimed in claim 1, it is characterised in that described 4th nmos pass transistor and the 5th nmos pass transistor equal sized, described second PMOS transistor and the 3rd PMOS transistor equal sized.
4. LDO circuit as claimed in claim 1, it is characterised in that also include: compensate resistance and Miller capacitance；
Described compensation resistance and Miller capacitance are connected and between the outfan of described secondary nodal point and described difference amplifier；
Primary nodal point is formed between grid and the described compensation resistance of described power output PMOS transistor.
5. LDO circuit as claimed in claim 4, it is characterised in that described compensation resistance is in parallel with described 5th nmos pass transistor.
6. LDO circuit as claimed in claim 5, it is characterized in that, the reverse input end of described difference amplifier connects a reference voltage, and the source electrode of described power output PMOS transistor, the first PMOS transistor, the second PMOS transistor and the 3rd PMOS transistor is all connected with a supply voltage.
7. LDO circuit as claimed in claim 1, it is characterised in that described LDO circuit is without capacitor type LDO circuit.
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| CN201410098539.5A CN103838290B (en) | 2014-03-17 | 2014-03-17 | Ldo circuit |
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| CN201410098539.5A CN103838290B (en) | 2014-03-17 | 2014-03-17 | Ldo circuit |
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| CN103838290B true CN103838290B (en) | 2016-08-03 |
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| CN104820459A (en) * | 2015-03-18 | 2015-08-05 | 北京兆易创新科技股份有限公司 | LDO circuit |
| CN104734498B (en) * | 2015-04-13 | 2017-03-29 | 无锡新硅微电子有限公司 | DC DC boost modules |
| ITUB20151005A1 (en) | 2015-05-27 | 2016-11-27 | St Microelectronics Srl | VOLTAGE REGULATOR WITH IMPROVED ELECTRICAL CHARACTERISTICS AND CORRESPONDING CONTROL METHOD |
| CN104950974B (en) | 2015-06-30 | 2017-05-31 | 华为技术有限公司 | Low pressure difference linear voltage regulator and the method and phaselocked loop that increase its stability |
| IT201600088370A1 (en) * | 2016-08-31 | 2018-03-03 | St Microelectronics Srl | CIRCUIT WITH MILLER COMPENSATION, REGULATOR, CORRESPONDENT SYSTEM AND PROCEDURE |
| EP3511796B1 (en) | 2018-01-15 | 2021-06-30 | Nxp B.V. | A linear regulator with a common resistance |
| US10338614B1 (en) * | 2018-04-24 | 2019-07-02 | Analog Devices, Inc. | Low dropout linear regulator with internally compensated effective series resistance |
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| CN113342108B (en) * | 2021-06-08 | 2022-09-06 | 成都华微电子科技股份有限公司 | Parallel operational amplifier zero compensation circuit |
| CN114167938B (en) * | 2021-10-12 | 2023-04-14 | 广东赛微微电子股份有限公司 | Power management chip, linear voltage stabilizing circuit and bias current compensation method thereof |
| CN115113681B (en) * | 2022-07-22 | 2023-04-28 | 北京智芯微电子科技有限公司 | Load adjustment rate compensation circuit, voltage stabilizing circuit, device and chip |
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