CN103713682B - Low pressure difference linear voltage regulator - Google Patents
Low pressure difference linear voltage regulator Download PDFInfo
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- CN103713682B CN103713682B CN201410010118.2A CN201410010118A CN103713682B CN 103713682 B CN103713682 B CN 103713682B CN 201410010118 A CN201410010118 A CN 201410010118A CN 103713682 B CN103713682 B CN 103713682B
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Abstract
The present invention discloses a kind of low pressure difference linear voltage regulator, except comprising error amplifier, Correctional tube, outside sample circuit and a miller capacitance, this low pressure difference linear voltage regulator also comprises a cathode-input amplifier, this cathode-input amplifier is arranged between this miller capacitance and this Correctional tube grid, this miller capacitance is connected to this cathode-input amplifier and this Correctional tube drains, this cathode-input amplifier feeds back to error amplifier output by after the Sample buffer of miller capacitance, while reaching primary and secondary limit separation object, the grid of miller capacitance and Correctional tube is isolated by impact damper, thus reach the object increasing circuit stability and improve PSRR.
Description
Technical field
The present invention, about a kind of low pressure difference linear voltage regulator (LDO, Low Dropout Regulator), particularly relates to the low pressure difference linear voltage regulator that a kind of stability is high, PSRR is higher.
Background technology
Recently, increasing occasion needs to use LDO(low pressure difference linear voltage regulator) to chip power supply.In on-chip system chip, more extensive to the demand without electric capacity LDO, when designing without electric capacity LDO, exchanging stability is a very important performance.
Fig. 1 is the circuit diagram of traditional LDO.As shown in Figure 1, traditional LDO comprises an error amplifier, Correctional tube mpd and sample circuit, the differential pair of the error amplifying circuit be made up of NMOS tube mn1 and mn2, this differential pair source electrode connects bias current sources, PMOS mp1 and mp2 forms mirror current source, it is as the active load of differential pair, one of error amplifier input end (mn2 grid) meets reference voltage VREF, its another input end (mn1 grid) connects the sampling of output voltage VO UT, sampled voltage exports from mn2 drain electrode after error amplifier amplifies, this error amplifies the input end (mpd grid) exporting and be sent to Correctional tube mpd, simultaneously mn2 drain electrode to be drained with Correctional tube mpd by a miller capacitance Cc and is connected, Correctional tube mpd drains and exports voltage of voltage regulation VOUT, this VOUT delivers to one of error amplifier input end (grid of mn1) after the electric resistance partial pressure sampling of sample circuit R1/R2, if it is higher to export VOUT, then sampled voltage is higher, the error of error amplifier exports and increases, because PMOS mp1 adopts diode-connected, therefore PMOS mp1 drain electrode and NMOS tube mn1 drain voltage are certain, under the inverting function of differential pair, NMOS tube mn2 drain voltage raises, so Correctional tube mpd grid voltage raises, Correctional tube mpd drain voltage and VOUT decline, and vice versa.In traditional LDO, the stability dependency of circuit is in the miller capacitance Cc increased, but the access of miller capacitance Cc is to PSRR(Power Supply Rejection Ratio, Power Supply Rejection Ratio) deterioration serious.
Summary of the invention
For overcoming above-mentioned prior art Problems existing, fundamental purpose of the present invention is to provide a kind of low pressure difference linear voltage regulator, it by increasing by a cathode-input amplifier between error amplifier and output circuit, this cathode-input amplifier feeds back to error amplifier output by after the Sample buffer of miller capacitance, to reach the object of primary and secondary limit separation simultaneously, the grid of miller capacitance and Correctional tube is isolated by a separator tube, thus reaches the object increasing circuit stability and improve PSRR.
For reaching above-mentioned purpose, the invention provides a kind of low pressure difference linear voltage regulator, comprise error amplifier, Correctional tube, sample circuit and a miller capacitance, this low pressure difference linear voltage regulator also comprises a cathode-input amplifier, this cathode-input amplifier is arranged between this miller capacitance and this Correctional tube grid, this miller capacitance is connected to this cathode-input amplifier source electrode and this Correctional tube drains, this cathode-input amplifier feeds back to this error amplifier output by after the Sample buffer of miller capacitance, to realize miller capacitance and Correctional tube gate isolation.
Further, this cathode-input amplifier comprises the 3rd NMOS tube and the first current source, 3rd NMOS tube and this first current source are connected in series between this Correctional tube grid and ground, 3rd NMOS tube source electrode connects the first current source, grid connects reference voltage, drain electrode connects the output terminal of this error amplifier, and this miller capacitance is connected between the drain electrode of this Correctional tube and the 3rd NMOS tube source electrode.
Further, this error amplifier comprises the differential pair of the first NMOS tube and the second NMOS tube composition and the mirror current source of the first PMOS and the second PMOS composition, this differential pair source electrode connects bias current sources, this first PMOS and the second PMOS form the active load of mirror current source as differential pair, this the second NMOS tube grid connects reference voltage, this the first NMOS tube grid connects the sampling of output voltage, sampled voltage exports from the second NMOS tube drain electrode after this error amplifier amplifies, this error amplifier exports the grid being sent to this Correctional tube, the drain electrode of this second NMOS tube also drains with the 3rd NMOS tube and is connected, the drain electrode of this Correctional tube exports voltage of voltage regulation, this the first NMOS tube grid is delivered to after the electric resistance partial pressure sampling of this sample circuit.
Further, this low pressure difference linear voltage regulator also comprises the second common grid offset current branch road, and this second common grid offset current branch road comprises the 4th NMOS tube and the second current source, and the 4th NMOS tube source electrode connects this second current source, grid connects reference voltage, and drain electrode connects the drain electrode of this first NMOS tube.
Further, this cathode-input amplifier and this second altogether mirror current source of forming of grid offset current branch road this first PMOS all multiplexing and this second PMOS.
Further, this first current source is equal with the second current source.
Further, this cathode-input amplifier adopts and realizes the compensation of common grid to the mode of the differential pair separation length of this error amplifier.
Further, two NMOS tube of the differential pair of this error amplifier are split into the NMOS tube of two series connection, first NMOS tube is split into NMOS tube mn11 and mn10 series connection, second NMOS tube is split into NMOS tube mn21 and mn20 series connection, this NMOS tube mn11, the voltage that mn10 grid connects this sample circuit exports, NMOS tube mn11 drain electrode connects the first PMOS drain electrode of this error amplifier, source electrode connects NMOS tube mn10 drain electrode, NMOS tube mn10 source electrode connects current source load, NMOS tube mn21, mn20 grid connects reference voltage, NMOS tube mn21 drain electrode connects the second PMOS drain electrode of this error amplifier, NMOS tube mn21 source electrode connects NMOS tube mn20 drain electrode, NMOS tube mn20 source electrode connects current source load, this miller capacitance is connected between the node of the drain electrode of this Correctional tube and this NMOS tube mn21 source electrode and this NMOS tube mn20 drain electrode formation.
Compared with prior art, a kind of low pressure difference linear voltage regulator of the present invention by increasing by a cathode-input amplifier between Correctional tube grid and miller capacitance, this cathode-input amplifier feeds back to error amplifier output by after the Sample buffer of miller capacitance, to realize miller capacitance and Correctional tube gate isolation, thus reach the object increasing circuit stability and improve PSRR.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of traditional LDO;
Fig. 2 is the circuit diagram of the first preferred embodiment of a kind of low pressure difference linear voltage regulator of the present invention;
Fig. 3 is the circuit diagram of the second preferred embodiment of a kind of low pressure difference linear voltage regulator of the present invention;
Fig. 4 PSRR that to be the present invention first preferred embodiment (method one) with all devices of prior art adopt when typical case arranges (TT), temperature 27 degrees Celsius, load current Iload=50mA, 3V export compares schematic diagram;
Fig. 5 is that the present invention second preferred embodiment (method two) adopts typical case to arrange (TT), temperature 27 degrees Celsius, load current Iload=50mA, 3V with all devices of prior art, adjustment miller capacitance is 60 degree by phase margin, the comparison schematic diagram of the PSRR of output.
Embodiment
Below by way of specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention is also implemented by other different instantiation or is applied, and the every details in this instructions also can based on different viewpoints and application, carries out various modification and change not deviating under spirit of the present invention.
A kind of low pressure difference linear voltage regulator of the present invention, between Correctional tube grid and miller capacitance, increase by a cathode-input amplifier, this cathode-input amplifier feeds back to error amplifier output by after the Sample buffer of miller capacitance, to realize miller capacitance and Correctional tube gate isolation, thus reach the object improving PSRR, increasing the method for cathode-input amplifier has following two kinds: one to be directly realize grid altogether at error amplifier output and a Correctional tube input end node P1 cathode-input amplifier in parallel to compensate, and two, be adopt the way of differential pair separation length to realize grid altogether to compensate.Below will do concrete introduction one by one.
Fig. 2 is the circuit diagram of the first preferred embodiment of a kind of low pressure difference linear voltage regulator of the present invention.As shown in Figure 2, a kind of low pressure difference linear voltage regulator of the present invention, comprising: error amplifier 20, Correctional tube mpd, cathode-input amplifier 21 and sample circuit 22.Error amplifier comprises NMOS tube mn1(first NMOS tube) and NMOS tube mn2(second NMOS tube) differential pair that forms and PMOS mp1(first PMOS) and PMOS mp2(second PMOS) mirror current source that forms, this differential pair source electrode meets bias current sources I, mp1 and mp2 forms the active load of mirror current source as differential pair, one of error amplifier 20 input end (mn2 grid) meets reference voltage VREF, its another input end (mn1 grid) connects the sampling of output voltage VO UT, sampled voltage exports from mn2 drain electrode after error amplifier amplifies, this error amplifies the input end (mpd grid) exporting and be sent to output circuit, mpd drain electrode exports voltage of voltage regulation VOUT, this VOUT delivers to one of error amplifier input end (mn1 drain electrode) after resistance (R1/R2) the dividing potential drop sampling of sample circuit 22, cathode-input amplifier 21 is connected between error amplifier 20 and Correctional tube mpd, miller capacitance Cc is connected between cathode-input amplifier 21 and Correctional tube mpd drain, this cathode-input amplifier feeds back to error amplifier output by after the Sample buffer of miller capacitance Cc, to realize miller capacitance and Correctional tube gate isolation, thus reach the object improving PSRR.In the present invention first preferred embodiment, cathode-input amplifier 21 comprises the 3rd NMOS tube mn3L and the first current source I1,3rd NMOS tube mn3L and the first current source I1 is connected in series between Correctional tube mpd grid and ground, 3rd NMOS tube mn3L source electrode meets the first current source I1, grid meets reference voltage VREF, its drain electrode connects NMOS tube mn2 drain electrode, and building-out capacitor (miller capacitance) Cc is connected between Correctional tube mpd drain electrode and mn3L source electrode.In the present invention, the 3rd NMOS tube mn3L being connected into cathode-input amplifier plays the effect of current buffer, this impact damper had both achieved primary and secondary limit and had been separated, and again by miller capacitance and Correctional tube gate isolation, therefore the present invention first preferred embodiment is to while the improvement of stability, turn improves the PSRR under high frequency.It should be noted that, for not increasing too much bias PMOS pipe, in the present invention first preferred embodiment, the mirror current source of cathode-input amplifier 21 is multiplexing mp1 and mp2 composition.
For ensureing the symmetry of circuit, in the present invention first preferred embodiment, increase by one second at the input end of error amplifier and the drain node P2 of NMOS tube mn1 and be total to grid offset current branch road 23, these second common grid compensate branch road 23 and comprise the 4th NMOS tube mn3R and the second current source I2,4th NMOS tube mn3R source electrode meets the second current source I2, grid meets reference voltage VREF, and drain electrode connects mn1 drain electrode, the second current source I2=I1.Equally, for not increasing too much bias PMOS pipe, the mirror current source of the second altogether grid offset current branch road 23 also multiplexing mp1 and mp2 composition.
Fig. 3 is the circuit diagram of the second preferred embodiment of a kind of low pressure difference linear voltage regulator of the present invention.As shown in Figure 3, in the present invention second preferred embodiment, cathode-input amplifier adopts and realizes grid compensation altogether to the way of the differential pair separation length of error amplifier.Specifically, each NMOS tube of the differential pair of error amplifier is split into the NMOS tube of two series connection, namely mn1 be split into mn11 and mn10 series connection, mn2 be split into mn21 and mn20 series connection, the voltage that mn11, mn10 grid still connects sample circuit exports, mn11 drain electrode connects mp1 drain electrode, mn11 source electrode connects mn10 drain electrode, mn10 source electrode meets current source load I, mn21, mn20 grid still meets reference voltage VREF, mn21 drain electrode connects mp2 drain electrode, mn21 source electrode connects mn20 drain electrode, and mn20 source electrode meets current source load I.Control mn11 and mn21 works in saturation region (saturation region), and building-out capacitor Cc is connected between the node of Correctional tube mpd drain electrode and mn21 source electrode and mn20 drain electrode formation.
Concerning sampling exports, mn21 forms cathode-input amplifier, and it possesses the effect of current buffer, and this impact damper had both achieved primary and secondary limit and has been separated, and again by miller capacitance and Correctional tube gate isolation.Therefore the present invention second preferred embodiment is to while the improvement of stability, turn improves the PSRR. under high frequency
It should be noted that, although in the present invention second preferred embodiment, adopt the way of differential pair separation length to realize grid altogether to compensate, but in fact the PMOS mp1/mp2 of mirror current source to be implemented separation length be also feasible, just compensate input cross from power lead close to can cause poor PSRR.
Fig. 4 PSRR that to be the present invention first preferred embodiment (method one) with all devices of prior art adopt when typical case arranges (TT), temperature 27 degrees Celsius, load current Iload=50mA, 3V export compares schematic diagram.Visible, when phase margin all gets 60 degree, the curve that the PSRR(bottom of the present invention first preferred embodiment (method one) is more sharp-pointed in all frequency ranges) be obviously better than prior art.
Fig. 5 is that the present invention second preferred embodiment (method two) adopts typical case to arrange (TT), temperature 27 degrees Celsius, load current Iload=50mA, 3V with all devices of prior art, adjustment miller capacitance is 60 degree by phase margin, the comparison schematic diagram of the PSRR exported, visible, when phase margin all gets 60 degree, the curve that the PSRR(bottom of the present invention second preferred embodiment (method two) is more sharp-pointed in all frequency ranges) be obviously better than prior art.
In sum, a kind of low pressure difference linear voltage regulator of the present invention by increasing by a cathode-input amplifier between Correctional tube grid and miller capacitance, this cathode-input amplifier will feed back to the output terminal of error amplifier after the Sample buffer of miller capacitance, be separated both to have achieved primary and secondary limit with impact damper, and again by miller capacitance and Correctional tube gate isolation, thus reach the object increasing circuit stability and improve PSRR.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (7)
1. a low pressure difference linear voltage regulator, comprise error amplifier, Correctional tube, sample circuit and a miller capacitance, it is characterized in that: this low pressure difference linear voltage regulator also comprises a cathode-input amplifier, this cathode-input amplifier is arranged between this miller capacitance and this Correctional tube grid, this cathode-input amplifier comprises the 3rd NMOS tube and the first current source, 3rd NMOS tube and this first current source are connected in series between this Correctional tube grid and ground, 3rd NMOS tube source electrode connects the first current source, grid connects reference voltage, drain electrode connects the output terminal of this error amplifier, this miller capacitance is connected between the drain electrode of this Correctional tube and the 3rd NMOS tube source electrode, this cathode-input amplifier feeds back to this error amplifier output by after the Sample buffer of miller capacitance, realize this miller capacitance and this Correctional tube gate isolation.
2. a kind of low pressure difference linear voltage regulator as claimed in claim 1, it is characterized in that: this error amplifier comprises the differential pair of the first NMOS tube and the second NMOS tube composition and the mirror current source of the first PMOS and the second PMOS composition, this differential pair source electrode connects bias current sources, this first PMOS and the second PMOS form the active load of mirror current source as differential pair, this the second NMOS tube grid connects reference voltage, this the first NMOS tube grid connects the sampling of output voltage, sampled voltage exports from the second NMOS tube drain electrode after this error amplifier amplifies, this error amplifies the grid exporting and be sent to this Correctional tube, the drain electrode of this second NMOS tube also drains with the 3rd NMOS tube and is connected, the drain electrode of this Correctional tube exports voltage of voltage regulation, this the first NMOS tube grid is delivered to after the electric resistance partial pressure sampling of this sample circuit.
3. a kind of low pressure difference linear voltage regulator as claimed in claim 2, it is characterized in that: this low pressure difference linear voltage regulator also comprises second and is total to grid offset current branch road, this second common grid offset current branch road comprises the 4th NMOS tube and the second current source, 4th NMOS tube source electrode connects this second current source, grid connects reference voltage, and drain electrode connects the drain electrode of this first NMOS tube.
4. a kind of low pressure difference linear voltage regulator as claimed in claim 3, is characterized in that: this cathode-input amplifier and this second altogether mirror current source of forming of grid offset current branch road this first PMOS all multiplexing and this second PMOS.
5. a kind of low pressure difference linear voltage regulator as claimed in claim 4, is characterized in that: this first current source is equal with the second current source.
6. a kind of low pressure difference linear voltage regulator as claimed in claim 1, is characterized in that: this cathode-input amplifier adopts and realizes the compensation of common grid to the mode of the differential pair separation length of this error amplifier.
7. a kind of low pressure difference linear voltage regulator as claimed in claim 6, it is characterized in that: two NMOS tube of the differential pair of this error amplifier are split into the NMOS tube of two series connection, first NMOS tube is split into the first sub-NMOS tube and the second sub-NMOS tube series connection, second NMOS tube is split into the 3rd sub-NMOS tube and the 4th sub-NMOS tube series connection, the voltage that this first sub-NMOS tube and this second sub-NMOS tube grid connect this sample circuit exports, this the first sub-NMOS tube drain electrode connects the first PMOS drain electrode of this error amplifier, source electrode connects this second sub-NMOS tube drain electrode, this second sub-NMOS tube source electrode connects current source load, 3rd sub-NMOS tube and the 4th sub-NMOS tube grid connect reference voltage, 3rd sub-NMOS tube drain electrode connects the second PMOS drain electrode of this error amplifier, 3rd sub-NMOS tube source electrode connects the 4th sub-NMOS tube drain electrode, 4th sub-NMOS tube source electrode connects current source load, this miller capacitance is connected between the node of the drain electrode of this Correctional tube and the 3rd sub-NMOS tube source electrode and the 4th sub-NMOS tube drain electrode formation.
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| CN201410010118.2A CN103713682B (en) | 2014-01-09 | 2014-01-09 | Low pressure difference linear voltage regulator |
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| CN201410010118.2A CN103713682B (en) | 2014-01-09 | 2014-01-09 | Low pressure difference linear voltage regulator |
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| CN103713682B true CN103713682B (en) | 2015-08-26 |
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| US9490759B2 (en) * | 2014-05-27 | 2016-11-08 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Neutralization of parasitic capacitance using MOS device |
| CN104734646B (en) * | 2015-04-13 | 2018-11-23 | 无锡新硅微电子有限公司 | Single miller capacitance frequency compensation method applied to multistage amplifier circuit |
| CN105867504B (en) * | 2016-06-13 | 2017-04-12 | 电子科技大学 | Reference voltage source with high power supply rejection ratio (PSRR) |
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| CN110554728A (en) * | 2019-09-26 | 2019-12-10 | 苏州晟达力芯电子科技有限公司 | Low dropout linear voltage stabilizing circuit |
| CN112684841B (en) * | 2019-10-18 | 2022-04-01 | 圣邦微电子（北京）股份有限公司 | Low dropout regulator with high power supply rejection ratio |
| CN110879629A (en) * | 2019-11-15 | 2020-03-13 | 芯创智（北京）微电子有限公司 | Low dropout linear voltage stabilizing circuit |
| US11036247B1 (en) | 2019-11-28 | 2021-06-15 | Shenzhen GOODIX Technology Co., Ltd. | Voltage regulator circuit with high power supply rejection ratio |
| US11112813B2 (en) | 2019-11-28 | 2021-09-07 | Shenzhen GOODIX Technology Co., Ltd. | Distributed low-dropout voltage regulator (LDO) with uniform power delivery |
| CN111290461B (en) * | 2020-03-09 | 2022-03-08 | 上海华虹宏力半导体制造有限公司 | Voltage regulator |
| CN111338416A (en) * | 2020-03-17 | 2020-06-26 | 北京思众电子科技有限公司 | LDO circuit control system and control method based on BCD process |
| CN111414040A (en) * | 2020-04-10 | 2020-07-14 | 上海兆芯集成电路有限公司 | Low dropout linear regulator |
| CN112015224A (en) * | 2020-10-22 | 2020-12-01 | 深圳市汇顶科技股份有限公司 | Low dropout regulator and power supply circuit |
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