CN105242734A - High-power LDO circuit without externally setting capacitor - Google Patents
High-power LDO circuit without externally setting capacitor Download PDFInfo
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- CN105242734A CN105242734A CN201410321405.5A CN201410321405A CN105242734A CN 105242734 A CN105242734 A CN 105242734A CN 201410321405 A CN201410321405 A CN 201410321405A CN 105242734 A CN105242734 A CN 105242734A
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Abstract
The invention relates to the technical field of power sources, and discloses a high-power LDO circuit without externally setting a capacitor, wherein the high-power LDO circuit provided herein is characterized in that the high-power LDO circuit is constituted of an error amplifier EA, an operational amplifier OP, two capacitors C1 and C2, three resistors R1, R2 and R3 and on N-type MOS pipe; the C2 is a built-in capacitor loaded by a gate end of Mpass of the N-type MOS pipe for reducing dominant pole frequency of a loop circuit of the LDO circuit; and at the same time, the capacitor C1 and the resistor R1 are added on an output end of the error amplifier EA to produce a zero point to offset the influence of the secondary dominant pole, thus ensuring the stability of a system. According to the invention, an internal loop circuit is set to compensate a circuit, thus ensuring that the system can still work stably without externally compensating capacitance at a large amount; and at the same time, by using the NMOS as a power device, the response speed of the system is improved, thus ensuring the output power of the LDO. The high-power LDO circuit provided herein is mainly used for supplying electricity for chips like central processing units with high performance, digital signal processors, programmable logic device and converters with high performance.
Description
Technical field
The invention belongs to power technique fields, particularly a kind of technology of the high power LD O circuit without external electric capacity.
Background technology
Along with the requirement that the progress of semiconductor technology and electronic market are more and more harsher, central processing unit, digital signal processor, programmable logic device (PLD) etc. core component speed goes is fast, and integrated level is more and more higher, also more and more higher to the requirement of power supply.And the linear voltage regulator LDO circuit of traditional external compensation, building-out capacitor is large, and application circuit is complicated, and do not meet the development trend of system compact, wherein namely LDO is linear voltage regulator.
Summary of the invention
The object of this invention is to provide a kind of high power LD O circuit not needing external electric capacity, guarantee system is without the need to the also Absorbable organic halogens work of outside large compensation electric capacity, the response speed of effective raising system simultaneously, ensures the power stage that circuit is large, easily with core component cooperating.
For achieving the above object, the technical solution used in the present invention is:
A kind of high power LD O circuit without external electric capacity, it is characterized in that: the described high power LD O circuit without external electric capacity is by an error amplifier EA, an operational amplifier OP, two electric capacity C1, C2, three resistance R1, R2, R3 and a N-type metal-oxide-semiconductor composition, the in-phase input end of error amplifier EA is connected on reference voltage V ref, the output terminal of error amplifier EA, the in-phase input end of operational amplifier OP are connected with one end of electric capacity C1, the other end of electric capacity C1 is connected with one end of resistance R1, the other end of resistance R1 is connected with ground GND, one end of the inverting input of operational amplifier OP, the output terminal of operational amplifier OP, electric capacity C2 is connected with the grid end of N-type metal-oxide-semiconductor Mpass, the other end of electric capacity C2 is connected with ground GND, the drain terminal of N-type metal-oxide-semiconductor Mpass is connected with power supply Vin, the source of N-type metal-oxide-semiconductor Mpass is connected with one end of resistance R3, as the output Vout of LDO, the other end, one end of resistance R2 of resistance R3 are connected with the inverting input of error amplifier, the other end of resistance R2 is connected with ground GND, wherein R3 and R2 is that the output voltage Vout of described high power LD O circuit is carried out the negative input end that then dividing potential drop is connected to error amplifier EA by divider resistance, the difference of the magnitude of voltage that this dividing potential drop obtains by described error amplifier EA and reference voltage V ref is amplified, and error amplification is obtained the positive input terminal that voltage is connected to operational amplifier OP, the output terminal of operational amplifier OP is connected with its negative input end, as the buffering between the output of error amplifier EA and output mos pipe Mpass, whole high power LD O circuit forms a feedback loop, when high power LD O circuit stability, the partial pressure value of R3 and R2 is equal with reference voltage V ref, the output voltage Vout=Vref* (1+R3/R2) of high power LD O circuit, wherein C2 is that the built-in capacitance of the grid end loading of N-type metal-oxide-semiconductor Mpass is to reduce the dominant pole frequency of the loop of high power LD O circuit, simultaneously by adding that at the output terminal of error amplifier EA electric capacity C1 and resistance R1 produces the impact of offsetting time dominant pole a zero point, thus the system of guarantee is stable.
Described operational amplifier comprises an electric current and leaks, five P type metal-oxide-semiconductors and three N-type metal-oxide-semiconductors, a resistance, an electric capacity, the connection of its circuit is: the drain electrode of the 0th P type metal-oxide-semiconductor MPO, the grid of the 0th P type metal-oxide-semiconductor MPO, the input end of current source I, the grid of the 4th P type metal-oxide-semiconductor MP4 are connected with the grid of a P type metal-oxide-semiconductor MP1; The drain electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The VP of input port in the same way of this operational amplifier is connected with the grid of the 3rd P type metal-oxide-semiconductor MP3; The reverse input end mouth VN of this operational amplifier is connected with the grid of the 2nd P type metal-oxide-semiconductor MP2; The drain electrode of the drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the grid of the 0th N-type metal-oxide-semiconductor MNO, the 0th N-type metal-oxide-semiconductor MNO is connected with the grid of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the drain electrode of the first N-type metal-oxide-semiconductor MN1, one end of electric capacity Cc are connected with the grid of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the drain electrode of the 4th P type metal-oxide-semiconductor MP4, one end of resistance Rc, the second N-type metal-oxide-semiconductor MN2 is connected with the output end vo ut of amplifier.The other end of resistance Rc is connected with the other end of electric capacity Cc.The source electrode of the source electrode of the 0th P type metal-oxide-semiconductor MPO, the source electrode of a P type metal-oxide-semiconductor MP1, the 4th P type metal-oxide-semiconductor MP4 is connected with power vd D.The source electrode of the 0th N-type metal-oxide-semiconductor MNO, the source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the outflow end of current source I are connected with ground GND.
Described error amplifier EA is cascade one-stage amplifier, and comprise seven P type metal-oxide-semiconductors and four N-type metal-oxide-semiconductors, its circuit connecting mode is: the drain electrode of a P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the input end in the same way of this error amplifier; The grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the reverse input end of this error amplifier; The drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the grid of the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6 is connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3; The drain electrode of the 4th P type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th P type metal-oxide-semiconductor MP6; The drain electrode of the 5th P type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th P type metal-oxide-semiconductor MP7; The drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier; The grid of the one P type metal-oxide-semiconductor MP1 is connected with bias voltage Vpb1; The grid of the 6th P type metal-oxide-semiconductor MP6, the grid of the 7th P type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb2; The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1; The grid of the 3rd N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2.The source electrode of the source electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5 is connected with power vd D.The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2 are connected with ground GND.
Compared with prior art, tool has the following advantages:
The present invention, by the linear voltage regulators of internal compensation, without the need to external large compensation electric capacity, can ensure system stability work by the improvement of internal circuit configuration, and can provide larger power stage, can easily with core component cooperating.Simultaneously also by NMOS power device, improve the response speed of system, ensure that the output power of LDO circuit.Be mainly used in central processing unit in high-performance, digital signal processor, programmable logic device (PLD), the power supply of the chips such as high performance converters.
Specifically, the present invention is due to when LDO circuit working, LDO circuit output voltage carries out by R3 and R2 the negative input end that then dividing potential drop is connected to error amplifier EA, the difference of the magnitude of voltage that this dividing potential drop obtains by error amplifier EA and reference voltage V ref is amplified, and error amplification is obtained the positive input terminal that voltage is connected to operational amplifier OP; The output terminal of operational amplifier OP is connected with its negative input end, as the buffering between the output of error amplifier EA and output mos pipe Mpass.Whole LDO system forms a feedback loop, when LDO circuit stability, the partial pressure value of R3 and R2 is equal with reference voltage V ref, therefore the output voltage Vout=Vref* (1+R3/R2) of LDO circuit can be obtained, at the grid end of N-type metal-oxide-semiconductor Mpass, this LDO circuit is by adding that built-in capacitance C2 reduces the dominant pole frequency of the loop of LDO circuit, simultaneously by adding that at the output terminal of error amplifier EA electric capacity C1 and resistance R1 produces the impact of offsetting time dominant pole a zero point, thus ensure that the stable of system.
Accompanying drawing explanation
Fig. 1 is the structural drawing of operational amplifier OP circuit in the present invention;
Fig. 2 is the structural drawing of medial error amplifier EA circuit of the present invention;
Fig. 3 is the structural drawing of the present invention without the high power LD O circuit of external electric capacity.
Embodiment
Be described in detail further below in conjunction with accompanying drawing.
As shown in Figure 3, the present invention without the high power LD O circuit of external electric capacity by an error amplifier EA, one by one operational amplifier OP, two electric capacity, three resistance and a N-type metal-oxide-semiconductor composition, its circuit connecting mode is: reference voltage V ref is connected with the in-phase input end of error amplifier EA; The output terminal of error amplifier EA, the in-phase input end of operational amplifier OP are connected with one end of electric capacity C1; The other end of electric capacity C1 is connected with one end of resistance R1; The other end of resistance R1 is connected with ground GND; One end of the inverting input of operational amplifier OP, the output terminal of operational amplifier OP, electric capacity C2 is connected with the grid end of N-type metal-oxide-semiconductor Mpass; The other end of electric capacity C2 is connected with ground GND; The drain terminal of N-type metal-oxide-semiconductor Mpass is connected with power supply Vin; The source of N-type metal-oxide-semiconductor Mpass is connected with one end of resistance R3, as the output Vout of LDO; The other end, one end of resistance R2 of resistance R3 are connected with the inverting input of error amplifier; The other end of resistance R2 is connected with ground GND.
When LDO works, LDO output voltage carries out by R3 and R2 the negative input end that then dividing potential drop is connected to error amplifier EA, the difference of the magnitude of voltage that this dividing potential drop obtains by error amplifier EA and reference voltage V ref is amplified, and error amplification is obtained the positive input terminal that voltage is connected to operational amplifier OP; The output terminal of operational amplifier OP is connected with its negative input end, as the buffering between the output of error amplifier EA and output mos pipe Mpass.Whole LDO system forms a feedback loop, and when LDO stablizes, the partial pressure value of R3 and R2 is equal with reference voltage V ref, therefore can obtain the output voltage Vout=Vref* (1+R3/R2) of LDO.
At the grid end of N-type metal-oxide-semiconductor Mpass, this LDO is by adding that built-in capacitance C2 reduces the dominant pole frequency of LDO loop, simultaneously by adding that at the output terminal of error amplifier EA electric capacity C1 and resistance R1 produces the impact of offsetting time dominant pole a zero point, thus the system of guarantee is stable.
As shown in Figure 1, the operational amplifier in the present invention comprises an electric current and leaks, five P type metal-oxide-semiconductors and three N-type metal-oxide-semiconductors, a resistance, an electric capacity, and its circuit connecting mode is:
The drain electrode of the 0th P type metal-oxide-semiconductor MPO, the grid of the 0th P type metal-oxide-semiconductor MPO, the input end of current source I, the grid of the 4th P type metal-oxide-semiconductor MP4 are connected with the grid of a P type metal-oxide-semiconductor MP1; The drain electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The VP of input port in the same way of this operational amplifier is connected with the grid of the 3rd P type metal-oxide-semiconductor MP3; The reverse input end mouth VN of this operational amplifier is connected with the grid of the 2nd P type metal-oxide-semiconductor MP2; The drain electrode of the drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the grid of the 0th N-type metal-oxide-semiconductor MNO, the 0th N-type metal-oxide-semiconductor MNO is connected with the grid of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the drain electrode of the first N-type metal-oxide-semiconductor MN1, one end of electric capacity Cc are connected with the grid of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the drain electrode of the 4th P type metal-oxide-semiconductor MP4, one end of resistance Rc, the second N-type metal-oxide-semiconductor MN2 is connected with the output end vo ut of amplifier.The other end of resistance Rc is connected with the other end of electric capacity Cc.The source electrode of the source electrode of the 0th P type metal-oxide-semiconductor MPO, the source electrode of a P type metal-oxide-semiconductor MP1, the 4th P type metal-oxide-semiconductor MP4 is connected with power vd D.The source electrode of the 0th N-type metal-oxide-semiconductor MNO, the source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the outflow end of current source I are connected with ground GND.
As shown in Figure 2, error amplifier EA is cascade one-stage amplifier, comprise seven P type metal-oxide-semiconductors and four N-type metal-oxide-semiconductors, its circuit connecting mode is: the drain electrode of a P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the input end in the same way of this error amplifier; The grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the reverse input end of this error amplifier; The drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the grid of the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6 is connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3; The drain electrode of the 4th P type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th P type metal-oxide-semiconductor MP6; The drain electrode of the 5th P type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th P type metal-oxide-semiconductor MP7; The drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier; The grid of the one P type metal-oxide-semiconductor MP1 is connected with bias voltage Vpb1; The grid of the 6th P type metal-oxide-semiconductor MP6, the grid of the 7th P type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb2; The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1; The grid of the 3rd N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2.The source electrode of the source electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5 is connected with power vd D.The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2 are connected with ground GND.
Claims (3)
1. the high power LD O circuit without external electric capacity, it is characterized in that: the described high power LD O circuit without external electric capacity is by an error amplifier EA, an operational amplifier OP, two electric capacity C1, C2, three resistance R1, R2, R3 and a N-type metal-oxide-semiconductor composition, the in-phase input end of error amplifier EA is connected on reference voltage V ref; The output terminal of error amplifier EA, the in-phase input end of operational amplifier OP are connected with one end of electric capacity C1; The other end of electric capacity C1 is connected with one end of resistance R1; The other end of resistance R1 is connected with ground GND; One end of the inverting input of operational amplifier OP, the output terminal of operational amplifier OP, electric capacity C2 is connected with the grid end of N-type metal-oxide-semiconductor Mpass; The other end of electric capacity C2 is connected with ground GND; The drain terminal of N-type metal-oxide-semiconductor Mpass is connected with power supply Vin; The source of N-type metal-oxide-semiconductor Mpass is connected with one end of resistance R3, as the output Vout of LDO; The other end, one end of resistance R2 of resistance R3 are connected with the inverting input of error amplifier; The other end of resistance R2 is connected with ground GND,
Wherein R3 and R2 is that the output voltage Vout of described high power LD O circuit is carried out the negative input end that then dividing potential drop is connected to error amplifier EA by divider resistance,
The difference of the magnitude of voltage that this dividing potential drop obtains by described error amplifier EA and reference voltage V ref is amplified, and error amplification is obtained the positive input terminal that voltage is connected to operational amplifier OP; The output terminal of operational amplifier OP is connected with its negative input end, as the buffering between the output of error amplifier EA and output mos pipe Mpass, whole high power LD O circuit forms a feedback loop, when high power LD O circuit stability, the partial pressure value of R3 and R2 is equal with reference voltage V ref, the output voltage Vout=Vref* (1+R3/R2) of high power LD O circuit
Wherein C2 is that the built-in capacitance of the grid end loading of N-type metal-oxide-semiconductor Mpass is to reduce the dominant pole frequency of the loop of LDO circuit, simultaneously by adding that at the output terminal of error amplifier EA electric capacity C1 and resistance R1 produces the impact of offsetting time dominant pole a zero point, thus the system of guarantee is stable.
2. according to claim 1 without the high power LD O circuit of external electric capacity, it is characterized in that: described operational amplifier comprises an electric current and leaks, five P type metal-oxide-semiconductors and three N-type metal-oxide-semiconductors, a resistance, an electric capacity, the connection of its circuit is: the drain electrode of the 0th P type metal-oxide-semiconductor MPO, the grid of the 0th P type metal-oxide-semiconductor MPO, the input end of current source I, the grid of the 4th P type metal-oxide-semiconductor MP4 are connected with the grid of a P type metal-oxide-semiconductor MP1; The drain electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The VP of input port in the same way of this operational amplifier is connected with the grid of the 3rd P type metal-oxide-semiconductor MP3; The reverse input end mouth VN of this operational amplifier is connected with the grid of the 2nd P type metal-oxide-semiconductor MP2; The drain electrode of the drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the grid of the 0th N-type metal-oxide-semiconductor MNO, the 0th N-type metal-oxide-semiconductor MNO is connected with the grid of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the drain electrode of the first N-type metal-oxide-semiconductor MN1, one end of electric capacity Cc are connected with the grid of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the drain electrode of the 4th P type metal-oxide-semiconductor MP4, one end of resistance Rc, the second N-type metal-oxide-semiconductor MN2 is connected with the output end vo ut of amplifier.The other end of resistance Rc is connected with the other end of electric capacity Cc.The source electrode of the source electrode of the 0th P type metal-oxide-semiconductor MPO, the source electrode of a P type metal-oxide-semiconductor MP1, the 4th P type metal-oxide-semiconductor MP4 is connected with power vd D.The source electrode of the 0th N-type metal-oxide-semiconductor MNO, the source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the outflow end of current source I are connected with ground GND.
3. according to claim 1 without the high power LD O circuit of external electric capacity, it is characterized in that: described error amplifier EA is cascade one-stage amplifier, comprise seven P type metal-oxide-semiconductors and four N-type metal-oxide-semiconductors, its circuit connecting mode is: the drain electrode of a P type metal-oxide-semiconductor MP1, the source electrode of the 2nd P type metal-oxide-semiconductor MP2 are connected with the source electrode of the 3rd P type metal-oxide-semiconductor MP3; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the input end in the same way of this error amplifier; The grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the reverse input end of this error amplifier; The drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1; The drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the grid of the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6 is connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3; The drain electrode of the 4th P type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th P type metal-oxide-semiconductor MP6; The drain electrode of the 5th P type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th P type metal-oxide-semiconductor MP7; The drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier; The grid of the one P type metal-oxide-semiconductor MP1 is connected with bias voltage Vpb1; The grid of the 6th P type metal-oxide-semiconductor MP6, the grid of the 7th P type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb2; The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1; The grid of the 3rd N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2.The source electrode of the source electrode of the one P type metal-oxide-semiconductor MP1, the source electrode of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5 is connected with power vd D.The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2 are connected with ground GND.
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| CN106067806B (en) * | 2016-06-01 | 2019-06-11 | 合肥格易集成电路有限公司 | A kind of buffer circuit |
| CN105955390A (en) * | 2016-07-01 | 2016-09-21 | 唯捷创芯(天津)电子技术股份有限公司 | Low-dropout linear regulator module, chip and communication terminal |
| CN106406411A (en) * | 2016-12-08 | 2017-02-15 | 上海爱信诺航芯电子科技有限公司 | Low dropout regulator circuit and power supply |
| US11537155B2 (en) | 2017-03-23 | 2022-12-27 | Ams Ag | Low-dropout regulator having reduced regulated output voltage spikes |
| CN110446992A (en) * | 2017-03-23 | 2019-11-12 | ams有限公司 | The low-dropout regulator of the output voltage spike through adjusting with reduction |
| CN107491131A (en) * | 2017-10-16 | 2017-12-19 | 佛山科学技术学院 | A kind of numerical model analysis controls more loop LDO circuits |
| CN107491131B (en) * | 2017-10-16 | 2023-02-28 | 佛山科学技术学院 | Digital-analog hybrid control multi-loop LDO circuit |
| CN109450385A (en) * | 2018-09-25 | 2019-03-08 | 福建省福芯电子科技有限公司 | Error amplifier circuit |
| CN111221369A (en) * | 2018-11-23 | 2020-06-02 | 比亚迪股份有限公司 | Low dropout linear regulator |
| CN111221369B (en) * | 2018-11-23 | 2022-01-07 | 比亚迪半导体股份有限公司 | Low dropout linear regulator |
| CN110187730A (en) * | 2019-04-30 | 2019-08-30 | 广东明丰电源电器实业有限公司 | A kind of energy conservation linear circuit and electronic equipment |
| CN110837268A (en) * | 2019-12-10 | 2020-02-25 | 复旦大学 | Two-stage low dropout linear regulator with low noise and high power supply rejection ratio |
| US11467614B2 (en) * | 2020-09-10 | 2022-10-11 | Apple Inc. | Voltage mode low-dropout regulator circuit with reduced quiescent current |
| CN113067469A (en) * | 2021-03-30 | 2021-07-02 | 苏州源特半导体科技有限公司 | Quick response loop compensation circuit, loop compensation chip and switching power supply |
| CN114625196B (en) * | 2022-03-28 | 2022-10-11 | 广东鸿翼芯汽车电子科技有限公司 | LDO circuit with wide input common mode range |
| CN114625196A (en) * | 2022-03-28 | 2022-06-14 | 广东鸿翼芯汽车电子科技有限公司 | LDO circuit with wide input common mode range |
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