CN109450385A - Error amplifier circuit - Google Patents
Error amplifier circuit Download PDFInfo
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- CN109450385A CN109450385A CN201811115462.2A CN201811115462A CN109450385A CN 109450385 A CN109450385 A CN 109450385A CN 201811115462 A CN201811115462 A CN 201811115462A CN 109450385 A CN109450385 A CN 109450385A
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- connect
- grid
- drain electrode
- amplifier
- source electrode
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The present invention provides a kind of error amplifier circuit, including the first amplifier, the second amplifier, the electrode input end of first amplifier connects chip sampled voltage, output termination negative input, the negative input of the second amplifier of output end connects, the output pin of reference voltage in the electrode input end contact pin of second amplifier, output end and error amplifier circuit connects.The external COMP capacitor of the prior art can be save, system cost is greatly saved and simplifies manufacturing process, while further improving the constant pressure precision of output voltage.
Description
Technical field
The present invention relates on piece error amplifying circuit design field more particularly to a kind of on piece error amplifications being internally integrated
Circuit.
Background technique
In fields such as AC/DC, DC/DC designs using the output voltage signal sampled as the feedback of PWM/PFM controller
Voltage, the feedback voltage adjust the duty ratio of switching signal after the error amplifier inside controller to realize output electricity
The stabilization of pressure.Wherein the design of error amplifier is one of key technology.
Error amplifier amplifies the error of output signal and reference signal, amplified error signal and comparator
It is compared and is converted into digital logic signal adjusting duty ratio, when output voltage is higher, duty ratio is reduced, otherwise duty ratio liter
It is high.Error amplifier also plays the role of adjusting power supply loop stability simultaneously, and power-supply system loop is passed by the small signal of main circuit
Defeated function and the small signal transfer function of control circuit cascade, whether power supply is stable, by the transfer function of entire loop
Amplitude-frequency characteristic and phase-frequency characteristic determine.In general to meet condition: 1) loop bandwidth is the part of switching frequency
To between ten parts；2) low frequency amplitude is sufficiently high；3) intermediate frequency -20dB/10 overtones band passes through；4) rf amplitude is sufficiently low；
5) certain phase margin and loop gain；AC/DC, DC/DC loop of the prior art need to meet the stability of loop
Error amplifier output end connect a several pico farads to tens pf capacitance values adjust loop transfer function amplitude-frequency and phase frequency
Characteristic can not be integrated into chip interior since capacitance is larger, and the prior art is needed through chip pin external capacitor.
For prior art error amplifier as shown in Figure 1, Ccomp is chip pin external capacitor in figure, particular sheet choosing is outer
Enclosing design can need according to periphery generally from several pico farads to tens pico farads, if with 1.5fF/um^2 with reference to Fig. 2, the i.e. capacitor
It estimates, 10 pf capacitance values about 6660um^2, chip area significant proportion can be accounted for, while the capacitive property is not so good as external ceramic electrical
Hold function admirable.
Summary of the invention
In order to save the bulky capacitor in DC communication electricity consumption circulationization circuit design, the present invention is provided in a kind of choosing design
A kind of error amplifier circuit, including the first amplifier, the second amplifier, the electrode input end of first amplifier connect
Chip sampled voltage, output termination negative input, the negative input connection of the second amplifier of output end, the second amplifier
The output pin of reference voltage in electrode input end contact pin, output end and error amplifier circuit connects.
It specifically, further include resistance R1, resistance R2, one end of the resistance R1 is connect with the second amplifier out, separately
One end is connect with the second amplifier negative input；One end of the resistance R2 is connect with the second amplifier negative input, separately
One end is connect with the first amplifier out.
Preferably, the comparator include p-type metal-oxide-semiconductor PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, PMOS6,
PMOS7,PMOS8,PMOS9；Further include N-type metal-oxide-semiconductor NMOS1, NMOS2, NMOS3, NMOS4, NMOS5, NMOS6, NMOS7,
NMOS8,NMOS9,NMOS10；
The source electrode of described PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, PMOS6, PMOS9 connects, the grid of PMOS1 with
Drain electrode connection, the grid of PMOS1 are also connect with the grid of PMOS2, PMOS3, PMOS9, and the drain electrode of the PMOS2 is with NMOS6's
Grid is connect with source electrode, and the grid of NMOS6 is also connect with the grid of NMOS7, NMPS8, NMOS10；The drain electrode of the PMOS3 is also
It is connect with the source electrode of PMOS7, PMOS8, the grid of PMOS7, PMOS8 connect negative input and the anode input of comparator respectively
End, the drain electrode of PMOS7 are connect with the source electrode of NMOS7, and the drain electrode of PMOS8 is connect with the source electrode of NMOS8；The grid of the PMOS4
It is connected with drain electrode, the grid of PMOS4 is also connect with the grid of PMOS5, and the drain electrode of PMOS4 is connect with the source electrode of NMOS1, PMOS5
Drain electrode connect with the source electrode of the grid of PMOS9 and NMOS2；The grid of NMOS1, NMOS2 and NMOS3 are connected with each other, NMOS1's
Drain electrode is connect with the source electrode of NMOS7, and the drain electrode of NMOS2 is connect with the source electrode of NMOS8；The drain electrode of the PMOS6 and the source of NMOS3
Pole and grid connection, the drain electrode of NMOS3 are connect with the source electrode of NMOS9 and grid；The grid of PMOS9 also connects with the source electrode of NMOS5
Connect, the source electrode of the grid of NMOS5 and NMOS4 connect, and the drain electrode of NMOS5 is connect with the grid of NMOS4, the drain electrode of NMOS4 and
The drain electrode of PMOS9 and the source electrode of NMOS10 are connect with comparator output terminal, NMOS6, NMOS7, NMOS8, NMOS9, NMOS10
Drain electrode be connected with each other.
The present invention has the advantage that save the external COMP capacitor of the prior art, be greatly saved system cost and
Simplify manufacturing process；The constant pressure precision of output voltage is further improved simultaneously.
Detailed description of the invention
Fig. 1 is existing error amplifier figure described in certain specific embodiment of the invention；
Fig. 2 is peripheral system design drawing described in certain specific embodiment of the invention；
Fig. 3 is error amplifier circuit figure described in certain specific embodiment of the invention；
Fig. 4 is comparator design figure described in certain specific embodiment of the invention；
Fig. 5 is peripheral system design drawing described in certain specific embodiment of the invention.
Specific embodiment
In order to describe the technical content, the structural feature, the achieved object and the effect of this invention in detail, below in conjunction with embodiment
And attached drawing is cooperated to be explained in detail.
In the embodiment shown in fig. 3, a kind of mistake that can be used for AC-DC conversion chip or DC-DC conversion chip is described
Poor amplifier circuit can integrate in the design of the on piece of AC-DC conversion chip or DC-DC conversion chip.Including the first amplification
Device, the second amplifier, the electrode input end of first amplifier connect chip sampled voltage, and output termination negative input is defeated
The negative input of the second amplifier of outlet connects, reference voltage in the electrode input end contact pin of the second amplifier, output end with
The output pin of error amplifier circuit connects.
It specifically, further include resistance R1, resistance R2, one end of the resistance R1 is connect with the second amplifier out, separately
One end is connect with the second amplifier negative input；One end of the resistance R2 is connect with the second amplifier negative input, separately
One end is connect with the first amplifier out.Wherein VFB is chip sampled voltage；The output and negative input of operational amplifier OPA1
End connects and composes buffer structure, acts on VFB voltage sample to output end；R1 and R2 is proportion divider resistance；R3 and C1
Low-pass filtering effect, C1 capacitor play a filtering role size and are less about 100um^2 and are common metal-oxide-semiconductor capacitor, compared with prior art
External capacitor, area occupied will greatly reduce.The R3 resistance is as dropping resistor and C1 capacitor conduct in certain embodiments
Filter capacitor also can be omitted, thus influence on circuit performance little.It completely can be integrated on piece design.VREF is
Reference voltage, operational amplifier OPA2 output are connected to the end R1, and OPA2 negative input end is connected to the R1 other end, and the output of OPA2 is logical
It crosses R1, R2 electric resistance partial pressure and forms negative-feedback.
Wherein:
Above formula may be implemented in the above circuit, sampled voltage VFB and EAout can be made real by adjusting R1, R2 resistance value
Existing required proportionate relationship, while EAout and internal ramp are compared the corresponding duty ratio of generation.While OPA2, OPA1
Gain can be designed bigger, keep sampled voltage VFB and reference voltage VREF error smaller.
Proposed by the present invention by the cascade mode of OPA1 and OPA2 is that buffer structure and reverse phase are summed the cascade of structure, instead
Phase summing circuit is typically employed in a control system and for example needs to turn the physical quantitys such as temperature, pressure and speed by sensor
Analog voltage amount is turned in being summed, the present invention applied in error amplifier can with more precise control VFB and
The error of VREF.
In preferred embodiment, as shown in figure 4, giving the circuit of specific implementation amplifier OPA1 or OPA2 can design such as
Shown in figure.Used the AC-DC conversion chip after the design scheme peripheral system connect design then can with as shown in figure 5,
Relative to the prior art shown above, our error amplifying circuit update obviously eliminates external pin, saves
On piece design area, while cost of manufacture is also saved, there is good practical value.In the example in figure 4, comparator includes
P-type metal-oxide-semiconductor PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, PMOS6, PMOS7, PMOS8, PMOS9；It further include N-type metal-oxide-semiconductor
NMOS1,NMOS2,NMOS3,NMOS4,NMOS5,NMOS6,NMOS7,NMOS8,NMOS9,NMOS10；
The source electrode of described PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, PMOS6, PMOS9 connects, the grid of PMOS1 with
Drain electrode connection, the grid of PMOS1 are also connect with the grid of PMOS2, PMOS3, PMOS9, and the drain electrode of the PMOS2 is with NMOS6's
Grid is connect with source electrode, and the grid of NMOS6 is also connect with the grid of NMOS7, NMPS8, NMOS10；The drain electrode of the PMOS3 is also
It is connect with the source electrode of PMOS7, PMOS8, the grid of PMOS7, PMOS8 connect negative input and the anode input of comparator respectively
End, the drain electrode of PMOS7 are connect with the source electrode of NMOS7, and the drain electrode of PMOS8 is connect with the source electrode of NMOS8；The grid of the PMOS4
It is connected with drain electrode, the grid of PMOS4 is also connect with the grid of PMOS5, and the drain electrode of PMOS4 is connect with the source electrode of NMOS1, PMOS5
Drain electrode connect with the source electrode of the grid of PMOS9 and NMOS2；The grid of NMOS1, NMOS2 and NMOS3 are connected with each other, NMOS1's
Drain electrode is connect with the source electrode of NMOS7, and the drain electrode of NMOS2 is connect with the source electrode of NMOS8；The drain electrode of the PMOS6 and the source of NMOS3
Pole and grid connection, the drain electrode of NMOS3 are connect with the source electrode of NMOS9 and grid；The grid of PMOS9 also connects with the source electrode of NMOS5
Connect, the source electrode of the grid of NMOS5 and NMOS4 connect, and the drain electrode of NMOS5 is connect with the grid of NMOS4, the drain electrode of NMOS4 and
The drain electrode of PMOS9 and the source electrode of NMOS10 are connect with comparator output terminal, NMOS6, NMOS7, NMOS8, NMOS9, NMOS10
Drain electrode be connected with each other.
The above description is only an embodiment of the present invention, is not intended to limit scope of patent protection of the invention, all utilizations
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content is applied directly or indirectly in other correlations
Technical field, be included within the scope of the present invention.
Claims (3)
1. a kind of error amplifier circuit, which is characterized in that including the first amplifier, the second amplifier, first amplifier
Electrode input end connect chip sampled voltage, output termination negative input, the negative input of the second amplifier of output end connects
It connects, reference voltage in the electrode input end contact pin of the second amplifier, the output pin connection of output end and error amplifier circuit.
2. error amplifier circuit according to claim 1, which is characterized in that further include resistance R1, resistance R2, the electricity
One end of resistance R1 is connect with the second amplifier out, and the other end is connect with the second amplifier negative input；The resistance R2
One end connect with the second amplifier negative input, the other end is connect with the first amplifier out.
3. error amplifier circuit according to claim 1, which is characterized in that the comparator includes p-type metal-oxide-semiconductor
PMOS1,PMOS2,PMOS3,PMOS4,PMOS5,PMOS6,PMOS7,PMOS8,PMOS9；Further include N-type metal-oxide-semiconductor NMOS1,
NMOS2,NMOS3,NMOS4,NMOS5,NMOS6,NMOS7,NMOS8,NMOS9,NMOS10；
The source electrode of described PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, PMOS6, PMOS9 connect, the grid of PMOS1 and drain electrode
Connection, the grid of PMOS1 are also connect with the grid of PMOS2, PMOS3, PMOS9, the drain electrode of the PMOS2 and the grid of NMOS6
It is connect with source electrode, the grid of NMOS6 is also connect with the grid of NMOS7, NMPS8, NMOS10；The drain electrode of the PMOS3 also with
The source electrode of PMOS7, PMOS8 connect, and the grid of PMOS7, PMOS8 connect the negative input and electrode input end of comparator respectively,
The drain electrode of PMOS7 is connect with the source electrode of NMOS7, and the drain electrode of PMOS8 is connect with the source electrode of NMOS8；The grid of the PMOS4 and leakage
Pole connection, the grid of PMOS4 are also connect with the grid of PMOS5, and the drain electrode of PMOS4 is connect with the source electrode of NMOS1, the leakage of PMOS5
The source electrode of the grid and NMOS2 of pole and PMOS9 connects；The grid of NMOS1, NMOS2 and NMOS3 are connected with each other, the drain electrode of NMOS1
It is connect with the source electrode of NMOS7, the drain electrode of NMOS2 is connect with the source electrode of NMOS8；The drain electrode of the PMOS6 and the source electrode of NMOS3 and
Grid connection, the drain electrode of NMOS3 are connect with the source electrode of NMOS9 and grid；The grid of PMOS9 is also connect with the source electrode of NMOS5,
The grid of NMOS5 and the source electrode of NMOS4 connect, and the drain electrode of NMOS5 is connect with the grid of NMOS4, the drain electrode of NMOS4 and PMOS9
Drain electrode and the source electrode of NMOS10 connect with comparator output terminal, the drain electrode of NMOS6, NMOS7, NMOS8, NMOS9, NMOS10
It is connected with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811115462.2A CN109450385A (en) | 2018-09-25 | 2018-09-25 | Error amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811115462.2A CN109450385A (en) | 2018-09-25 | 2018-09-25 | Error amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109450385A true CN109450385A (en) | 2019-03-08 |
Family
ID=65530677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811115462.2A Pending CN109450385A (en) | 2018-09-25 | 2018-09-25 | Error amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109450385A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102707755A (en) * | 2012-05-30 | 2012-10-03 | 西安航天民芯科技有限公司 | Linear voltage regulator with built-in compensation capacitor |
| CN103792982A (en) * | 2013-11-21 | 2014-05-14 | 无锡芯响电子科技有限公司 | Low dropout linear regulator without external capacitor |
| CN104076854A (en) * | 2014-06-27 | 2014-10-01 | 电子科技大学 | Capless LDO (Low Dropout Regulator) |
| US20150156834A1 (en) * | 2013-12-04 | 2015-06-04 | Infineon Technologies Ag | Feedforward circuit for fast analog dimming in led drivers |
| CN105242734A (en) * | 2014-07-08 | 2016-01-13 | 广州市力驰微电子科技有限公司 | High-power LDO circuit without externally setting capacitor |
-
2018
- 2018-09-25 CN CN201811115462.2A patent/CN109450385A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102707755A (en) * | 2012-05-30 | 2012-10-03 | 西安航天民芯科技有限公司 | Linear voltage regulator with built-in compensation capacitor |
| CN103792982A (en) * | 2013-11-21 | 2014-05-14 | 无锡芯响电子科技有限公司 | Low dropout linear regulator without external capacitor |
| US20150156834A1 (en) * | 2013-12-04 | 2015-06-04 | Infineon Technologies Ag | Feedforward circuit for fast analog dimming in led drivers |
| CN104076854A (en) * | 2014-06-27 | 2014-10-01 | 电子科技大学 | Capless LDO (Low Dropout Regulator) |
| CN105242734A (en) * | 2014-07-08 | 2016-01-13 | 广州市力驰微电子科技有限公司 | High-power LDO circuit without externally setting capacitor |
Non-Patent Citations (4)
| Title |
|---|
| R.JACOB BAKER: "《CMOS电路设计.布局与仿真》", 31 January 2006, 机械工业出版社 * |
| WAI-KAI CHEN: "《模拟与超大规模集成电路》", 30 November 2013, 国防工业出版社 * |
| 史红梅: "《测控电路及应用》", 31 January 2011, 华中科技大学出版社 * |
| 陈朝勇: "700V单芯片LED照明恒流驱动电路", 《中国优秀硕士论文全文数据库（基础科学辑）》 * |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190308 |
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| RJ01 | Rejection of invention patent application after publication |