CN113342108B - Parallel operational amplifier zero compensation circuit - Google Patents
Parallel operational amplifier zero compensation circuit Download PDFInfo
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- CN113342108B CN113342108B CN202110640554.8A CN202110640554A CN113342108B CN 113342108 B CN113342108 B CN 113342108B CN 202110640554 A CN202110640554 A CN 202110640554A CN 113342108 B CN113342108 B CN 113342108B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention relates to a parallel operational amplifier zero compensation circuit, which relates to the integrated circuit technology and comprises a power MOS (M0), a resistor (Rc) and a load Capacitor (CL), and is characterized in that the input end of the compensation circuit is connected with the grid of the power MOS and the input end of a current amplifier, and the grid of the power MOS is connected with the current output end of the power MOS through a capacitor; the current output end of the power MOS tube is used as the output end of the compensation circuit, the current output end of the power MOS tube is connected with the output end of the current amplifier through a resistor (Rc), the output end of the current amplifier is connected with the current source, and the other end of the current source is grounded. The invention can reduce the overcharge amplitude of the output voltage when the load current is suddenly reduced.
Description
Technical Field
The invention relates to a linear voltage stabilizer, in particular to a parallel operational amplifier zero compensation circuit of a low dropout linear voltage stabilizer
Background
The low dropout regulator is an essential part of a power management circuit, and is widely applied to portable electronic equipment, communication electronic equipment and the like due to unique advantages of the low dropout regulator in voltage drop, PSRR, noise, cost and the like.
The low dropout linear regulator consists of a negative feedback loop, can adjust the output voltage to a required voltage value, and has to design a proper frequency response compensation network for better stability and transient response performance. Because of its own characteristics, a conventional voltage regulator usually includes a secondary pole in a loop of the voltage regulator, and in order to eliminate the influence of the secondary pole, the conventional method generates a left half-plane zero close to the secondary pole to counteract the influence of the secondary pole through the effect of an equivalent series resistance of an output capacitor, so that the loop of the voltage regulator is stable, as shown in fig. 1; or the original right half-plane zero point is converted into the left half-plane zero point by connecting a zero resistor and the miller capacitor in series, as shown in the attached figure 2. However, the two methods introduce a fixed zero point, and the position of the zero point does not change along with the change of the load current, so in order to maintain the stability of the circuit in a wide load range, other better circuit structures must be designed to generate the required left half-plane zero point, so that the circuit has better stability and transient response performance.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a parallel operational amplifier zero compensation circuit, which can generate a dynamic zero, and the zero position is dynamically adjusted along with the load current.
The technical scheme adopted by the invention for solving the technical problems is that the parallel operational amplifier zero compensation circuit comprises a power MOS tube, a resistor Rc and a load capacitor CL, and is characterized in that the input end of the compensation circuit is connected with the grid of the power MOS tube and the input end of a current amplifier, and the grid of the power MOS tube is connected with the current output end of the power MOS tube through a capacitor; the current output end of the power MOS tube is used as the output end of the compensation circuit, the current output end of the power MOS tube is connected with the output end of the current amplifier through a resistor Rc, the output end of the current amplifier is connected with a current source, and the other end of the current source is grounded.
The power MOS tube is a PMOS tube.
The current amplifier includes:
the source electrode of the first PMOS tube (mp0) and the source electrode of the power MOS tube are connected with a high-level end VIN;
a source electrode of the fourth PMOS tube is connected with a high-level end VIN, and a grid electrode of the fourth PMOS tube, a grid electrode of the first PMOS tube and a grid electrode of the power MOS tube are connected with an input end Vi of the compensation circuit;
a second current source, one end of which is connected with a high level end VIN and the other end of which is connected with the drain electrode of the first PMOS tube (mp 0);
a second PMOS tube (Md0), the source electrode of which is connected with the drain electrode of the first PMOS tube (mp0), and the drain electrode of which is connected with the drain electrode of the third NMOS tube (MC 0);
the source electrode of the third NMOS tube is grounded, and the grid electrode and the drain electrode of the third NMOS tube are connected with the grid electrode of the fifth NMOS tube (MC);
the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube;
the positive input end of the operational amplifier is connected with the drain electrode of the fourth PMOS tube, the negative input end of the operational amplifier is connected with the drain electrode of the first PMOS tube, and the output end of the operational amplifier is connected with the grid electrode of the second PMOS tube;
and the drain electrode of the fourth PMOS tube is used as the output end of the current amplifier.
Compared with a zero point with a fixed position generated by a traditional zero point compensation circuit, due to the combined action of the current amplifier, the Rc and the Cgd, the zero point compensation circuit can generate a dynamic zero point of a left half plane, the zero point position changes along with the change of load current, the stability of the circuit when the load current of the circuit changes in a wide range can be maintained, and the zero point can offset one pole of an LDO circuit, so that the bandwidth of the circuit is increased, and the transient response performance of the circuit is enhanced. Meanwhile, the current amplifier mirrors the current of the power tube M0, so that the output current of the current amplifier can be increased along with the increase of the load current, and the overcharge amplitude of the output voltage when the load current suddenly decreases is reduced.
Drawings
FIG. 1 is a schematic diagram of an equivalent series ESR resistance zero compensation circuit of an output capacitor
FIG. 2 is a schematic diagram of a compensation circuit for zero point of the series resistor of the Maitreya capacitor
FIG. 3 is a schematic diagram of a parallel operational amplifier zero compensation circuit according to the present invention
FIG. 4 is a schematic diagram of a parallel operational amplifier zero compensation circuit according to an embodiment of the present invention
Detailed Description
Referring to fig. 3, as an embodiment, the present invention includes a power MOS transistor M0, a current amplifier, a resistor Rc, a current source I0, a capacitor Cgd, and a load capacitor CL, and can generate a left half-plane dynamic zero for canceling a secondary pole of the LDO circuit, thereby maintaining system stability, increasing circuit bandwidth, and enhancing transient response performance of the circuit. Meanwhile, the current amplifier mirrors the current of the power tube M0, so that the output current of the current amplifier can be increased along with the increase of the load current, and the overcharge amplitude of the output voltage when the load current suddenly decreases is reduced.
The power MOS tube comprises a grid electrode, a current amplifier and a capacitor Cgd, wherein one end of the power MOS tube is connected with an input Vi of a circuit, a source electrode of the power MOS tube P is connected with a power supply voltage, a drain electrode of the power MOS tube is connected with the other end of the resistor Rc and the capacitor Cgd and a load capacitor CL is connected with an output voltage Vo, the other end of the load capacitor is grounded, the other end of the resistor Rc is connected with an output of the current amplifier and one end of a current source I0, and the other end of the current source I0 is grounded.
Referring to fig. 4, the current amplifier includes:
a first PMOS transistor mp0, the source electrode of which and the source electrode of the power MOS transistor are connected with a high level end VIN;
a source electrode of the fourth PMOS transistor mp is connected with a high-level end VIN, and a grid electrode of the fourth PMOS transistor mp, a grid electrode of the first PMOS transistor mp0 and a grid electrode of the power MOS transistor are connected with an input end Vi of the compensation circuit;
a second current source, one end of which is connected with a high level end VIN and the other end of which is connected with the drain electrode of the first PMOS tube mp 0;
a source electrode of the second PMOS tube Md0 is connected with a drain electrode of the first PMOS tube mp0, and a drain electrode of the second PMOS tube Md0 is connected with a drain electrode of the third NMOS tube MC 0;
the source electrode of the third NMOS tube MC0 is grounded, and the grid electrode and the drain electrode are connected with the grid electrode of the fifth NMOS tube MC;
the source electrode of the fifth NMOS transistor MC is grounded, and the drain electrode of the fifth NMOS transistor MC is connected with the drain electrode of the fourth PMOS transistor mp;
the positive input end of the operational amplifier is connected with the drain electrode of the fourth PMOS transistor mp, the negative input end of the operational amplifier is connected with the drain electrode of the first PMOS transistor, and the output end of the operational amplifier is connected with the grid electrode of the second PMOS transistor Md 0;
the drain electrode of the fourth PMOS pipe mp is used as the output end of the current amplifier.
From fig. 4, the power MOS transistor M0 is a large PMOS transistor, and the fourth PMOS transistor mp is a PMOS transistor of the same type. Power MOS transistor M0 andthe transconductance of the four PMOS tubes mp is G mp 、g mp The capacitance across the two ends of each gate and drain is C gd 、C gdp . Since the area of the fourth PMOS transistor mp is smaller than that of M0, if the fourth PMOS transistor mp is connected to form a source-level negative feedback structure, the equivalent input transconductance of the fourth PMOS transistor mp will be reduced, so C gdp And can be ignored. The amplifier A provides high gain and clamps the drain voltage of the first PMOS transistor mp0 and the drain voltage of the fourth PMOS transistor mp, so that when VFB changes, the drain voltage of the first PMOS transistor mp0 changes along with the change of the VFB, and nonlinearity of current copying with the power MOS transistor M0 is reduced; the MC tube of the fifth NMOS tube provides bias current for the mp tube of the fourth PMOS tube, calculates the zero point from input to output, and makes the output short-circuit to the ground:
obtaining:
in the above formula, when
When S is present Z < 0, zero occurs in the left half plane. And because of V FB ＝V ref ，V out ＝V FB +(I 0 +I out )R c If the output point is required to follow the reference voltage value within 0.1% of the error
ΔV out /V ref ＝(I 0 +I out )R c /V ref ＜0.1％
Namely:
R c ＜0.1％V ref /(I 0 +I out )
so that:
i.e. the appropriate value R c The zero point can be moved from the right half plane to the left half plane. From another perspective, R is the accuracy with which the output voltage does not follow the reference voltage c The zero point can be positioned on the left half plane by taking a larger value, and the system stability can be met, but the larger R c Will slow down the discharge speed of the output point charge and increase the recovery time of the output overcharge voltage after the large load current is withdrawn, so R c Larger values are not preferred.
When the load current changes, the current flowing through the PMOS power tube M0 and the fourth PMOS tube mp changes along with the change, G mp And g mp The value of zero follows the change, and according to the expression of zero point, the value of zero point follows the change, so that the required dynamic zero point which changes along with the load is obtained. Apply to above-mentioned circuit LDO, when the load current of LDO changes, because the output pole (the secondary pole) of LDO itself can follow the load current and change, set up suitable circuit parameter and make the dynamic zero can offset the secondary pole of LDO circuit for LDO can be at full load within range steady operation. Meanwhile, the bandwidth of the LDO is increased, and the transient response performance of the circuit is enhanced.
On the other hand, an output current formula is obtained according to the KCL law:
I out ＝I 2 +I in -I 1
according to the formula and the circuit, I is obtained at low load current out ＝I in Is a constant value; as the load increases to a certain value, I 1 And I 2 The difference between them is not negligible, so I out ＝I 2 +I in -I 1 At this time I out Increases non-linearly with increasing load current. Such a dynamic pull-down current helps to reduce the output point V when the heavy load current suddenly drops out Thereby enhancing the transient response performance of the circuit.
Claims (2)
1. The parallel operational amplifier zero-point compensation circuit comprises a power MOS (metal oxide semiconductor) tube (M0), a resistor (Rc) and a load Capacitor (CL), wherein the drain electrode and the grid electrode of the power MOS tube (M0) are connected through a capacitor (Cgd), and the parallel operational amplifier zero-point compensation circuit is characterized in that the input end of the compensation circuit is connected with the grid electrode of the power MOS tube and the input end of a current amplifier, and the grid electrode of the power MOS tube is connected with the current output end of the power MOS tube through a capacitor; the current output end of the power MOS tube is used as the output end of the compensation circuit, the current output end of the power MOS tube is connected with the output end of the current amplifier through a resistor (Rc), the output end of the current amplifier is connected with a current source, and the other end of the current source is grounded;
the current amplifier includes:
the source electrode of the first PMOS tube (mp0) and the source electrode of the power MOS tube are connected with a high-level end VIN;
a fourth PMOS tube (mp), wherein the source electrode of the fourth PMOS tube (mp) is connected with the high-level end VIN, and the grid electrode of the fourth PMOS tube (mp) and the grid electrode of the first PMOS tube (mp0) and the grid electrode of the power MOS tube are connected with the input end Vi of the compensation circuit;
a second current source, one end of which is connected with a high level end VIN and the other end of which is connected with the drain electrode of the first PMOS tube (mp 0);
a second PMOS tube (Md0), the source electrode of which is connected with the drain electrode of the first PMOS tube (mp0), and the drain electrode of which is connected with the drain electrode of the third NMOS tube (MC 0);
the source electrode of the third NMOS tube (MC0) is grounded, and the grid electrode and the drain electrode of the third NMOS tube (MC) are connected with the grid electrode of the fifth NMOS tube (MC);
the source electrode of the fifth NMOS tube (MC) is grounded, and the drain electrode of the fifth NMOS tube (MC) is connected with the drain electrode of the fourth PMOS tube (mp);
the positive input end of the operational amplifier is connected with the drain electrode of the fourth PMOS tube (mp), the negative input end of the operational amplifier is connected with the drain electrode of the first PMOS tube, and the output end of the operational amplifier is connected with the grid electrode of the second PMOS tube (Md 0);
the drain electrode of the fourth PMOS tube (mp) is used as the output end of the current amplifier, the area of the fourth PMOS tube (mp) is smaller than that of the power MOS tube (M0), and the fourth PMOS tube (mp) is provided with a source electrode negative feedback structure;
resistance Rc satisfies
Wherein g is mp Is transconductance of a fourth PMOS transistor (mp), and Cgd is capacitance C gd Capacitance value of (C) L Is the capacitance value of the load Capacitance (CL).
2. The parallel operational amplifier zero compensation circuit of claim 1, wherein the power MOS transistor is a PMOS transistor.
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| CN202110640554.8A CN113342108B (en) | 2021-06-08 | 2021-06-08 | Parallel operational amplifier zero compensation circuit |
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| CN117452998B (en) * | 2022-09-28 | 2024-04-02 | 晟芯腾跃(北京)科技有限公司 | PMOS power tube LDO circuit with feedforward zero point stability compensation |
| CN117519397B (en) * | 2024-01-05 | 2024-04-12 | 成都新欣神风电子科技有限公司 | Zero bias adjustable circuit based on magnetic balance current sensor |
Citations (4)
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| CN103064455A (en) * | 2012-12-07 | 2013-04-24 | 广州慧智微电子有限公司 | Dynamic zero miller compensation linear voltage regulator circuit based on zero adjusting resistor |
| CN103838290A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Ldo circuit |
| CN106774572A (en) * | 2016-12-08 | 2017-05-31 | 广州慧智微电子有限公司 | Miller-compensated circuit and electronic circuit |
| CN109460105A (en) * | 2018-12-24 | 2019-03-12 | 中国电子科技集团公司第五十八研究所 | A kind of dynamic zero pole point tracking and compensating circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6690147B2 (en) * | 2002-05-23 | 2004-02-10 | Texas Instruments Incorporated | LDO voltage regulator having efficient current frequency compensation |
| US7589507B2 (en) * | 2005-12-30 | 2009-09-15 | St-Ericsson Sa | Low dropout regulator with stability compensation |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103064455A (en) * | 2012-12-07 | 2013-04-24 | 广州慧智微电子有限公司 | Dynamic zero miller compensation linear voltage regulator circuit based on zero adjusting resistor |
| CN103838290A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Ldo circuit |
| CN106774572A (en) * | 2016-12-08 | 2017-05-31 | 广州慧智微电子有限公司 | Miller-compensated circuit and electronic circuit |
| CN109460105A (en) * | 2018-12-24 | 2019-03-12 | 中国电子科技集团公司第五十八研究所 | A kind of dynamic zero pole point tracking and compensating circuit |
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