CN220156403U - Low-delay inductance current sampling circuit - Google Patents

Abstract

The utility model relates to the technical field of inductance current sampling integrated circuits, and discloses a low-delay inductance current sampling circuit. The sampling circuit comprises a sampling circuit core unit, a biasing unit, a differential current generating unit, an RC filtering unit and a sampling voltage generating unit, wherein the sampling circuit core unit comprises a total PMOS power tube and a first PMOS tube which are connected with each other, and the total PMOS power tube is also connected with a second PMOS tube; and the biasing unit comprises a third PMOS tube connected with the first PMOS tube. The circuit only comprises a feedforward path, does not comprise a feedback loop, has higher response speed compared with a closed-loop structure of the traditional SenseFET sampling method, greatly reduces the sampling delay of inductance current, and is suitable for a DC-DC converter with higher switching frequency.

Description

Low-delay inductance current sampling circuit

Technical Field

The utility model relates to the technical field of inductance current sampling integrated circuits, in particular to a low-delay inductance current sampling circuit.

Background

In the boost type DC-DC converter based on current mode control, an inductor current sampling circuit is used for sampling information of an inductor current, converting the information into a voltage signal and sending the voltage signal into a PWM comparator, and generating a duty ratio signal to control on and off of a power tube after comparing the voltage signal with an output signal VC of an error amplifier. However, at high switching frequencies, the delay of conventional current sampling circuits will cause the converter to fail to operate properly, and therefore a low sampling delay inductor current sampling circuit is required.

The SenseFET sampling method is currently the most commonly used inductor current detection method. The SenseFET sampling method utilizes the structure of a current mirror to mirror the current flowing through a power tube according to a certain proportion, and in the actual circuit design, an operational amplifier is usually introduced to clamp the drain terminal voltage of the power tube and a sampling tube, so that the channel length modulation effect is eliminated, and the accuracy of the current mirror is improved. Because the operational amplifier is introduced, the sampling circuit belongs to a closed loop system, the bandwidth of an amplifier is limited, the response speed of the circuit is slow, the sampling delay of the inductive current is high, and the sampling delay is usually tens of ns or even 100ns, and the sampling circuit is not suitable for a boost DC-DC converter with high switching frequency.

Disclosure of Invention

This section is intended to outline some aspects of embodiments of the utility model and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the utility model and in the title of the utility model, which may not be used to limit the scope of the utility model.

The utility model provides a boost DC-DC converter and aims to solve the problem that the converter cannot work normally due to the fact that the traditional SenseFET sampling method is large in delay under the condition of high switching frequency.

It is therefore an object of the present utility model to provide a low delay inductor current sampling circuit, which aims to: compared with a closed loop structure of a SenseFET sampling method, the sampling delay of the inductive current is reduced.

In order to solve the technical problems, the utility model provides the following technical scheme: the low-delay inductive current sampling circuit comprises a sampling circuit core unit, a bias unit, a differential current generating unit, an RC filtering unit and a sampling voltage generating unit, wherein the sampling circuit core unit comprises a total PMOS power tube and a first PMOS tube which are connected with each other, and the total PMOS power tube is also connected with a second PMOS tube; the bias unit comprises a third PMOS tube connected with the first PMOS tube, the third PMOS tube is connected with a fourth PMOS tube, the other end of the third PMOS tube is connected with a fifth PMOS tube, the fourth PMOS tube is connected with a sixth PMOS tube, and the fifth PMOS tube and the sixth PMOS tube are respectively connected with a seventh PMOS tube and an eighth PMOS tube; the difference current generating unit comprises a first NMOS tube and a second NMOS tube which form a current mirror structure, wherein the first NMOS tube is connected with the fifth PMOS tube, and the second NMOS tube is connected with the sixth PMOS tube; the RC filter unit comprises a filter resistor connected with the second PMOS tube and the seventh PMOS tube; and the sampling voltage generating unit is connected with the biasing unit and comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube and a twelfth PMOS tube, wherein the eleventh PMOS tube is connected with the eighth PMOS tube, the twelfth PMOS tube is connected with a sampling resistor RSENSE, and the other side of the sampling resistor RSENSE is connected with the second NMOS tube.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: the grid electrode of the total PMOS power tube is connected with the grid electrodes of the first PMOS tube and the second PMOS tube, the drain electrode of the total PMOS power tube is connected with the source electrode of the first PMOS tube, and the source electrode of the total PMOS power tube is connected with the source electrode of the second PMOS tube.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the grid electrode of the seventh PMOS tube, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube and the grid electrode of the eighth PMOS tube, the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the source electrode of the sixth PMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube and is connected with the drain electrode of the eleventh PMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the fifth PMOS tube and is connected with the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: one end of the filter resistor is connected to the output voltage, the other end of the filter resistor is connected with a filter capacitor, the source electrode of the seventh PMOS tube is connected with the filter capacitor, and the other end of the filter capacitor is grounded; the grid electrode of the seventh PMOS tube is connected with the drain electrode of the fourth PMOS tube and is connected to the source electrode of the eighth PMOS tube, the grid electrode of the eighth PMOS tube is connected with the drain electrode of the eleventh PMOS tube and is connected to one end of a constant current source, and the other end of the constant current source is grounded.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: the grid electrode of the ninth PMOS tube is connected with the source electrode of the eleventh PMOS tube and is connected with the grid electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube and the source electrode of the tenth PMOS tube are connected with the input voltage, the drain electrode of the tenth PMOS tube is connected with the source electrode of the twelfth PMOS tube, and the grid electrode of the eleventh PMOS tube is connected with the drain electrode of the eighth PMOS tube; the grid electrode of the eleventh PMOS tube is also connected with the grid electrode of the twelfth PMOS tube, the drain electrode of the twelfth PMOS tube is connected to one end of the sampling resistor, and the other end of the sampling resistor is grounded.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: the channel length and the width-to-length ratio of the first PMOS tube and the second PMOS tube are the same, and the width-to-length ratio of the total PMOS power tube is N1 times that of the first PMOS tube and the second PMOS tube; the channel length and the width-to-length ratio of the third PMOS tube and the fourth PMOS tube are the same, and the width-to-length ratio is N2 times that of the seventh PMOS tube.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: the channel lengths and the width-to-length ratios of the fifth PMOS tube and the sixth PMOS tube are the same, the width-to-length ratio is N2 times that of the eighth PMOS tube, the channel lengths and the width-to-length ratios of the ninth PMOS tube and the tenth PMOS tube are the same, and the channel lengths and the width-to-length ratios of the eleventh PMOS tube and the twelfth PMOS tube are the same.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: the total PMOS power tube is connected with a driving signal, and the drain electrode of the total PMOS power tube is connected with a switch node of the boost DC-DC converter.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: the source electrode of the total PMOS power tube is connected to the output voltage.

As a preferred embodiment of the low-delay inductor current sampling circuit of the present utility model, the method further comprises: the input voltage is the supply voltage of the lithium battery, and a typical voltage value of the input voltage is 3.6V.

The utility model has the beneficial effects that: the utility model provides a low-delay inductance current sampling circuit, which only comprises a feedforward path and does not comprise a feedback loop, compared with a closed-loop structure of the traditional SenseFET sampling method, the response speed of the circuit is faster, the inductance current sampling delay is greatly reduced, and the low-delay inductance current sampling circuit is suitable for a DC-DC converter with higher switching frequency.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

fig. 1 is a schematic diagram of a low-delay inductor current sampling circuit according to the present utility model.

Fig. 2 is a circuit diagram of a low-delay inductor current sampling circuit according to the present utility model.

Fig. 3 is a circuit diagram of a sampling circuit core unit 100 of a low-delay inductor current sampling circuit according to the present utility model.

Fig. 4 is a circuit diagram of a bias unit 200 of a low-delay inductor current sampling circuit according to the present utility model.

Fig. 5 is a second circuit diagram of a bias unit 200 of a low-delay inductor current sampling circuit according to the present utility model.

Fig. 6 is a circuit diagram of a differential current generating unit 300 of a low-delay inductor current sampling circuit according to the present utility model.

Fig. 7 is a circuit diagram of an RC filter 400 of a low delay inductor current sampling circuit according to the present utility model.

Fig. 8 is a circuit diagram of a sampling voltage generation unit 500 of a low-delay inductor current sampling circuit according to the present utility model.

Detailed Description

In order that the above-recited objects, features and advantages of the present utility model will become more readily apparent, a more particular description of the utility model will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model, but the present utility model may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present utility model is not limited to the specific embodiments disclosed below.

Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the utility model. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

Further, in describing the embodiments of the present utility model in detail, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of description, and the schematic is only an example, which should not limit the scope of protection of the present utility model. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

Example 1

Referring to fig. 1 to 2, a low-delay inductor current sampling circuit according to a first embodiment of the present utility model is provided, and the circuit includes a sampling circuit core unit 100, a bias unit 200, a differential current generating unit 300, an rc filtering unit 400, and a sampling voltage generating unit 500. The sampling circuit core unit 100 includes a total PMOS power transistor MP and a first PMOS transistor MP1, which are connected to each other, and the total PMOS power transistor MP is further connected to a second PMOS transistor MP2.

In this embodiment, the bias unit 200 includes a third PMOS transistor MP3 connected to the first PMOS transistor MP1, the third PMOS transistor MP3 is connected to a fourth PMOS transistor MP4, the other end of the third PMOS transistor MP3 is connected to a fifth PMOS transistor MP5, the fourth PMOS transistor MP4 is connected to a sixth PMOS transistor MP6, and the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are respectively connected to a seventh PMOS transistor MP7 and an eighth PMOS transistor MP8.

In this embodiment, the differential current generating unit 300 includes a first NMOS transistor MN1 and a second NMOS transistor MN2 that form a current mirror structure, where the first NMOS transistor MN1 is connected to a fifth PMOS transistor MP5, and the second NMOS transistor MN2 is connected to a sixth PMOS transistor MP 6; the RC filter unit 400 comprises a filter resistor R1 connected with a second PMOS tube MP2 and a seventh PMOS tube MP 7; and a sampling voltage generating unit 500 connected with the bias unit 200, including a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, the eleventh PMOS transistor MP11 being connected with an eighth PMOS transistor MP8, the twelfth PMOS transistor MP12 being connected with a sampling resistor RSENSE, the other side of the sampling resistor RSENSE being connected with a second NMOS transistor MN 2.

In the use process, the sampling circuit core unit 100 generates two paths of differential currents, the PMOS tube MP3, the PMOS tube MP4, the PMOS tube MP5, the PMOS tube MP6, the PMOS tube MP7 and the PMOS tube MP8 in the bias unit 200 form a cam current mirror, the current of the constant current source IB is duplicated to provide bias for the circuit, wherein the differential current generating unit 300 is used for generating the current proportional to the inductance current, the RC filter unit 400 is used for reducing the influence of the output voltage on the sampling circuit, in the embodiment, the PMOS tube MP9, the PMOS tube MP10, the PMOS tube MP11 and the PMOS tube MP12 are used as the cam current mirror, so that the differential current is duplicated, and the differential current flows through the sampling resistor R1 to obtain the final sampling voltage VSENSE.

Example 2

Referring to fig. 1 to 8, a second embodiment of the present utility model is different from the first embodiment in that: further explaining the connection relation of the inductive current sampling circuit with low delay of the my, wherein, the grid electrode of the total PMOS power tube MP is connected with the grid electrodes of the first PMOS tube MP1 and the second PMOS tube MP2, the drain electrode of the total PMOS power tube MP is connected with the source electrode of the first PMOS tube MP1, and the source electrode of the total PMOS power tube MP is connected with the source electrode of the second PMOS tube MP2.

In this embodiment, the drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3, the drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4, the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4 and the gate of the seventh PMOS transistor MP7, the gate of the fifth PMOS transistor MP5 is connected to the gate of the sixth PMOS transistor MP6 and the gate of the eighth PMOS transistor MP8, the drain of the third PMOS transistor MP3 is connected to the source of the fifth PMOS transistor MP5, the drain of the fourth PMOS transistor MP4 is connected to the source of the sixth PMOS transistor MP6, the drain of the third PMOS transistor MP3 is connected to the drain of the first NMOS transistor MN1, the drain of the sixth PMOS transistor MP6 is connected to the drain of the second NMOS transistor MN2 and to the drain of the eleventh PMOS transistor MP11, the gate of the first NMOS transistor MN1 is connected to the drain of the fifth PMOS transistor MP5 and to the gate of the second NMOS transistor MN2, and the source of the first NMOS transistor MN1 is grounded.

One end of the filter resistor R1 is connected with the output voltage VOUT, the other end of the filter resistor R1 is connected with a filter capacitor C, the source electrode of the seventh PMOS tube MP7 is connected with the filter capacitor C, and the other end of the filter capacitor C is grounded; the grid electrode of the seventh PMOS tube MP7 is connected with the drain electrode of the fourth PMOS tube MP4 and is connected to the source electrode of the eighth PMOS tube MP8, the grid electrode of the eighth PMOS tube MP8 is connected with the drain electrode of the eleventh PMOS tube MP11 and is connected to one end of the constant current source IB, and the other end of the constant current source IB is grounded.

In this embodiment, the gate of the ninth PMOS transistor MP9 is connected to the source of the eleventh PMOS transistor MP11 and to the gate of the tenth PMOS transistor MP10, the source of the ninth PMOS transistor MP9 is connected to the input voltage VIN, the other end of the input voltage VIN is connected to the source of the tenth PMOS transistor MP10, the drain of the tenth PMOS transistor MP10 is connected to the source of the twelfth PMOS transistor MP12, and the gate of the eleventh PMOS transistor MP11 is connected to the drain of the eighth PMOS transistor MP 8; the grid electrode of the eleventh PMOS tube MP11 is also connected with the grid electrode of the twelfth PMOS tube MP12, the drain electrode of the twelfth PMOS tube MP12 is connected to one end of a sampling resistor RSENSE, and the other end of the sampling resistor RSENSE is grounded.

In this embodiment, the channel lengths and the width-to-length ratios of the first PMOS transistor MP1 and the second PMOS transistor MP2 are the same, and the total PMOS power transistor MP has a width-to-length ratio N1 times that of the first PMOS transistor MP1 and the second PMOS transistor MP2, where n1=4000; the channel length and the width-to-length ratio of the third PMOS tube MP3 and the fourth PMOS tube MP4 are the same, and the width-to-length ratio is N2 times of that of the seventh PMOS tube MP7, and N2=30.

In this embodiment, the channel lengths and the width-to-length ratios of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are the same, the width-to-length ratio is N2 times that of the eighth PMOS transistor MP8, the channel lengths and the width-to-length ratios of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are the same, and the channel lengths and the width-to-length ratios of the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are the same.

The total PMOS power tube MP is connected with a driving signal P_D, the drain electrode of the total PMOS power tube MP is connected with a switch node SW of the boost DC-DC converter, the source electrode of the total PMOS power tube MP is connected with an output voltage VOUT, an input voltage VIN is a supply voltage of a lithium battery, and a typical voltage value of the input voltage VIN is 3.6V.

The utility model provides a low-delay inductance current sampling circuit, which only comprises a feedforward path and does not comprise a feedback loop, compared with a closed-loop structure of the traditional SenseFET sampling method, the response speed of the circuit is faster, the inductance current sampling delay is greatly reduced, and the low-delay inductance current sampling circuit is suitable for a DC-DC converter with higher switching frequency.

The rest of the structure is the same as that of embodiment 1.

Example 3

Referring to fig. 1 to 2, a second embodiment of the present utility model is different from the first embodiment in that: the principle of the inductor current sampling circuit provided by the utility model is shown in fig. 2, and the circuit only comprises a feedforward path and does not comprise a feedback loop. The PMOS power transistors MP1 and MP2 are represented by resistors RON, and N1 times RON, which can be obtained according to loop 1 and loop 2 in fig. 2:

|V _GS3 |+I _S1 ·N ₁ R _ON ＝|V _GS4 |+I _S2 ·N ₁ R _ON +I _P ·R _ON (S1)

further reduction can be given by:

according to the formula (S2), a sampling current which is approximately in linear relation with the inductance current can be obtained by eliminating the second term on the right side of the formula. NMOS transistors MN1 and MN2 form a current mirror structure, and the mirror proportion is 1:1. The PMOS tubes MP9 and MP10 form a current mirror structure, and the mirror proportion is 1:1. The difference value of two paths of currents IS1 and IS2 flows through a sampling resistor Rsense through a current mirror image, so that a final sampling voltage VSENSE can be obtained, and the expression IS as follows:

where RSENSE and N1 are constants, it can be seen that the sampling voltage VSENSE is linear with the current IP flowing through the PMOS transistor.

The specific circuit of the inductor current sampling circuit is shown in fig. 3, wherein the width-to-length ratio of the PMOS power transistor MP is N1 times of the width-to-length ratio of the PMOS power transistors MP1 and MP2. The on-resistance of the PMOS can be expressed as:

thus, the on-resistance of MP1 and MP2 is N1 times that of MP. MP3 to MP8 form a cascode current mirror structure, thereby improving the accuracy of current mirror image. The aspect ratios of MP3, MP4 and MP5, MP6 are N2 times that of MP7 and MP8, respectively. The filter circuit formed by the resistor R1 and the capacitor C can reduce the influence of output voltage noise on the sampling circuit. MP9, MP10, MP11, MP12 form a cascode current mirror, the difference value of the currents IS1 and IS2 IS mirrored in equal proportion, and the sampling voltage VSENSE IS obtained by flowing through a sampling resistor RSENSE.

Further, compared to embodiment 1, when the driving signal p_d of the PMOS power transistor IS at high level, MP1 and MP2 are turned off, IS1 and IS2 are 0, and vsense IS 0. When the driving signal p_d of the PMOS power transistor is at low level, MP1 and MP2 are turned on. Increasing the aspect ratio of MP3 and MP4 can make the gate-source voltages of MP3 and MP4 approximately equal, the second term on the right of equation (S2) is approximately zero, and the obtained sampling voltage VSENSE is in a linear relationship with the inductor current IP. Because the circuit has no feedback loop, the circuit belongs to an open loop system, the response speed is faster, and the sampling delay of the inductive current is lower.

The rest of the structure is the same as that of embodiment 2.

It should be noted that the above embodiments are only for illustrating the technical solution of the present utility model and not for limiting the same, and although the present utility model has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present utility model may be modified or substituted without departing from the spirit and scope of the technical solution of the present utility model, which is intended to be covered in the scope of the claims of the present utility model.

Claims (10)

1. A low delay inductor current sampling circuit, characterized by: comprising the steps of (a) a step of,

the sampling circuit core unit (100) comprises a total PMOS power tube (MP) and a first PMOS tube (MP 1) which are connected with each other, wherein the total PMOS power tube (MP) is also connected with a second PMOS tube (MP 2);

the bias unit (200) comprises a third PMOS tube (MP 3) connected with the first PMOS tube (MP 1), wherein the third PMOS tube (MP 3) is connected with a fourth PMOS tube (MP 4), the other end of the third PMOS tube (MP 3) is connected with a fifth PMOS tube (MP 5), the fourth PMOS tube (MP 4) is connected with a sixth PMOS tube (MP 6), and the fifth PMOS tube (MP 5) and the sixth PMOS tube (MP 6) are respectively connected with a seventh PMOS tube (MP 7) and an eighth PMOS tube (MP 8);

the differential current generation unit (300) comprises a first NMOS tube (MN 1) and a second NMOS tube (MN 2) which form a current mirror structure, wherein the first NMOS tube (MN 1) is connected with the fifth PMOS tube (MP 5), and the second NMOS tube (MN 2) is connected with the sixth PMOS tube (MP 6);

the RC filter unit (400) comprises a filter resistor (R1) connected with the second PMOS tube (MP 2) and the seventh PMOS tube (MP 7); the method comprises the steps of,

the sampling voltage generating unit (500) is connected with the biasing unit (200) and comprises a ninth PMOS tube (MP 9), a tenth PMOS tube (MP 10), an eleventh PMOS tube (MP 11) and a twelfth PMOS tube (MP 12), wherein the eleventh PMOS tube (MP 11) is connected with the eighth PMOS tube (MP 8), the twelfth PMOS tube (MP 12) is connected with a sampling Resistor (RSENSE), and the other side of the sampling Resistor (RSENSE) is connected with the second NMOS tube (MN 2).

2. The low-delay inductor current sampling circuit of claim 1, wherein: the grid electrode of the total PMOS power tube (MP) is connected with the grid electrodes of the first PMOS tube (MP 1) and the second PMOS tube (MP 2), the drain electrode of the total PMOS power tube (MP) is connected with the source electrode of the first PMOS tube (MP 1), and the source electrode of the total PMOS power tube (MP) is connected with the source electrode of the second PMOS tube (MP 2).

3. The low-delay inductor current sampling circuit of claim 2, wherein: the drain electrode of the first PMOS tube (MP 1) is connected with the source electrode of the third PMOS tube (MP 3), the drain electrode of the second PMOS tube (MP 2) is connected with the source electrode of the fourth PMOS tube (MP 4), the grid electrode of the third PMOS tube (MP 3) is connected with the grid electrode of the fourth PMOS tube (MP 4) and the grid electrode of the seventh PMOS tube (MP 7), the grid electrode of the fifth PMOS tube (MP 5) is connected with the grid electrode of the sixth PMOS tube (MP 6) and the grid electrode of the eighth PMOS tube (MP 8), the drain electrode of the third PMOS tube (MP 3) is connected with the source electrode of the fifth PMOS tube (MP 5), the drain electrode of the fourth PMOS tube (MP 4) is connected with the drain electrode of the first NMOS tube (MN 1), the drain electrode of the sixth PMOS tube (MP 6) is connected with the drain electrode of the second NMOS tube (MN 2) and is connected with the drain electrode of the eleventh NMOS tube (MP 11), the drain electrode of the first NMOS tube (MN 1) is connected with the drain electrode of the second NMOS tube (MN 2), and the drain electrode of the first NMOS tube (MN 1) is connected with the drain electrode of the second NMOS tube (MN 2) is connected with the ground.

4. A low delay inductor current sampling circuit according to claim 3, characterized in that: one end of the filter resistor (R1) is connected to the output Voltage (VOUT), the other end of the filter resistor is connected with a filter capacitor (C), a source electrode of the seventh PMOS tube (MP 7) is connected with the filter capacitor (C), and the other end of the filter capacitor (C) is grounded;

the grid electrode of the seventh PMOS tube (MP 7) is connected with the drain electrode of the fourth PMOS tube (MP 4) and is connected to the source electrode of the eighth PMOS tube (MP 8), the grid electrode of the eighth PMOS tube (MP 8) is connected with the drain electrode of the eleventh PMOS tube (MP 11) and is connected to one end of a constant current source (IB), and the other end of the constant current source (IB) is grounded.

5. The low-delay inductor current sampling circuit of claim 4, wherein: the grid electrode of the ninth PMOS tube (MP 9) is connected with the source electrode of the eleventh PMOS tube (MP 11) and is connected with the grid electrode of the tenth PMOS tube (MP 10), the source electrodes of the ninth PMOS tube (MP 9) and the tenth PMOS tube (MP 10) are connected with the input Voltage (VIN), the drain electrode of the tenth PMOS tube (MP 10) is connected with the source electrode of the twelfth PMOS tube (MP 12), and the grid electrode of the eleventh PMOS tube (MP 11) is connected with the drain electrode of the eighth PMOS tube (MP 8);

the grid electrode of the eleventh PMOS tube (MP 11) is also connected with the grid electrode of the twelfth PMOS tube (MP 12), the drain electrode of the twelfth PMOS tube (MP 12) is connected to one end of the sampling Resistor (RSENSE), and the other end of the sampling Resistor (RSENSE) is grounded.

6. The low-delay inductor current sampling circuit of claim 5, wherein: the channel length and the width-to-length ratio of the first PMOS tube (MP 1) and the second PMOS tube (MP 2) are the same, and the width-to-length ratio of the total PMOS power tube (MP) is N1 times of that of the first PMOS tube (MP 1) and the second PMOS tube (MP 2);

the channel length and the width-to-length ratio of the third PMOS tube (MP 3) and the fourth PMOS tube (MP 4) are the same, and the width-to-length ratio is N2 times that of the seventh PMOS tube (MP 7).

7. The low-delay inductor current sampling circuit of claim 6, wherein: the channel length and the width-to-length ratio of the fifth PMOS tube (MP 5) and the sixth PMOS tube (MP 6) are the same, the width-to-length ratio is N2 times that of the eighth PMOS tube (MP 8), the channel length and the width-to-length ratio of the ninth PMOS tube (MP 9) and the tenth PMOS tube (MP 10) are the same, and the channel length and the width-to-length ratio of the eleventh PMOS tube (MP 11) and the twelfth PMOS tube (MP 12) are the same.

8. The low-delay inductor current sampling circuit of claim 7, wherein: the total PMOS power tube (MP) is connected with a driving signal (P_D), and the drain electrode of the total PMOS power tube (MP) is connected with a switch node (SW) of the boost DC-DC converter.

9. The low-delay inductor current sampling circuit of claim 8, wherein: the source of the total PMOS power transistor (MP) is connected to the output Voltage (VOUT).

10. The low-delay inductor current sampling circuit of claim 9, wherein: the input Voltage (VIN) is a supply voltage of a lithium battery, and a typical voltage value of the input Voltage (VIN) is 3.6V.