CN113885649B - Low-dropout linear voltage regulator - Google Patents
Low-dropout linear voltage regulator Download PDFInfo
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- CN113885649B CN113885649B CN202111124095.4A CN202111124095A CN113885649B CN 113885649 B CN113885649 B CN 113885649B CN 202111124095 A CN202111124095 A CN 202111124095A CN 113885649 B CN113885649 B CN 113885649B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application discloses low dropout linear voltage regulator includes: the power amplifier comprises a power adjusting tube, an error amplifier, a transconductance sampling circuit, a variable resistance circuit and a compensation capacitor. The transconductance sampling circuit is connected with the control end of the power adjusting tube and used for obtaining sampling current representing transconductance of the power adjusting tube, the variable resistance circuit is connected with the transconductance sampling circuit and is suitable for obtaining variable resistance inversely related to the transconductance of the power adjusting tube according to the sampling current, one end of the compensation capacitor is connected with the variable resistance circuit, the other end of the compensation capacitor is connected with the control end of the power adjusting tube and forms a dynamic compensation network with the variable resistance circuit, and the unit gain bandwidth of the system is always in a set interval range regardless of change of output current, so that a higher phase margin can be obtained, and higher stability in a full-load large range can be achieved.
Description
Technical Field
The invention relates to the technical field of linear regulators, in particular to a low-dropout linear regulator.
Background
A low dropout linear regulator (Low Dropout Regulator, LDO) converts an unstable input voltage into an adjustable dc output voltage for use as a power supply for other systems. Since the linear voltage regulator has the characteristics of simple structure, small static power consumption, small output voltage ripple, etc., the linear voltage regulator is often used for on-chip power management of a chip of a mobile consumer electronic device.
Fig. 1 is a schematic circuit diagram of a low dropout linear regulator of the prior art. As shown in fig. 1, the low dropout linear regulator 100 includes a reference voltage VREF, a feedback network, an error amplifier 110, a voltage buffer BUFF, a power regulator tube Mpout, a load capacitor Co, and the like. The power regulating tube Mpout is connected between the power input end and the power output end and is used for providing an output voltage Vout for a backward load according to an input voltage Vin provided by the power input end. The feedback network formed by the resistor R1 and the resistor R2 is connected between the power output end and the reference ground, and the common end of the resistor R1 and the resistor R2 is used for providing the feedback voltage VFB of the output voltage Vout. The error amplifier 110 has an inverting input terminal for receiving the reference voltage VREF, a non-inverting input terminal for receiving the feedback voltage VFB, and an output terminal connected to the control terminal of the power adjustment tube Mpout via a voltage buffer BUFF. The error amplifier 110 is used for comparing the feedback voltage VFB with the reference voltage VREF and adjusting the source-drain voltage drop of the power adjustment tube Mpout according to the voltage difference therebetween, so as to stabilize the output voltage Vout.
In order to maintain the stability of the LDO, frequency compensation must be introduced in the circuit, as shown in fig. 1, with compensation resistor Rc, compensation capacitor Cc and capacitor Cp being used to form a dynamic frequency compensation network. The compensation resistor Rc and the compensation capacitor Cc are connected between the power input terminal and the output terminal of the error amplifier 110, the capacitor Cp is connected between the power input terminal and the common terminal of the compensation resistor Rc and the compensation capacitor Cc, P1 is a primary pole, P2 is a secondary primary pole, P3 is a parasitic high-frequency pole, and Z1 is a zero.
Fig. 2 shows a system baud diagram of a low dropout linear regulator of the prior art. Where A1 is the gain of the error amplifier 110, A2 is the gain of the second stage amplifying circuit, the total gain of the system is a1×a2, and the approximate frequency points of each pole-zero and unity gain bandwidth are shown in the figure. As shown in fig. 2, when the attenuation of A2 is 1, the total gain a1=a2=a1 of the system is obtained, and the gain a1=gm×rc is obtained, where gm is the transconductance of the error amplifier 110, and Rc is the resistance of the compensation resistor Rc. As the frequency continues to increase, the total gain a1×a2 of the system continues to attenuate, at this time, the system can be simply approximated to a single-pole system with the gain A2 unit gain bandwidth as the main pole point and the gain gm×rc, so that the overall unit gain bandwidth bw=gm/co×gm×rc can be obtained, where Gm is the transconductance of the power regulator tube Mpout and Co is the capacitance value of the load capacitor Co. It is desirable to design the unity gain bandwidth between zero Z1 and parasitic high frequency pole P3 by:
BW 2 =(Gm/Co*gm*Rc) 2 ＝Z1*P3 (1)
equation (2) can be derived from equation (1):
thus, the zero point Z1 can offset the influence of the secondary main pole point P2, and the system can be simply regarded as a single pole point system, so that a higher phase margin (phase margin) is obtained.
Fig. 3 is a schematic circuit diagram of a dynamic compensation resistor of the prior art. The prior art performs compensation resistance Rc by sampling the output current of the LDO to dynamically compensate the system. As shown in fig. 3, the first terminals of the transistor Mp1 and the transistor Mp2 are connected to the power supply voltage, the control terminals of the two are connected to each other and to the second terminal of the transistor Mp2, thereby forming a current mirror, the second terminal of the transistor Mp1 is connected to the first terminal of the compensation capacitor Cc, and the second terminal of the transistor Mp2 is connected to the sampling current Iout/K of the output current Iout of the LDO. The transistor Mp1 operates in the adjustable resistance region and thus can function as a variable resistor. The relationship between the resistance Rc and the power regulator tube Mpout can be obtained from fig. 3 as follows:
substituting formula (5) into BW formula can result in:
the unit gain bandwidth of the system is almost fixed and does not change along with the change of the output current, while the Z1P 1 can change greatly along with the change of the output current, if the change range of the output current is large, the unit gain bandwidth can be distributed outside the interval of Z1-P3, so that the stability of the system is influenced, and therefore, the compensation mode in the prior art can hardly ensure the stability of the LDO in a large range in the full load range.
Therefore, improvements to existing low dropout regulators are needed to ensure the stability of LDOs over the full load range.
Disclosure of Invention
In view of the above problems, the present invention is directed to a low dropout linear regulator, which uses the transconductance of a sampling power regulator to replace the conventional sampling output current to perform frequency compensation, so as to ensure the stability of the LDO in the full load range.
According to an embodiment of the present invention, there is provided a low dropout linear regulator including: the power adjusting tube is connected in series between the input voltage and the output voltage; the output end of the error amplifier is connected to the control end of the power adjusting tube through a voltage buffer and is suitable for driving the power adjusting tube according to the voltage difference between the feedback voltage of the output voltage and the reference voltage; the transconductance sampling circuit is connected with the control end of the power adjusting tube and is used for obtaining sampling current representing transconductance of the power adjusting tube; the variable resistance circuit is connected with the transconductance sampling circuit and is suitable for obtaining a variable resistance inversely related to the transconductance of the power adjusting tube according to the sampling current; and one end of the compensation capacitor is connected with the variable resistance circuit, and the other end of the compensation capacitor is connected with the control end of the power adjusting tube so as to form a dynamic compensation network with the variable resistance circuit.
Optionally, the transconductance sampling circuit includes: the first transistor is connected with the input voltage at a first end, the control end of the first transistor is connected with the control end of the power adjusting tube, and the first transistor outputs a first current at a second end by sampling the current flowing through the power adjusting tube; the first end of the second transistor is connected with the input voltage, the control end of the second transistor is connected with the control end of the power adjustment tube through a voltage source, and the second transistor outputs a second current at the second end by sampling the current flowing through the power adjustment tube; and a current mirror circuit having a first current port connected to the second terminal of the first transistor, a second current port connected to the second terminal of the second transistor, and a ground terminal, the current mirror being configured to output the sampling current at the first current port according to a current difference between the first current and the second current.
Optionally, the current mirror circuit includes a third transistor and a fourth transistor, wherein a first end of the third transistor is connected as the first current port to a second end of the first transistor, a first end of the fourth transistor is connected as the second current port to a second end of the second transistor, control ends of the third transistor and the fourth transistor are connected to each other and are both connected to the first end of the fourth transistor, and a second end of the third transistor and the fourth transistor are connected as a ground end to a reference ground.
Optionally, the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.
Optionally, the variable resistance circuit includes a fifth transistor and a sixth transistor, where first ends of the fifth transistor and the sixth transistor are both connected to a power supply voltage, a second end of the fifth transistor is connected to the sampling current, a control end of the sixth transistor is connected to the control end of the fifth transistor, and is connected to the second end of the fifth transistor, and a second end of the sixth transistor is connected to the first end of the compensation capacitor, where the sixth transistor operates in an adjustable resistance region and can be used as a variable resistor.
Optionally, the fifth transistor and the sixth transistor are PMOS transistors.
Optionally, the low dropout linear regulator further includes a first resistor and a second resistor connected in series between the output voltage and a reference ground, wherein a feedback network formed by the first resistor and the second resistor is used for obtaining a feedback voltage of the output voltage.
The low dropout linear voltage regulator of the embodiment of the invention comprises a power adjusting tube, an error amplifier, a transconductance sampling circuit, a variable resistance circuit and a compensation capacitor. The output end of the error amplifier is connected to the control end of the power adjusting tube through a voltage buffer, the error amplifier is suitable for driving the power adjusting tube according to the voltage difference between the feedback voltage of the output voltage and the reference voltage, the transconductance sampling circuit is connected with the control end of the power adjusting tube and used for obtaining sampling current representing the transconductance of the power adjusting tube, the variable resistance circuit is connected with the transconductance sampling circuit and is suitable for obtaining a variable resistance inversely related to the transconductance of the power adjusting tube according to the sampling current, one end of the compensation capacitor is connected with the variable resistance circuit, and the other end of the compensation capacitor is connected with the control end of the power adjusting tube so as to form a dynamic compensation network with the variable resistance circuit. Compared with the mode of sampling output current in the prior art, the low-dropout linear voltage regulator obtains a variable compensation resistance through sampling the transconductance of the power adjusting tube, and the unit gain bandwidth of the system is always in a set interval range no matter how the output current changes, so that a higher phase margin can be obtained, and higher stability in a large range of full load can be realized.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic circuit diagram of a prior art low dropout linear regulator;
FIG. 2 is a system Bode diagram of a prior art low dropout linear regulator;
FIG. 3 is a schematic circuit diagram of a dynamic compensation resistor of the prior art;
FIG. 4 is a schematic circuit diagram of a low dropout linear regulator according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a transconductance sampling circuit and a variable resistance circuit of a low dropout linear regulator according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
In the present application, the transistor may be a PMOS (Metal-Oxide-Semiconductor Field-Effect Transistor) or NMOS. The first end, the second end and the control end of the PMOS tube are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the NMOS tube are respectively a drain electrode, a source electrode and a grid electrode.
The invention will be further described with reference to the drawings and examples.
Fig. 4 is a schematic circuit diagram of a low dropout linear regulator according to an embodiment of the present invention. As shown in fig. 4, the low dropout linear regulator 200 includes a power regulator tube Mpout, a load capacitor Co, and a control circuit integrated in the same integrated circuit chip. The power regulating tube Mpout is the main output tube of the chip and is connected between the power input end and the output end. The power regulator tube Mpout is, for example, a PMOS tube, and has a first end receiving the input voltage Vin and a second end providing the output voltage Vout to the backward load. The load capacitance Co is connected between the power supply output and the reference ground.
In other embodiments, the power regulator tube Mpout may be selected from NPN darlington tube, NPN bipolar transistor, PNP bipolar transistor, or NMOS tube.
The control circuit is used for driving the power adjustment tube Mpout so that the power adjustment tube Mpout can provide output current for a later-stage load. Specifically, the control circuit includes an error amplifier 210, a voltage buffer BUFF, a transconductance sampling circuit 220, a variable resistance circuit 230, and a compensation capacitor Cc.
The error amplifier 210 controls the on-resistance between the first terminal and the second terminal of the power regulator tube Mpout by controlling the voltage of the control terminal of the power regulator tube Mpout, thereby controlling the source-drain voltage drop of the power regulator tube Mpout.
Further, the error amplifier 210 has a non-inverting input terminal for receiving the feedback voltage VFB of the output voltage Vout, an inverting input terminal for receiving the reference voltage VREF, and an output terminal connected to the control terminal of the power regulator tube Mpout via the voltage buffer BUFF. The error amplifier 210 compares the feedback voltage VFB with the reference voltage VREF, and when the feedback voltage VFB and the reference voltage VREF deviate, the error amplifier 210 amplifies the deviation and then controls the source-drain voltage drop of the power regulator tube Mpout. In the present embodiment, when the output voltage Vout decreases, the voltage difference between the feedback voltage VFB and the reference voltage VREF increases, so that the voltage applied to the control terminal of the power adjustment tube Mpout increases, the on-resistance between the first terminal and the second terminal of the power adjustment tube Mpout decreases, and the voltage drop across the power adjustment tube Mpout decreases, thereby increasing the voltage at the output terminal of the low dropout linear regulator 200, so that the output voltage Vout returns to a normal level.
In other embodiments of the present invention, the control circuit further includes a feedback network connected between the output terminal and the reference ground, and the error amplifier 210 controls the source-drain voltage drop of the power regulator tube Mpout according to the voltage difference between the feedback voltage provided by the feedback network and the reference voltage. As an example, the control circuit of the low dropout linear regulator 200 includes a resistor R1 and a resistor R2 connected in series between the output terminal of the power adjustment tube Mpout and the reference ground, and an intermediate node of the resistor R1 and the resistor R2 is used to provide the feedback voltage VFB of the output voltage Vout.
The transconductance sampling circuit 220 Is connected to the control terminal of the power adjustment tube Mpout, and Is configured to obtain a sampling current Is that characterizes the transconductance Gm of the power adjustment tube.
The variable resistance circuit 230 Is connected to the transconductance sampling circuit 220 and Is adapted to obtain a variable resistance inversely related to the transconductance Gm of the power regulator tube Mpout based on the sampling current Is.
One end of the compensation capacitor Cc is connected to the variable resistance circuit 230, and the other end is connected to the control end of the power adjustment tube Mpout, so as to form a dynamic compensation network with the variable resistance circuit 230.
Compared with the mode of sampling output current in the prior art, the low-dropout linear voltage regulator 200 of the invention obtains a variable compensation resistance through the transconductance of the sampling power adjusting tube Mpout, thereby realizing the frequency compensation of the system, no matter how the output current Iout changes, the unit gain bandwidth of the system is always in a set interval range, thereby obtaining a higher phase margin and realizing higher stability in a full-load large range.
Fig. 5 is a schematic circuit diagram of a transconductance sampling circuit and a variable resistance circuit of a low dropout linear regulator according to an embodiment of the present invention.
As shown in fig. 5, the transconductance sampling circuit 220 includes transistors Mp1 and Mp2, transistors Mn1 and Mn2, and a voltage source 201. The first end of the transistor Mp1 is connected to the input voltage Vin, the control end is connected to the control end of the power adjustment tube Mp out, and the transistor Mp1 samples the current flowing through the power adjustment tube Mp out to output the first current I1 at the second end. The first end of the transistor Mp2 is connected to the input voltage Vin, the control end is connected to the control end of the power adjustment tube Mp out through the voltage source 201, and the transistor Mp2 samples the current flowing through the power adjustment tube Mp out to output the second current I2 at the second end. The transistors Mn1 and Mn2 constitute a current mirror circuit, the first terminal of the transistor Mn1 is connected as a first current port to the second terminal of the transistor Mp1, the first terminal of the transistor Mn2 is connected as a second current port to the second terminal of the transistor Mp2, the control terminals of the transistors Mn1 and Mn2 are connected to each other and to the first terminal of the transistor Mn2, and the second terminals of the transistors Mn1 and Mn2 are connected as ground terminals to the reference ground. Wherein the transistor Mn1 replicates the second current I2 to be different from the first current I1 through the transistor Mn2 and outputs the sampling current Is at the first current port according to the current difference therebetween.
The variable resistance circuit 230 includes transistors Mp3 and Mp4, the first terminals of the transistors Mp3 and Mp4 are connected to the power supply voltage Vcc, the second terminal of the transistor Mp3 Is connected to the sampling current Is, the control terminal of the transistor Mp4 Is connected to the control terminal of the transistor Mp3 and to the second terminal of the transistor Mp3, and the second terminal of the transistor Mp4 Is connected to the first terminal of the compensation capacitor Cc, wherein the transistor Mp4 operates in an adjustable resistance region and can be used as a variable compensation resistance Rc.
In the above embodiment, the transistors Mp1 to Mp4 are PMOS transistors, and the transistors Mn1 and Mn2 are NMOS transistors.
As can be seen from the above description, the sampling current Is the current difference between the first current I1 and the second current I2, and thus can be obtained:
Is∝ΔV*Gm (7)
where Δv is a constant voltage provided by the voltage source 201, and Gm is the transconductance of the power regulator tube Mpout. Can be obtained according to the formula (7)
Thus, no matter how the output current of the low dropout linear voltage regulator changes, the BW of the system 2 ＝(Gm/Co*gm*Rc) 2 The unit gain bandwidth BW of the system can be ensured to be always within the interval range of Z1 to P3, so that the system can obtain a higher phase margin, and higher stability in the full load range is realized.
In summary, the low dropout linear regulator according to the embodiment of the present invention includes: the power amplifier comprises a power adjusting tube, an error amplifier, a transconductance sampling circuit, a variable resistance circuit and a compensation capacitor. The output end of the error amplifier is connected to the control end of the power adjusting tube through a voltage buffer, the error amplifier is suitable for driving the power adjusting tube according to the voltage difference between the feedback voltage of the output voltage and the reference voltage, the transconductance sampling circuit is connected with the control end of the power adjusting tube and used for obtaining sampling current representing the transconductance of the power adjusting tube, the variable resistance circuit is connected with the transconductance sampling circuit and is suitable for obtaining a variable resistance inversely related to the transconductance of the power adjusting tube according to the sampling current, one end of the compensation capacitor is connected with the variable resistance circuit, and the other end of the compensation capacitor is connected with the control end of the power adjusting tube so as to form a dynamic compensation network with the variable resistance circuit. Compared with the mode of sampling output current in the prior art, the low-dropout linear voltage regulator obtains a variable compensation resistance through sampling the transconductance of the power adjusting tube, and the unit gain bandwidth of the system is always in a set interval range no matter how the output current changes, so that a higher phase margin can be obtained, and higher stability in a large range of full load can be realized.
It should be noted that although the device is described herein as an N-channel or P-channel device, or an N-type or P-type doped region, it will be appreciated by those of ordinary skill in the art that complementary devices may be implemented in accordance with the present invention. It will be appreciated by those of ordinary skill in the art that conductivity type refers to a mechanism by which electrical conduction occurs, such as by hole or electron conduction, so conductivity type does not relate to doping concentration but rather to doping type, such as P-type or N-type. It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when … …" as used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of a start-up action, but rather there may be some small but reasonable delay or delays between it and the reaction action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (20%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described. When used in connection with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.
Furthermore, it should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the following claims.
Claims (6)
1. A low dropout linear regulator comprising:
the power adjusting tube is connected in series between the input voltage and the output voltage;
the output end of the error amplifier is connected to the control end of the power adjusting tube through a voltage buffer and is suitable for driving the power adjusting tube according to the voltage difference between the feedback voltage of the output voltage and the reference voltage;
the transconductance sampling circuit is connected with the control end of the power adjusting tube and is used for obtaining sampling current representing transconductance of the power adjusting tube;
the variable resistance circuit is connected with the transconductance sampling circuit and is suitable for obtaining a variable resistance inversely related to the transconductance of the power adjusting tube according to the sampling current; and
one end of the compensation capacitor is connected with the variable resistance circuit, the other end of the compensation capacitor is connected with the control end of the power adjusting tube through the voltage buffer so as to form a dynamic compensation network with the variable resistance circuit,
wherein, the transconductance sampling circuit includes:
the first transistor is connected with the input voltage at a first end, the control end of the first transistor is connected with the control end of the power adjusting tube, and the first transistor outputs a first current at a second end by sampling the current flowing through the power adjusting tube;
the first end of the second transistor is connected with the input voltage, the control end of the second transistor is connected with the control end of the power adjustment tube through a voltage source, and the second transistor outputs a second current at the second end by sampling the current flowing through the power adjustment tube; and
and a current mirror circuit having a first current port connected to the second terminal of the first transistor, a second current port connected to the second terminal of the second transistor, and a ground terminal, the current mirror being configured to output the sampling current at the first current port according to a current difference between the first current and the second current.
2. The low dropout linear regulator according to claim 1, wherein said current mirror circuit includes a third transistor and a fourth transistor,
wherein a first terminal of the third transistor is connected as the first current port to a second terminal of the first transistor, a first terminal of the fourth transistor is connected as the second current port to a second terminal of the second transistor, control terminals of the third transistor and the fourth transistor are connected to each other and to the first terminal of the fourth transistor, and the second terminals of the third transistor and the fourth transistor are connected as ground terminals to a reference ground.
3. The low dropout linear regulator according to claim 2, wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.
4. The low dropout linear regulator according to claim 1, wherein said variable resistance circuit includes a fifth transistor and a sixth transistor,
the first ends of the fifth transistor and the sixth transistor are connected with a power supply voltage, the second end of the fifth transistor is connected with the sampling current, the control end of the sixth transistor is connected with the control end of the fifth transistor and is connected with the second end of the fifth transistor, the second end of the sixth transistor is connected with the first end of the compensation capacitor,
wherein the sixth transistor operates in the adjustable resistance region and can be used as a variable resistor.
5. The low dropout linear regulator according to claim 4, wherein the fifth transistor and the sixth transistor are PMOS transistors.
6. The low dropout linear regulator according to claim 1, further comprising a first resistor and a second resistor connected in series between said output voltage and a reference ground,
and a feedback network formed by the first resistor and the second resistor is used for obtaining the feedback voltage of the output voltage.
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