CN116974327A

CN116974327A - Linear voltage stabilizer circuit

Info

Publication number: CN116974327A
Application number: CN202210429777.4A
Authority: CN
Inventors: 梁华; 易新敏
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2022-04-22
Filing date: 2022-04-22
Publication date: 2023-10-31

Abstract

The application discloses a linear voltage stabilizer circuit, comprising: a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to the output node; a voltage regulation loop configured to sense a voltage at the output node and to modulate a control signal to cause the power transistor to deliver current to the output node such that the output voltage at the output node is regulated; and a current regulation loop configured to sense a load current flowing through the power transistor and to modulate a control signal to cause the power transistor to output a constant current to the output node; the linear voltage regulator circuit is configured to turn on one of the voltage regulating loop and the current regulating loop based on a comparison result of the load current and the target value, so that when the output load is increased to be heavy load or even overloaded, the secondary pole point inside the LDO is changed into the main pole point through loop switching, and the stability problem of the LDO loop is effectively improved.

Description

Linear voltage stabilizer circuit

Technical Field

The application relates to the technical field of linear regulators, in particular to a linear voltage stabilizer circuit.

Background

In modern electronic products, chips have become an indispensable core element, particularly as integrated circuit manufacturing processes are advanced more and more advanced, and the desire of humans to integrate more complex functions in as limited a Chip area as possible has led to a small System Chip, called System On Chip (SOC), which typically comprises a microprocessor MCU, an analog IP core, a digital IP core, an embedded memory module, an interface module for external communication, a power management module for power supply. In practical chip design, the inside of the SOC chip is often realized by using devices with different withstand voltages (e.g., 1 v/1.5 v/1.8 v/3.3 v/5 v, etc.) according to the requirements of the area, the speed and the power consumption, so that the SOC chip needs to be powered by corresponding power supply voltages.

Most of portable electronic products are powered by a lithium battery as a peripheral power supply, the voltage range of the lithium battery is 2.6V-3.6V, and the lithium battery cannot directly power a low-voltage module, so that different power supply voltages are required to be designed in an SOC chip to power related modules, and the low-dropout linear voltage regulator (Low Dropout Regulator, LDO) is often used for on-chip power management of a chip of mobile consumer electronic equipment due to the characteristics of simple structure, low static power consumption, low output voltage ripple and the like.

Fig. 1 shows a schematic circuit diagram of a conventional linear regulator circuit. As shown in fig. 1, the linear voltage regulator 100 includes a reference voltage module BGR, an error amplifier EA, a power transistor MP, voltage dividing resistors R1 and R2, and a compensation capacitor C1. To improve loop stability of the circuit, conventional LDO outputs typically require off-chip capacitance, resulting in reduced chip integration (increased PAD pins) and increased peripheral cost. The off-chip capacitor-free LDO has the problems of poor transient response and unstable loop due to the reduction of the capacitance, and can cause the phenomenon of undershoot or overshoot of LDO output when the LDO jumps from light load to heavy load or even overcurrent occurs.

Disclosure of Invention

In view of the above problems, an object of the present application is to provide a linear voltage regulator circuit with current foldback current limiting and main pole point adaptive switching, which can limit load current while ensuring loop stability without an internal compensation capacitor.

According to an embodiment of the present application, there is provided a linear voltage regulator circuit including: a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to the output node; a voltage regulation loop configured to sense a voltage at the output node and to modulate the control signal to cause the power transistor to deliver current to the output node such that an output voltage at the output node is regulated; and a current regulation loop configured to sense a load current flowing through the power transistor and to modulate the control signal so that the power transistor outputs a constant current to the output node; wherein the linear regulator circuit is configured to turn on one of the voltage regulation loop or the current regulation loop based on a comparison of the load current to a target value.

Optionally, the linear voltage regulator circuit is configured to: opening the voltage regulation loop and closing the current regulation loop if the load current does not reach the target value; and opening the current regulation loop and closing the voltage regulation loop if the load current reaches the target value.

Optionally, the current regulation loop is a current limiting circuit with a current foldback function.

Optionally, the voltage regulation loop includes: a differential input circuit having a first input configured to receive a feedback voltage at the output node and a second input configured to receive a reference voltage; and a first gain amplification circuit having an input coupled to an output of the differential input circuit and an output configured to generate the control signal for application to the control terminal of the power transistor.

Optionally, the voltage regulation loop further comprises: a first bias circuit coupled between a first stage supply voltage and ground potential, configured to provide a first bias current to the differential input circuit; and a feedback resistor network coupled between the output node and ground potential, configured to provide the feedback voltage to the differential input circuit.

Optionally, the differential input circuit further has a power supply terminal configured to receive a first stage power supply voltage and a ground terminal coupled to ground potential.

Optionally, the first gain amplification circuit further has a power supply terminal configured to receive a second stage power supply voltage and a ground terminal coupled to ground potential.

Optionally, the first bias circuit includes: a current source having a first terminal coupled to a first stage supply voltage; a first resistor having a first terminal coupled to a second terminal of the current source; a third transistor having a first terminal coupled to the second terminal of the first resistor, a control terminal coupled to the first terminal of the first resistor to receive a first bias voltage; a fourth transistor having a control terminal coupled to the control terminal of the third transistor; a first transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal coupled to the second terminal of the first resistor to receive a second bias voltage, and a second terminal coupled to ground potential; a second transistor having a first terminal coupled to the second terminal of the fourth transistor, a control terminal coupled to the control terminal of the first transistor, and a second terminal coupled to a ground potential; and a fifth transistor having a first terminal coupled to the first stage supply voltage, and a control terminal and a second terminal coupled to the first terminal of the fourth transistor.

Optionally, the differential input circuit includes: a sixth transistor having a first terminal coupled to the first stage supply voltage, and a control terminal coupled to the control terminal of the fifth transistor; a seventh transistor having a first terminal coupled to the second terminal of the sixth transistor, and a control terminal coupled to the reference voltage; an eighth transistor having a first terminal coupled to the second terminal of the sixth transistor, and a control terminal coupled to the feedback voltage; a ninth transistor having a first terminal coupled to the second terminal of the seventh transistor and a control terminal, and a second terminal coupled to a ground potential; and a tenth transistor having a first terminal coupled to the second terminal of the eighth transistor, and a center tap node of the two as an output of the differential input circuit, a control terminal coupled to the control terminal of the ninth transistor, and a second terminal coupled to the ground potential.

Optionally, the current regulation loop includes: a current sensing circuit configured to sense the load current to obtain a sensed current; a current comparison circuit configured to compare the sensing current with a preset reference current to generate a current limit control signal; and a second gain amplification circuit having an input configured to receive the current limit control signal and an output configured to generate the control signal for application to the control terminal of the power transistor.

Optionally, the voltage regulation loop and the current regulation loop share a gain amplification circuit.

Optionally, the gain amplifying circuit includes: a thirteenth transistor having a first terminal coupled to the second stage supply voltage, and a control terminal and a second terminal coupled to the control terminal of the power transistor; a third resistor having a first terminal coupled to the thirteenth transistor; a twelfth transistor having a first terminal coupled to the second terminal of the third resistor and a second terminal coupled to ground potential; and a second resistor having a first terminal coupled to an output of the differential input circuit and a second terminal coupled to the twelfth transistor.

Optionally, the current regulation loop further comprises: a feedback control circuit having a first terminal coupled to an output of the differential input circuit, a second terminal coupled to ground potential, and a control terminal configured to receive the current limit control signal, wherein the feedback control circuit is configured to be controlled by the current limit control signal to conduct a current path of the output of the differential input circuit to ground to close the voltage regulation loop.

Optionally, a primary pole of the linear voltage regulator circuit is located at the output node, and a secondary pole is located at an output of the differential input circuit, wherein a frequency at the secondary pole is set by the feedback control circuit.

Optionally, the feedback control circuit includes: an eleventh transistor having a first terminal coupled to the output of the differential input circuit, a second terminal coupled to ground potential, and a control terminal configured to receive the current limit control signal.

Optionally, the current regulation loop further comprises: a second bias circuit coupled between the output node and ground potential, configured to provide a second bias current to the current comparison circuit, the current comparison circuit determining a magnitude of the reference current based on the second bias current.

Optionally, the current sensing circuit includes: a fourteenth transistor having a first terminal coupled to the second stage supply voltage, a control terminal coupled to the control terminal of the power transistor, and a second terminal configured to supply the sense current.

Optionally, the current comparison circuit includes: a nineteenth transistor having a first terminal coupled to the second terminal of the fourteenth transistor and a control terminal coupled to the second bias circuit; a twentieth transistor having a first terminal coupled to the second terminal of the nineteenth transistor and a control terminal, and a second terminal coupled to the ground potential; a twenty-first transistor having a first terminal coupled to a control terminal of the twentieth transistor, and a second terminal coupled to the ground potential; an eighteenth transistor having a first terminal coupled to the output node and a control terminal coupled to the second bias circuit; a twenty-third transistor having a first terminal coupled to the second terminal of the eighteenth transistor and a control terminal, and the control terminal of the twenty-third transistor is also coupled to the control terminal of the twenty-first transistor; and a twentieth transistor having a first terminal coupled to the control terminal of the twenty-third transistor, a control terminal coupled to the control terminal of the twentieth transistor, and a second terminal coupled to the ground potential, wherein the eighteenth transistor is configured to generate the reference current, and wherein the nineteenth transistor and the center tap node of the twentieth transistor are configured to provide the current limit control signal.

Optionally, the second bias circuit includes: a seventeenth transistor having a first terminal coupled to the output node, and control and second terminals coupled to control terminals of the eighteenth and nineteenth transistors; a sixteenth transistor having a first terminal coupled to the second terminal of the seventeenth transistor and a control terminal configured to receive a first bias voltage; and a fifteenth transistor having a first terminal coupled to the second terminal of the sixteenth transistor, a control terminal configured to receive a second bias voltage, and a second terminal coupled to the ground potential.

Optionally, the current comparison circuit further includes: a fourth resistor coupled between the second terminal of the fourteenth transistor and the first terminal of the nineteenth transistor; and a diode coupled between the first terminal of the nineteenth transistor and the ground potential.

In summary, the embodiment of the application provides a linear voltage regulator circuit with current foldback current limiting and main pole self-adaptive switching, which does not need to internally set a compensation capacitor, and is different from the main pole position set by the existing off-chip capacitor structure, the main pole is set at an output node of an LDO, and when an output load is a middle-low load, the output node can be used as the main pole to ensure the stability of a system loop and output stable signals. Along with the increase of output load to heavy load and even overload, the linear voltage regulator circuit switches loop control to a current regulation loop and pulls out the voltage regulation loop, the secondary pole point inside the LDO is changed into the main pole point through loop switching, the stability problem of the LDO loop is effectively improved, meanwhile, load current can be limited to a certain current range, the damage of large current to the circuit under the overload condition is effectively reduced, and the circuit stability is higher.

Drawings

The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic circuit diagram of a conventional linear regulator circuit;

FIG. 2 shows a schematic block diagram of a linear voltage regulator circuit in accordance with an embodiment of the application;

fig. 3 shows a schematic circuit diagram of a linear voltage regulator circuit according to an embodiment of the application.

Detailed Description

Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.

It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

In the present application, the power transistor is a transistor that operates in a linear mode to provide a current path, including one selected from a bipolar transistor or a field effect transistor. The input terminal and the output terminal of the power transistor are a high potential end and a low potential end on a current path respectively, and the control terminal is used for receiving a driving signal to control the voltage drop of the power transistor. The power transistor may be a PMOS (N-Metal-Oxide-Semiconductor) transistor or an NMOS (N-Metal-Oxide-Semiconductor) transistor. The first terminal, the second terminal and the control terminal of the PMOS transistor are a source, a drain and a gate, respectively, and the first terminal, the second terminal and the control terminal of the NMOS transistor are a drain, a source and a gate, respectively.

The application will be described in detail below with reference to the drawings and the specific embodiments.

Referring to fig. 2, fig. 2 shows a schematic block diagram of a linear regulator circuit 200 configured to support operation in one instance (e.g., in light load instance) to enable voltage regulation loop 210 to regulate delivery of voltage at a load, and operation in another instance (e.g., in output overload instance) to enable current regulation loop to regulate delivery of current to the load, in accordance with an embodiment of the present application. The power transistor MP has a source-drain current path coupled between the second stage supply voltage AVCC and the output voltage Vout node and configured to provide current to the output node. Specifically, the power transistor MP is implemented by a PMOS transistor, the drain of which is coupled to the second stage supply voltage AVCC, and the source of which is coupled to the output voltage Vout node. The gate terminal of the power transistor MP is configured to receive a control signal PG, which is used as a gate voltage of the power transistor MP to control a current flowing through the power transistor MP.

The voltage regulation loop 210 is configured to sense the voltage at the output voltage Vout node and to modulate the control signal PG such that the power transistor MP delivers current to the output voltage Vout node in order to regulate the output voltage Vout to a level such that the feedback voltage Vfb is substantially equal to the reference voltage Vref. Specifically, the voltage regulation loop 210 senses the output voltage Vout at the load using a feedback resistor network 214 coupled to the output voltage Vout node, the feedback resistor network 214 being formed, for example, by a series connection of a plurality of resistors, and generates a feedback voltage Vfb at a tap node of the resistors.

Specifically, the voltage regulation loop 210 further includes a first bias circuit 211, a differential input circuit 212, and a gain amplification circuit 213. Wherein the first bias circuit 211 is coupled between the first stage supply voltage VINT and the ground potential VSS and configured to provide a first bias current to the differential input circuit 212. Differential input circuit 212 has a first input configured to receive feedback voltage Vfb at an output node and a second input configured to receive reference voltage Vref. The reference voltage Vref is a bandgap reference from the inside of the chip, and does not vary with the temperature and the power supply voltage. The gain amplification circuit 213 has an input coupled to the output of the differential input circuit 212 and an output configured to generate a control signal PG for application to the gate of the power transistor MP. The differential input circuit 212 forms a first stage of a conventional error amplifier, and is formed by a differential input pair transistor and a current mirror load, so that conversion from double-ended input to single-ended output is completed; the gain amplifying circuit 213 forms a second stage of a conventional error amplifier, which can provide high gain for the output, and the poles included in the second stage circuit are all high-frequency poles, which is beneficial to the stable output of the LDO circuit.

In an embodiment of the present application, the error amplifier provided in the embodiment of the present application may be an OTA (operational transconductance amplifier, transconductance amplifier), which is not particularly limited.

Further, the linear voltage regulator circuit 200 of the present embodiment has a dual power rail structure, the differential input circuit 212 further has a power terminal configured to receive the first stage power voltage VINT and a ground terminal coupled to the ground potential VSS, and the gain amplifying circuit 213 further has a power terminal configured to receive the second stage power voltage AVCC and a ground terminal coupled to the ground potential VSS. The second stage power supply voltage AVCC is higher than the first stage power supply voltage VINT, and by adopting the structure of the dual power supply rails, the linear voltage regulator circuit 200 of the present embodiment can improve the PSR (Power Supply Rejection ) of the circuit while improving the efficiency.

The current regulation loop 220 is configured to sense a load current flowing through the power transistor MP and to modulate the control signal PG so that the power transistor MP can output a constant current to a load. The current regulation loop 220 includes a current sensing circuit 221, a current comparison circuit 222, a gain amplification circuit 213, a feedback control circuit 223, and a second bias circuit 224. Wherein the current sensing circuit 221 Is configured to sense a load current flowing through the power transistor MP to obtain a sensing current Is. The current comparison circuit 222 Is configured to compare the sensing current Is with a preset reference current, determine whether the load current reaches an overcurrent threshold according to the comparison result, and generate a current limiting control signal SG. The magnitude of the reference current is determined based on the second bias current provided by the second bias circuit 224. The feedback control circuit 223 is coupled between the output of the differential input circuit 212 and the ground potential VSS and is configured to switch on a current path of the output of the differential input circuit to ground, thereby closing the voltage regulation loop 210, controlled by the current limiting control signal SG. At the same time, the feedback control circuit 223 pulls the potential of the input terminal of the gain amplification circuit 213 low, and then pulls the gate voltage of the power transistor MP high through the gain amplification circuit 213, and the current regulation loop 220 modulates the gate voltage of the gate terminal of the power transistor MP accordingly, so that the power transistor MP outputs a defined constant current to the output node.

The working process of the linear voltage regulator circuit 200 of the present application is: assuming that the output voltage Vout is at a level such that the feedback voltage Vfb is much smaller than the reference voltage Vref, the load current is much less than the overcurrent threshold. The current is sensed by the current sensing circuit 221. At this point, the current regulation loop 220 is closed, the voltage regulation loop 210 is open, and the output of the LDO is dominated by the voltage regulation loop 210. The voltage regulation loop 210 will control the power transistor MP by modulating the control signal PG to increase the amplitude of the current delivered to the load. When the load current increases such that the sense current exceeds the reference current, the current comparison circuit 222 in the current regulation loop 220 triggers the feedback control circuit 223 to turn on, the feedback control circuit 223 pulls down the output of the differential input circuit 212 in the voltage regulation loop 210 such that the differential input circuit 212 in the voltage regulation loop 210 is no longer operational, the voltage regulation loop 210 is turned off, and the output of the LDO is dominated by the current regulation loop 220.

In some embodiments, the current regulation loop 220 is a current limiting circuit with a current foldback function, i.e., allowing the output of the LDO to be briefly overloaded without immediately switching to a current limiting modulation mode, can ensure that the system responds to load jumps quickly. In addition, when the system is over-current, the current regulation loop 220 does not exit modulation until the load current decreases to a lower value, and the output voltage is modulated by the voltage regulation loop 210.

In this embodiment, the primary pole of the linear regulator circuit 200 is located at the output node (i.e., point C in fig. 1), while the secondary pole is located at the output of the differential input circuit 212 of the voltage regulation loop 210 (i.e., point a in fig. 1). When the output load of the circuit is a medium-low load, the frequency of the main pole C is in a low frequency, and the secondary pole A is outside GBW (gain-bandwidth product ), so the voltage regulation loop 210 of the LDO can be used as a single-pole system to ensure the stability of the loop. As the output load increases gradually, the frequency of the primary pole C is pushed to a high frequency along with the decrease of the load resistance, and at this time, the frequency of the secondary pole a is smaller than the loop bandwidth of the whole linear voltage regulator circuit, so that the signal output by the output node is unstable. When the load current triggers the overcurrent, the linear voltage stabilizer circuit 200 provided by the embodiment of the application is controlled by the current regulating loop 220 to cut into the loop, and the current output by the differential input circuit 212 is pumped by the feedback control circuit 223, so that the current mirror load in the differential input circuit 212 enters a cut-off region, the secondary pole A is changed into a low-impedance node, the frequency of the secondary pole A is improved, the primary pole C is separated from the loop, the primary pole A is changed into the primary pole of the current loop, and good phase margin is ensured, thereby ensuring that the system still has good transient characteristics in heavy load and even overload, and outputting stable signals.

Fig. 3 shows a schematic circuit diagram of a linear voltage regulator circuit according to an embodiment of the application. As shown in fig. 3, the first bias circuit 211 includes a current source Ib, a resistor R1, NMOS transistors M1 to M4, and a PMOS transistor M5. The first end of the current source Ib is coupled to the first stage power supply voltage VINT, the second end of the current source Ib is coupled to the first end of the resistor R1, and the second end of the resistor R1 is coupled to the drain of the NMOS transistor M3. The first terminal of the resistor R1 is configured to provide the first bias voltage Vcn, the second terminal is configured to provide the second bias voltage Vbn, the gates of the NMOS transistors M3 and M4 are each coupled to the first terminal of the resistor R1 to receive the first bias voltage Vcn, and the gates of the NMOS transistors M1 and M2 are each coupled to the second terminal of the resistor R1 to receive the second bias voltage Vbn. The drain of NMOS transistor M1 is coupled to the source of NMOS transistor M3, which is coupled to ground potential VSS. The drain of NMOS transistor M2 is coupled to the source of NMOS transistor M4, which is coupled to ground potential VSS. The PMOS transistor M5 is diode-connected, its drain is coupled to the first stage supply voltage VINT, its gate and drain are coupled to the drain of the NMOS transistor M4, and the PMOS transistor M5 provides the bias current to the differential input circuit 212 in a mirror image manner.

The differential input circuit 212 is a common five-tube operational amplifier, and includes PMOS tubes M6 to M8 and NMOS tubes M9 and M10. The PMOS tube M6 is used as a tail current source, the PMOS tubes M7 and M8 are used as differential input pair tubes, and the NMOS tubes M9 and M10 are connected into a current mirror structure to be used as a current mirror active load. Specifically, the source of the PMOS transistor M6 is coupled to the first stage power supply voltage VINT, the gate is coupled to the gate of the PMOS transistor M5 to connect with the PMOS transistor M5 into a current mirror structure, and the drain is coupled to the sources of the PMOS transistors M7 and M8. The gate of the PMOS transistor M7 is configured to receive the reference voltage Vref as a first input of the differential input circuit 212, and the gate of the PMOS transistor M8 is configured to receive the feedback voltage Vfb as a second input of the differential input circuit 212. The sources of the NMOS transistors M9 and M10 are both coupled to the ground potential VSS, the grid electrode is coupled to the drain electrode of the NMOS transistor M9, the drain electrode of the NMOS transistor M9 is also coupled to the drain electrode of the PMOS transistor M7, the drain electrode of the NMOS transistor M10 is coupled to the drain electrode of the PMOS transistor M8, and the common node of the two is used as the output of the differential input circuit 212.

The gain amplifying circuit 213 includes a resistor R2, a resistor R3, an NMOS transistor M12, and a PMOS transistor M13. The PMOS transistor M13 is diode-connected, and has a source coupled to the second stage supply voltage AVCC, a gate and a drain coupled to the gate of the power transistor MP, a first end of the resistor R3 coupled to the drain of the PMOS transistor M13, a second end coupled to the drain of the NMOS transistor M12, a source of the NMOS transistor M12 coupled to the ground potential VSS, a first end coupled to the output of the differential input circuit 212, and a second end coupled to the gate of the NMOS transistor M12. The NMOS tube M12 forms a source follower structure, the PMOS tube M13 forms a PMOS active load, and the resistors R2 and R3 are used for protecting the NMOS tube M12 from being damaged by high voltage. The gain amplifying circuit 213 of this embodiment can convert the output of the differential input circuit 212 from low voltage to high voltage, and push up the parasitic pole of the power tube gate, so as to reduce the influence of the power tube gate pole on the loop stability, and facilitate the stable output of the LDO circuit.

The feedback resistor network 214 includes resistors R5-R7, the resistors R7, R6, and R5 being coupled in sequence between the output pole of the LDO and the ground potential VSS, the center tap node of the resistors R5 and R6 being configured to provide the feedback voltage Vfb.

The current sensing circuit 221 includes a PMOS transistor M14, a source of the PMOS transistor M14 and a source of the power transistor MP are both coupled to the second stage power supply voltage AVCC, a gate Is coupled to a gate of the power transistor MP, and a drain Is configured to provide the sensing current Is. The load current is equal to the sum of the current flowing through the sampling transistor M14 and the current flowing through the power transistor MP, and is approximately equal to the current flowing through the power transistor MP because the current of the sampling transistor M14 is negligible because it is small. The sampling transistor M14 is used for sampling the current flowing through the power transistor MP, i.e. the load current. The sampling transistor M14 has a fixed ratio relationship between the width-to-length ratio and the power transistor MP, for example, when the load current Is 1A, the sense current Is 1 μa.

The second bias circuit 224 includes a PMOS transistor M17 and NMOS transistors M15 and M16, where the PMOS transistor M17 is a diode structure, a source thereof is coupled to an output node of the circuit, a gate and a drain thereof are coupled to a drain of the NMOS transistor M16, a gate of the NMOS transistor M16 is configured to receive the first bias voltage Vcn, a source of the NMOS transistor M16 is coupled to a drain of the NMOS transistor M15, a gate of the NMOS transistor M15 is configured to receive the second bias voltage Vbn, and a source of the NMOS transistor M15 is coupled to the ground potential VSS. The PMOS transistor M17 supplies a second bias current having a certain value to the current comparing circuit 222 in a mirror image manner, and the current comparing circuit 222 determines the magnitude of the reference current based on the second bias current.

The current comparison circuit 222 includes PMOS transistors M18 and M19 and NMOS transistors M20 to M23. The source of the PMOS transistor M19 Is configured to receive the sensing current Is, and the gate Is coupled to the gate of the PMOS transistor M17. The source electrode of the PMOS tube M18 is coupled with the source electrode of the PMOS tube M17, the grid electrode is coupled with the grid electrode and the drain electrode of the PMOS tube M17, the structure of a current mirror is formed by the grid electrode and the PMOS tube M17, and the second bias current is obtained through the mirror current. The NMOS transistors M20 and M23 are diode-connected, wherein the gate and the drain of the NMOS transistor M20 are coupled to the drain of the PMOS transistor M19, and a common node between the PMOS transistor M19 and the NMOS transistor M20 is used to provide the current limiting control signal SG, the source is coupled to the ground potential VSS, the gate and the drain of the NMOS transistor M23 are coupled to the drain of the PMOS transistor M18, the source is coupled to the ground potential VSS, the drain of the NMOS transistor M21 is coupled to the gate and the drain of the NMOS transistor M20, the gate is coupled to the gate and the drain of the NMOS transistor M23, the source is coupled to the ground potential VSS, the drain of the NMOS transistor M22 is coupled to the gate and the drain of the NMOS transistor M23, and the source is coupled to the ground potential VSS.

Further, the linear voltage regulator circuit 200 of the present embodiment further includes a resistor R4 and a diode D1, wherein the resistor R4 is coupled between the drain of the PMOS transistor M14 and the source of the PMOS transistor M19. The diode D1 is a clamping diode, and has an anode coupled to the ground potential VSS, and a cathode coupled to the source of the PMOS transistor M19, for protecting the PMOS transistor M19 from high voltage.

In the above embodiment, diode connection refers to the case where the gate and the drain of the MOS transistor are directly coupled together.

In some embodiments, the threshold of the linear regulator circuit 200 that triggers the over-current and over-current recovery is adjusted by the size ratio of the NMOS transistors M20-M23 in the current comparison circuit 222. For example, assume that the size ratio of the NMOS transistors M20 to M23 is: m20:m21:m22:m23=20:10:1:2, when the output load Is a medium-low load, the sense current Is small, at this time, almost no current flows in the NMOS transistors M20 and M22, and all the current flows through the NMOS transistors M21 and M23, so the current limiting control signal SG Is pulled low to a low level, and then the gate of the NMOS transistor M11 Is pulled low to be turned off, and the output of the LDO Is dominated by the voltage regulation loop 210 through the whole circuit. When the output load Is heavy load or even overload, the sense current Is greatly rises by more than 5 times of the mirror current of the PMOS transistor M18, because the NMOS transistor M21 cannot fully absorb the sense current Is, the NMOS transistor M20 Is turned on and the NMOS transistor M22 splits the current originally flowing through the NMOS transistor M23 through the mirror current, and the current flowing through the NMOS transistor M21 Is continuously reduced due to the current mirror structure formed by the NMOS transistor M23, so that the current limiting control signal SG Is pulled high to high level through the positive feedback loop, and then the gate of the NMOS transistor M11 Is pulled high to be turned on, at this time, the voltage regulating loop 210 Is turned off, and the output of the LDO Is dominated by the current regulating loop 220. Similarly, when the sense current Is less than 1/20 of the current mirrored by the PMOS transistor M18, the circuit exits the current limiting modulation mode and the output of the LDO Is again dominated by the voltage regulation loop 210.

Correspondingly, the embodiment of the application also provides an electronic device, which comprises the linear voltage regulator circuit 200 provided by any one of the embodiments.

In an embodiment of the present application, the electronic device provided by the present application may be a portable electronic device such as a cellular phone.

It should be noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The scope of the application should be determined by the following claims.

Claims

1. A linear voltage regulator circuit, comprising:

a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to the output node;

a voltage regulation loop configured to sense a voltage at the output node and to modulate the control signal to cause the power transistor to deliver current to the output node such that an output voltage at the output node is regulated; and

a current regulation loop configured to sense a load current flowing through the power transistor and to modulate the control signal so that the power transistor outputs a constant current to the output node;

wherein the linear regulator circuit is configured to turn on one of the voltage regulation loop or the current regulation loop based on a comparison of the load current to a target value.

2. The linear regulator circuit of claim 1, wherein the linear regulator circuit is configured to: opening the voltage regulation loop and closing the current regulation loop if the load current does not reach the target value; and opening the current regulation loop and closing the voltage regulation loop if the load current reaches the target value.

3. The linear regulator circuit of claim 1, wherein the current regulation loop is a current limiting circuit with a current foldback function.

4. The linear regulator circuit of claim 1, wherein the voltage regulation loop comprises:

a differential input circuit having a first input configured to receive a feedback voltage at the output node and a second input configured to receive a reference voltage; and

a first gain amplification circuit has an input coupled to an output of the differential input circuit and an output configured to generate the control signal for application to the control terminal of the power transistor.

5. The linear regulator circuit of claim 4, wherein the voltage regulation loop further comprises:

a first bias circuit coupled between a first stage supply voltage and ground potential, configured to provide a first bias current to the differential input circuit; and

a feedback resistor network, coupled between the output node and ground potential, is configured to provide the feedback voltage to the differential input circuit.

6. The linear regulator circuit of claim 4, wherein the differential input circuit further has a power supply terminal configured to receive a first stage power supply voltage and a ground terminal coupled to ground potential.

7. The linear regulator circuit of claim 4, wherein the first gain amplification circuit further has a power supply terminal configured to receive a second stage supply voltage and a ground terminal coupled to ground potential.

8. The linear regulator circuit of claim 5, wherein the first bias circuit comprises:

a current source having a first terminal coupled to a first stage supply voltage;

a first resistor having a first terminal coupled to a second terminal of the current source;

a third transistor having a first terminal coupled to the second terminal of the first resistor, a control terminal coupled to the first terminal of the first resistor to receive a first bias voltage;

a fourth transistor having a control terminal coupled to the control terminal of the third transistor;

a first transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal coupled to the second terminal of the first resistor to receive a second bias voltage, and a second terminal coupled to ground potential;

a second transistor having a first terminal coupled to the second terminal of the fourth transistor, a control terminal coupled to the control terminal of the first transistor, and a second terminal coupled to a ground potential; and

a fifth transistor having a first terminal coupled to the first stage supply voltage, and a control terminal and a second terminal coupled to the first terminal of the fourth transistor.

9. The linear regulator circuit of claim 8, wherein the differential input circuit comprises:

a sixth transistor having a first terminal coupled to the first stage supply voltage, and a control terminal coupled to the control terminal of the fifth transistor;

a seventh transistor having a first terminal coupled to the second terminal of the sixth transistor, and a control terminal coupled to the reference voltage;

an eighth transistor having a first terminal coupled to the second terminal of the sixth transistor, and a control terminal coupled to the feedback voltage;

a ninth transistor having a first terminal coupled to the second terminal of the seventh transistor and a control terminal, and a second terminal coupled to a ground potential; and

a tenth transistor having a first terminal coupled to the second terminal of the eighth transistor and a center tap node thereof as an output of the differential input circuit, a control terminal coupled to the control terminal of the ninth transistor, and a second terminal coupled to the ground potential.

10. The linear regulator circuit of claim 4, wherein the current regulation loop comprises:

a current sensing circuit configured to sense the load current to obtain a sensed current;

a current comparison circuit configured to compare the sensing current with a preset reference current to generate a current limit control signal; and

a second gain amplification circuit has an input configured to receive the current limit control signal and an output configured to generate the control signal for application to the control terminal of the power transistor.

11. The linear regulator circuit of claim 10, wherein the voltage regulation loop and the current regulation loop share a gain amplification circuit.

12. The linear regulator circuit of claim 11, wherein the gain amplification circuit comprises:

a thirteenth transistor having a first terminal coupled to the second stage supply voltage, and a control terminal and a second terminal coupled to the control terminal of the power transistor;

a third resistor having a first terminal coupled to the thirteenth transistor;

a twelfth transistor having a first terminal coupled to the second terminal of the third resistor and a second terminal coupled to ground potential; and

a second resistor having a first terminal coupled to the output of the differential input circuit and a second terminal coupled to the twelfth transistor.

13. The linear regulator circuit of claim 10, wherein the current regulation loop further comprises:

a feedback control circuit having a first terminal coupled to an output of the differential input circuit, a second terminal coupled to ground potential, and a control terminal configured to receive the current limit control signal,

wherein the feedback control circuit is configured to be controlled by the current limit control signal to conduct a current path of an output of the differential input circuit to ground to close the voltage regulation loop.

14. The linear regulator circuit of claim 13, wherein a primary pole of the linear regulator circuit is located at the output node and a secondary pole is located at the output of the differential input circuit, wherein a frequency at the secondary pole is set by the feedback control circuit.

15. The linear regulator circuit of claim 13, wherein the feedback control circuit comprises:

an eleventh transistor having a first terminal coupled to the output of the differential input circuit, a second terminal coupled to ground potential, and a control terminal configured to receive the current limit control signal.

16. The linear regulator circuit of claim 10, wherein the current regulation loop further comprises:

a second bias circuit coupled between the output node and ground potential, configured to provide a second bias current to the current comparison circuit, the current comparison circuit determining a magnitude of the reference current based on the second bias current.

17. The linear regulator circuit of claim 16, wherein the current sensing circuit comprises:

a fourteenth transistor having a first terminal coupled to the second stage supply voltage, a control terminal coupled to the control terminal of the power transistor, and a second terminal configured to supply the sense current.

18. The linear regulator circuit of claim 17, wherein the current comparison circuit comprises:

a nineteenth transistor having a first terminal coupled to the second terminal of the fourteenth transistor and a control terminal coupled to the second bias circuit;

a twentieth transistor having a first terminal coupled to the second terminal of the nineteenth transistor and a control terminal, and a second terminal coupled to the ground potential;

a twenty-first transistor having a first terminal coupled to a control terminal of the twentieth transistor, and a second terminal coupled to the ground potential;

an eighteenth transistor having a first terminal coupled to the output node and a control terminal coupled to the second bias circuit;

a twenty-third transistor having a first terminal coupled to the second terminal of the eighteenth transistor and a control terminal, and the control terminal of the twenty-third transistor is also coupled to the control terminal of the twenty-first transistor; and

a twenty-third transistor having a first terminal coupled to the control terminal of the twenty-third transistor, a control terminal coupled to the control terminal of the twenty-third transistor, and a second terminal coupled to the ground potential,

wherein the eighteenth transistor is configured to generate the reference current, and wherein intermediate tap nodes of the nineteenth and twentieth transistors are configured to provide the current limit control signal.

19. The linear regulator circuit of claim 18, wherein the second bias circuit comprises:

a seventeenth transistor having a first terminal coupled to the output node, and control and second terminals coupled to control terminals of the eighteenth and nineteenth transistors;

a sixteenth transistor having a first terminal coupled to the second terminal of the seventeenth transistor and a control terminal configured to receive a first bias voltage; and

a fifteenth transistor having a first terminal coupled to the second terminal of the sixteenth transistor, a control terminal configured to receive a second bias voltage, and a second terminal coupled to the ground potential.

20. The linear regulator circuit of claim 18, wherein the current comparison circuit further comprises:

a fourth resistor coupled between the second terminal of the fourteenth transistor and the first terminal of the nineteenth transistor; and

a diode is coupled between the first terminal of the nineteenth transistor and the ground potential.