CN219143338U - Linear voltage stabilizer and system on chip - Google Patents
Linear voltage stabilizer and system on chip Download PDFInfo
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- CN219143338U CN219143338U CN202320181385.0U CN202320181385U CN219143338U CN 219143338 U CN219143338 U CN 219143338U CN 202320181385 U CN202320181385 U CN 202320181385U CN 219143338 U CN219143338 U CN 219143338U
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Abstract
The utility model discloses a linear voltage stabilizer and a system on a chip, wherein the linear voltage stabilizer comprises: the device comprises an error amplifying module, a buffer module, a transient enhancing module and an adjusting tube; the first input end of the error amplification module is connected with the output end of the linear voltage stabilizer, the second input end of the error amplification module is connected with the reference voltage, and the output end of the error amplification module is connected with the third input end of the buffer module; the fourth input end of the buffer module is connected with the bias voltage, the output end of the buffer module is connected with the grid electrode of the adjusting tube, and the buffer module is used for outputting control voltage to the grid electrode of the adjusting tube according to the voltages of the third input end and the fourth input end; the transient enhancement module comprises a current mirror, and the current mirror is used for mirroring the current output of the reduced adjusting tube to the grid electrode of the adjusting tube according to a set proportion. The embodiment of the utility model can improve the transient response capability of the linear voltage stabilizer and the stability of the circuit through the buffer module and the transient enhancement module.
Description
Technical Field
The embodiment of the utility model relates to the technical field of integrated circuits, in particular to a linear voltage stabilizer and a system on a chip.
Background
Linear regulators (Low Dropout Regulator, LDOs) are integrated in large numbers into System On Chip (SOC), digital chips, high performance analog to digital/digital to analog chips as an important circuit block in power management units (Power Management Unit, PMU). In a high-speed digital circuit using an LDO as voltage regulator, the main frequency is higher and higher, and can reach several GHz at present, and the instantaneous jump of the level in the digital circuit can cause the instantaneous jump of the current. If the load of the LDO is a digital circuit, the instantaneous jump in load current will affect the output voltage of the LDO.
The existing LDO mainly comprises a voltage reference source, an error amplifying module, an adjusting tube and a voltage division output module.
The existing LDO cannot meet the index requirement of rapidly responding to load current change.
Disclosure of Invention
The utility model provides a linear voltage stabilizer and a system on a chip, which can improve transient response capability of the linear voltage stabilizer and stability of a circuit.
In a first aspect, an embodiment of the present utility model provides a linear voltage regulator, including: the device comprises an error amplifying module, a buffer module, a transient enhancing module and an adjusting tube; the first input end of the error amplification module is connected with the output end of the linear voltage stabilizer, the second input end of the error amplification module is connected with the reference voltage, and the output end of the error amplification module is connected with the third input end of the buffer module; the fourth input end of the buffer module is connected with the bias voltage, the output end of the buffer module is connected with the grid electrode of the adjusting tube, and the buffer module is used for outputting control voltage to the grid electrode of the adjusting tube according to the voltages of the third input end and the fourth input end; the transient enhancement module comprises a current mirror, and the current mirror is used for mirroring the current output of the reduced adjusting tube to the grid electrode of the adjusting tube according to a set proportion.
Optionally, the buffer module includes a first transistor and a second transistor, a gate of the first transistor is connected to the third input end, a first pole of the first transistor is connected to an output end of the buffer module, and a second pole of the first transistor is grounded; the grid electrode of the second transistor is connected with the fourth input end, the first electrode of the second transistor is connected with a power supply, and the second electrode of the second transistor is connected with the output end of the buffer module.
Optionally, the transient enhancement module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a current source; the grid electrode of the third transistor is connected with the grid electrode of the adjusting transistor, the first electrode of the third transistor and the first electrode of the adjusting transistor are both connected with a power supply and the first end of a current source, and the second electrode of the third transistor is connected with the second end of the current source; the grid electrode of the fourth transistor is connected with the grid electrode of the fifth transistor, and the first electrode of the fourth transistor and the first electrode of the fifth transistor are both connected with a power supply; the second pole of the fourth transistor is connected with the grid electrode of the adjusting transistor, and the second pole of the fifth transistor is connected with the first pole of the sixth transistor; the grid electrode of the fifth transistor is connected with the second pole of the fifth transistor; the gate of the sixth transistor is connected to the gate of the seventh transistor, the second electrode of the sixth transistor is grounded, the first electrode of the seventh transistor is connected to the second electrode of the third transistor, and the second electrode of the seventh transistor is grounded.
Optionally, the first transistor and the second transistor of the buffer module, the third transistor, the fourth transistor and the fifth transistor of the transient enhancement module each comprise PMOS, and the sixth transistor and the seventh transistor each comprise NMOS.
Optionally, the error amplifying module includes an operational amplifier, a non-inverting input end of the operational amplifier is connected to a first input end of the error amplifying module, an inverting input end of the operational amplifier is connected to a second input end of the error amplifying module, and an output end of the operational amplifier is connected to an output end of the error amplifying module.
Optionally, the linear voltage stabilizer further comprises a voltage division output module, wherein the voltage division output module is connected between the second pole of the adjusting tube and the ground, and is used for outputting voltage to the output end of the linear voltage stabilizer according to the current of the adjusting tube.
Optionally, the voltage division output module includes a first resistor and a second resistor, the first resistor and the second resistor are connected in series between the second pole of the adjusting tube and the ground, and a common end of the first resistor and the second resistor is connected with an output end of the linear voltage stabilizer.
Optionally, the linear voltage stabilizer further comprises a capacitor, a first end of the capacitor is connected with the output end of the linear voltage stabilizer, and a second end of the capacitor is grounded.
Optionally, the linear voltage regulator further includes a bias voltage supply circuit electrically connected to the fourth input terminal for providing a bias voltage to the buffer module.
In a second aspect, an embodiment of the present utility model further provides a system on a chip, including the linear voltage regulator provided in the first aspect.
The linear voltage stabilizer provided by the embodiment of the utility model comprises an error amplifying module, a buffer module, a transient enhancement module and an adjusting tube, wherein the buffer module is used for outputting control voltage to the grid electrode of the adjusting tube according to the voltages of a third input end and a fourth input end; the transient enhancement module comprises a current mirror, and the current mirror is used for mirroring the current output of the reduced adjusting tube to the grid electrode of the adjusting tube according to a set proportion. Comparing the acquired output voltage with the input reference voltage through an error amplification module, and driving an adjusting tube by using the generated error calibration signal to enable the adjusting tube to provide current required by a load; the buffer module isolates the output impedance of the error amplification module and the parasitic capacitance of the grid electrode of the adjusting tube, which is beneficial to frequency compensation, and the buffer module can also increase the slew rate of the grid end of the adjusting tube, thereby improving the transient response capability of the LDO; the current of the current mirror image adjusting tube in the transient enhancement module does not increase extra power consumption under the condition of low load current, and the mirrored current increases the current of the buffer module under the condition of high load current, so that the output impedance of the buffer module is reduced, the parasitic pole of the output end is pushed to a higher frequency, the grid end of the adjusting tube is charged, the available current under the same slew rate is improved, and the transient response performance of the LDO is further improved.
Drawings
Fig. 1 is a schematic structural diagram of a linear voltage regulator according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a linear voltage regulator according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of a linear voltage regulator according to an embodiment of the present utility model;
fig. 4 is a schematic structural diagram of another linear voltage regulator according to an embodiment of the present utility model.
Detailed Description
The utility model is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present utility model are shown in the drawings.
Fig. 1 is a schematic structural diagram of a linear voltage regulator according to an embodiment of the present utility model, where the embodiment is applicable to a power supply voltage stabilizing situation.
As shown in fig. 1, the linear voltage regulator includes: error amplification module 10, buffer module 20, transient enhancement module 30, and tuning tube MP.
The first input terminal IN1 of the error amplifying module 10 is connected to the output terminal of the linear voltage stabilizer, the second input terminal IN2 of the error amplifying module 10 is connected to the reference voltage VREF, and the output terminal of the error amplifying module 10 is connected to the third input terminal IN3 of the buffer module 20.
The fourth input terminal IN4 of the buffer module 20 is connected to the bias voltage VB, the output terminal of the buffer module 20 is connected to the gate of the regulator MP, and the buffer module 20 is configured to output a control voltage to the gate of the regulator MP according to the voltages of the third input terminal IN3 and the fourth input terminal IN 4.
The transient enhancement module 30 includes a current mirror for mirroring the current output of the scaling tube MP to the gate of the scaling tube MP according to a set ratio.
The error amplification module 10 may be a single channel class AB gain with PMOS differential input pairs. The error amplifying module 10 compares the feedback voltage with the reference voltage VREF to generate an error voltage for controlling the gate of the regulator MP, and adjusts the on-current flowing through the regulator MP to stabilize the output voltage Vout. Wherein the error amplification module 10 may be provided with a high precision reference voltage VREF by a reference voltage source. The first input terminal IN1 of the error amplifying module 10 may be a non-inverting input terminal or an inverting input terminal; the second input terminal IN2 of the error amplification module 10 may be a non-inverting input terminal or an inverting input terminal.
The buffer module 20 may be a unipolar source follower. The buffer module 20 is adopted to isolate the output of the error amplifying module 10 from the grid electrode of the adjusting tube MP, so that the large capacitance of the grid electrode of the adjusting tube MP can be prevented from pulling down the output pole of the error amplifying module 10. Preferably, the buffer module 20 has a smaller input capacitance and a lower output impedance. Illustratively, the input capacitance of the buffer module 20 may be between 100fF and 1pF, and the output impedance of the buffer module 20 may be between 10Ω and 200Ω. After the buffer module 20 is added, the output pole of the error amplifying module 10 becomes high, and the pole formed by the output of the buffer module 20 and the input capacitance of the adjusting tube MP is far greater than the unity gain bandwidth. The buffer module 20 can convert a low-frequency secondary point formed by a large resistor and a large capacitor into two high-frequency secondary points formed by a large resistor and a small capacitor and a small resistor and a large capacitor, which is beneficial to frequency compensation, and the error amplification module 10 can also increase the slew rate of the gate end of the regulator tube MP, thereby improving the transient response capability of the LDO.
The transient enhancement module 30 adjusts the current of the pipe MP through the current mirror image without adding additional power consumption under low load current conditions. Under the condition of high load current, the mirrored current increases the current of the buffer module 20, reduces the output impedance of the buffer module 20, pushes the parasitic pole of the output end to a higher frequency, charges the gate end of the regulator tube MP, improves the available current under the same slew rate, and further improves the transient response performance of the LDO.
The regulator tube MP, also called a power tube, has the main function of inputting a channel for supplying a large current to a load. The first pole of the adjusting tube MP is connected with the power supply VDD, and the second pole of the adjusting tube MP is grounded GND. The regulator MP includes, but is not limited to, NPN, PNP, PMOS, or NMPS. Fig. 1 schematically shows a case where the adjustment tube MP is a PMOS tube. The drain electrode of the regulator tube MP serves as the output terminal of the linear voltage regulator circuit, and the output voltage Vout of the output terminal of the linear voltage regulator circuit drives a load connected thereto. The load can be a CMOS driver of the laser radar, and the load can also be an audio/video encoding/decoding chip. The CMOS driver and audio/video encoding/decoding chip of the laser radar belong to loads with rapid change of load current, and have severe ripple requirements, so that LDO with ultra-fast response speed is required. In addition, the regulator MP is used for ensuring that the LDO has smaller leakage voltage. In other words, the channel length of the regulator MP is generally smaller and the width of the regulator MP is larger, i.e. the width-to-length ratio of the regulator MP is generally larger, ranging from 1000 to 100000, so that the gate of the regulator MP has larger parasitic capacitance.
The working principle of the linear voltage stabilizer is that the output current flowing through the adjusting tube is adjusted through the negative feedback function, so that the output voltage Vout is kept stable. With continued reference to fig. 2, the reference voltage VREF is coupled to the second input IN2 of the error amplification module 10, and the output voltage Vout couples the generated feedback voltage to the first input IN1 of the error amplification module 10 via a feedback network. When the output voltage Vout decreases, the output voltage Vout is transmitted to the first input terminal IN1 of the error amplifying module 10 through the feedback network, the voltage at the first input terminal IN1 of the error amplifying module 10 decreases, the difference between the reference voltage VREF and the feedback voltage decreases, the gate voltage of the regulator MP decreases, the difference between the gate and source voltages increases, the drain current of the regulator MP increases, i.e., the output current increases, the output voltage Vout increases, and further decrease of the output voltage Vout is suppressed, thereby maintaining the output voltage Vout stable. Conversely, when the output voltage Vout increases, the voltage at the first input terminal IN1 of the error amplifying module 10 increases, the difference between the reference voltage VREF and the feedback voltage increases, the gate voltage of the regulator MP increases, the drain current of the regulator MP decreases, i.e. the output current of the LDO decreases, and the output voltage Vout decreases. Thus, the linear voltage stabilizer is always in a deep negative feedback state to continuously correct the output voltage Vout, so that the output voltage Vout is always stable.
The linear voltage stabilizer provided by the embodiment of the utility model comprises an error amplifying module, a buffer module, a transient enhancement module and an adjusting tube, wherein the buffer module is used for outputting control voltage to the grid electrode of the adjusting tube according to the voltages of a third input end and a fourth input end; the transient enhancement module comprises a current mirror, and the current mirror is used for mirroring the current output of the reduced adjusting tube to the grid electrode of the adjusting tube according to a set proportion. Comparing the acquired output voltage with the input reference voltage through an error amplification module, and driving an adjusting tube by using the generated error calibration signal to enable the adjusting tube to provide current required by a load; the buffer module isolates the output impedance of the error amplification module and the parasitic capacitance of the grid electrode of the adjusting tube, which is beneficial to frequency compensation, and the buffer module can also increase the slew rate of the grid end of the adjusting tube, thereby improving the transient response capability of the LDO; the current of the current mirror image adjusting tube in the transient enhancement module does not increase extra power consumption under the condition of low load current, and the mirrored current increases the current of the buffer module under the condition of high load current, so that the output impedance of the buffer module is reduced, the parasitic pole of the output end is pushed to a higher frequency, the grid end of the adjusting tube is charged, the available current under the same slew rate is improved, and the transient response performance of the LDO is further improved.
Fig. 2 is a schematic diagram of a linear voltage regulator according to another embodiment of the present utility model, where, based on the above embodiment, as shown IN fig. 2, optionally, the buffer module 20 includes a first transistor M1 and a second transistor M2, a gate of the first transistor M1 is connected to the third input terminal IN3, a first pole of the first transistor M1 is connected to an output terminal of the buffer module 20, and a second pole of the first transistor M1 is grounded GND.
The gate of the second transistor M2 is connected to the fourth input terminal IN4, the first pole of the second transistor M2 is connected to the power supply VDD, and the second pole of the second transistor M2 is connected to the output terminal of the buffer module 20.
The error amplifying module 10 includes an operational amplifier OP, wherein a non-inverting input end of the operational amplifier OP is connected to the first input end IN1 of the error amplifying module 10, an inverting input end of the operational amplifier OP is connected to the second input end IN2 of the error amplifying module, and an output end of the operational amplifier OP is connected to an output end of the error amplifying module 10.
The linear voltage stabilizer further comprises a voltage division output module 40, wherein the voltage division output module 40 is connected between the second pole of the adjusting tube MP and the ground GND, and the voltage division output module 40 is configured to output a voltage to an output terminal of the linear voltage stabilizer according to the current of the adjusting tube MP.
The voltage division output module 40 includes a first resistor R1 and a second resistor R2, where the first resistor R1 and the second resistor R2 are connected in series between the second pole of the regulator MP and the ground GND, and a common terminal a of the first resistor R1 and the second resistor R2 is connected to an output terminal of the linear voltage regulator.
The linear voltage stabilizer further comprises a capacitor Co, a first end of the capacitor Co is connected with the output end of the linear voltage stabilizer, and a second end of the capacitor Co is grounded to GND.
The linear voltage regulator further includes a bias voltage supply circuit 50, the bias voltage supply circuit 50 being electrically connected to the fourth input terminal IN4 for supplying the bias voltage VB to the buffer module 20.
The working process of the linear voltage stabilizer is as follows:
the first resistor R1 and the second resistor R2 collect the output voltage Vout of the output end of the linear voltage stabilizer, the collected voltage is input to the non-inverting input end of the operational amplifier OP, the collected voltage is compared with the reference voltage VREF of the inverting input end of the operational amplifier OP, the comparison result is amplified, the amplified signal is output to the grid electrode of the first transistor M1, the first transistor M1 is conducted, the amplified voltage signal can control the conducted voltage of the regulating tube MP, the output voltage Vout of the output end of the linear voltage stabilizer is equal to the voltage of the power supply VDD minus the conducted voltage, and therefore the conducted voltage of the regulating tube MP is controlled to be equal to the output voltage Vout of the LDO.
When the output voltage Vout drops due to load variation or other reasons, that is, the voltage at the common terminal a drops, the potential at the common terminal a is transmitted to the non-inverting input terminal of the operational amplifier OP through the feedback network, and compared with the reference voltage VREF at the inverting input terminal of the operational amplifier OP, the output voltage of the operational amplifier OP decreases, the first transistor M1 is turned on, so that the voltage at the gate of the regulator MP drops, the voltage at the source of the regulator MP does not change, further, the absolute value |vgs| of the voltage difference between the gate and the source of the regulator MP increases, the drain current of the regulator MP increases, the output current increases, and the capacitor Co is charged, so that the output voltage Vout rises, and one feedback control is completed, so that the potential at the common terminal a returns to the normal potential. When the output voltage Vout increases, the voltage at the common terminal a increases, the output voltage of the operational amplifier OP increases, the first transistor M1 is turned on, so that the voltage at the gate of the regulator MP increases, the voltage at the source of the regulator MP does not change, and further the absolute value |vgs| of the voltage difference between the gate and the source of the regulator MP decreases, the drain current of the regulator MP decreases, the output current decreases, the capacitor Co discharges to supply current to the load, and the output voltage Vout at the output terminal of the LDO decreases. Therefore, the feedback voltage fed back to the operational amplifier OP is also reduced, the output voltage of the operational amplifier OP is reduced, at this time, the first transistor M1 connected to the output end of the operational amplifier OP is turned on to provide a large pull-down current for the gate of the regulator MP, the voltage of the gate of the regulator MP is pulled down accordingly, the absolute value |vgs| of the voltage difference between the gate and the source of the regulator MP is increased, the output current of the load is increased, the capacitor Co stops discharging, the output voltage Vout at the output end of the LDO is not reduced any more, and the voltage starts to rise. Therefore, the linear voltage stabilizer is always in a deep negative feedback state, and continuously corrects the output voltage Vout of the LDO output end, so that the output voltage Vout of the LDO output end is always stable.
Fig. 3 is a schematic structural diagram of another linear voltage regulator according to an embodiment of the present utility model. This embodiment IS based on the embodiment of fig. 1, and as shown in fig. 3, the transient enhancement module 30 optionally includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a current source IS.
The gate of the third transistor M3 IS connected to the gate of the adjusting transistor MP, the first pole of the third transistor M3 and the first pole of the adjusting transistor MP are both connected to the power supply VDD and the first end of the current source IS, and the second pole of the third transistor M3 IS connected to the second end of the current source IS.
The grid electrode of the fourth transistor M4 is connected with the grid electrode of the fifth transistor M5, and the first electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5 are both connected with the power supply VDD; the second pole of the fourth transistor M4 is connected with the grid electrode of the adjusting transistor MP, and the second pole of the fifth transistor M5 is connected with the first pole of the sixth transistor M6; the gate of the fifth transistor M5 is connected to the second pole of the fifth transistor M5.
The gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7, the second pole of the sixth transistor M6 is grounded GND, the first pole of the seventh transistor M7 is connected to the second pole of the third transistor M3, and the second pole of the seventh transistor M7 is grounded GND.
Wherein, the second end of the current source IS connected to the power supply VDD. The third transistor M3, the fourth transistor M4, and the fifth transistor M5 of the transient enhancement module 30 each include PMOS, and the sixth transistor M6 and the seventh transistor M7 each include NMOS.
The error amplifying module 10 includes an operational amplifier OP, wherein a non-inverting input end of the operational amplifier OP is connected to the first input end IN1 of the error amplifying module 10, an inverting input end of the operational amplifier OP is connected to the second input end IN2 of the error amplifying module, and an output end of the operational amplifier OP is connected to an output end of the error amplifying module 10.
The linear voltage stabilizer further comprises a voltage division output module 40, wherein the voltage division output module 40 is connected between the second pole of the adjusting tube MP and the ground GND, and the voltage division output module 40 is configured to output a voltage to an output terminal of the linear voltage stabilizer according to the current of the adjusting tube MP.
The voltage division output module 40 includes a first resistor R1 and a second resistor R2, where the first resistor R1 and the second resistor R2 are connected in series between the second pole of the regulator MP and the ground GND, and a common terminal a of the first resistor R1 and the second resistor R2 is connected to an output terminal of the linear voltage regulator.
The linear voltage stabilizer further comprises a capacitor Co, a first end of the capacitor Co is connected with the output end of the linear voltage stabilizer, and a second end of the capacitor Co is grounded to GND.
The linear voltage regulator further includes a bias voltage supply circuit 50, the bias voltage supply circuit 50 being electrically connected to the fourth input terminal IN4 for supplying the bias voltage VB to the buffer module 20.
The current of the adjusting transistor MP is reduced by mirroring the third transistor M3, and the size ratio of the third transistor M3 to the adjusting transistor MP is 1: x is a metal alloy. X is generally in the range of 1000 to 100000. Optionally, the size ratio of the fourth transistor M4 to the fifth transistor is 1:1, and the size ratio of the sixth transistor M6 to the seventh transistor M7 is 1:1.
Before the transient enhancement module 30 is not present, the charging and discharging current Isr of the LDO to the regulator MP is equal to the bias current Ibias.
After adding the transient enhancement module 30, the LDO charges and discharges the current to the regulating tube MP
Where X represents the size of the third transistor M3. Id3 represents the current at the drain of the third transistor M3.
The transient response time of the LDO loop is delta-Vpo, and is mainly determined by the closed loop bandwidth BW of the LDO system, the parasitic capacitance Cpar of the grid electrode of the regulating tube MP and the charge-discharge current Isr of the regulating tube MP. LDO loop transient response time Deltat 1 The output voltage variation Δvpo caused by the LDO output load variation is also affected. The output voltage variation Δvpo is determined by the capacitance Co of the LDO, the equivalent series resistance ESR of the capacitance Co, and the maximum load current iload_max. The relationship is as follows:
wherein DeltaV Cpar Indicating the change of the gate voltage of the regulator tube MP; deltaV ESR The voltage change across the equivalent series resistance ESR of the capacitor Co is shown. It can be seen that by increasing the charge-discharge current Isr of the regulator MP, the transient response time Δt1 can be reduced, and thus the output voltage variation Δvpo of the LDO due to the load current variation can be reduced, thereby improving the transient response performance of the LDO.
The transient enhancement module 30 operates as follows:
when the output current is smaller, the current flowing through the adjusting transistor MP is smaller, the current mirrored to the third transistor M3 is also smaller, and the current is mirrored to the fourth transistor M4 and the fifth transistor M5 through the current mirror, at this time, the currents of the fourth transistor M4 and the fifth transistor M5 are both smaller, and the static power consumption of the LDO is hardly increased. When the output current increases, the current mirror formed by the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 can mirror the current of the adjusting transistor MP according to a certain proportion, the current after mirror reduction is outputted to the gate of the adjusting transistor MP by the fourth transistor M4 as the charging current of the adjusting transistor MP, at this time, the voltage of the gate of the adjusting transistor MP is pulled up, so that the absolute value |vgs| of the voltage difference between the gate and the source of the adjusting transistor MP is reduced, the adjusting transistor MP is turned off gradually, the capacitor Co stops charging, and the output voltage Vout stops rising and begins to fall back gradually.
Fig. 4 is a schematic structural diagram of another linear voltage regulator according to an embodiment of the present utility model. This embodiment IS based on the embodiment of fig. 2, and as shown in fig. 4, the transient enhancement module 30 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a current source IS.
The gate of the third transistor M3 IS connected to the gate of the adjusting transistor MP, the first pole of the third transistor M3 and the first pole of the adjusting transistor MP are both connected to the power supply VDD and the first end of the current source IS, and the second pole of the third transistor M3 IS connected to the second end of the current source IS.
The grid electrode of the fourth transistor M4 is connected with the grid electrode of the fifth transistor M5, and the first electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5 are both connected with the power supply VDD; the second pole of the fourth transistor M4 is connected with the grid electrode of the adjusting transistor MP, and the second pole of the fifth transistor M5 is connected with the first pole of the sixth transistor M6; the gate of the fifth transistor M5 is connected to the second pole of the fifth transistor M5.
The gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7, the second pole of the sixth transistor M6 is grounded GND, the first pole of the seventh transistor M7 is connected to the second pole of the third transistor M3, and the second pole of the seventh transistor M7 is grounded GND.
The first transistor M1 and the second transistor M2 of the buffer module 20, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 of the transient enhancement module 30 each include PMOS, and the sixth transistor M6 and the seventh transistor M7 each include NMOS.
The working process of the linear voltage stabilizer is as follows:
the first resistor R1 and the second resistor R2 collect the output voltage Vout of the output end of the linear voltage stabilizer, the collected voltage is input to the non-inverting input end of the operational amplifier OP, the collected voltage is compared with the reference voltage VREF of the inverting input end of the operational amplifier OP, the comparison result is amplified, the amplified signal is output to the grid electrode of the first transistor M1, the first transistor M1 is conducted, the amplified voltage signal can control the conducted voltage of the regulating tube MP, the output voltage Vout of the output end of the linear voltage stabilizer is equal to the voltage of the power supply VDD minus the conducted voltage, and therefore the conducted voltage of the regulating tube MP is controlled to be equal to the output voltage Vout of the LDO.
When the voltage of the output voltage Vout drops due to load variation or other reasons, that is, the voltage of the common terminal a drops, the potential of the common terminal a is transmitted to the non-inverting input terminal of the operational amplifier OP through the feedback network, and compared with the reference voltage VREF of the inverting input terminal of the operational amplifier OP, the output voltage of the operational amplifier OP decreases, the first transistor M1 is turned on, so that the voltage of the gate of the regulator MP drops, the voltage of the source of the regulator MP is unchanged, the absolute value |vgs| of the voltage difference between the gate and the source of the regulator MP increases, the drain current of the regulator MP increases, the output current increases, and the capacitor Co is charged, so that the output voltage Vout rises, at this time, the current mirror formed by the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 can mirror the current of the regulator MP according to a certain proportion, the current after mirror image reduction is outputted to the gate of the regulator MP as the charging current of the regulator MP, the voltage of the regulator MP is gradually stopped as the charging current of the regulator MP, the absolute value of the regulator MP stops gradually decreasing when the voltage of the regulator MP increases, the voltage of the drain current of the regulator MP increases, the output current of the regulator MP increases, the capacitor increases, the output current of the regulator MP increases, and the capacitor Co increases, and the voltage of the regulator MP increases accordingly increases, and the voltage of the regulator MP gradually decreases.
When the output voltage Vout increases, the voltage at the common terminal a increases, the output voltage of the operational amplifier OP increases, the first transistor M1 is turned on, so that the voltage at the gate of the regulator MP increases, the voltage at the source of the regulator MP does not change, and further the absolute value |vgs| of the voltage difference between the gate and the source of the regulator MP decreases, the drain current of the regulator MP decreases, the capacitor Co discharges to supply current to the load, and the output voltage Vout at the output terminal of the LDO decreases. Therefore, the feedback voltage fed back to the operational amplifier OP is also reduced, the output voltage of the operational amplifier OP is reduced, at this time, the first transistor M1 connected to the output end of the operational amplifier OP is turned on to provide a large pull-down current for the gate of the regulator MP, the voltage of the gate of the regulator MP is pulled down accordingly, the absolute value |vgs| of the voltage difference between the gate and the source of the regulator MP is increased, the output current of the load is increased, the capacitor Co stops discharging, the output voltage Vout at the output end of the LDO is not reduced any more, and the voltage starts to rise. Therefore, the linear voltage stabilizer is always in a deep negative feedback state, and continuously corrects the output voltage Vout of the LDO output end, so that the output voltage Vout of the LDO output end is always stable.
The embodiment of the utility model also provides a system on a chip, which comprises the linear voltage stabilizer in any embodiment, and has the corresponding functional modules and beneficial effects of the linear voltage stabilizer.
Note that the above is only a preferred embodiment of the present utility model and the technical principle applied. It will be understood by those skilled in the art that the present utility model is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, while the utility model has been described in connection with the above embodiments, the utility model is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the utility model, which is set forth in the following claims.
Claims (10)
1. A linear voltage regulator, comprising: the device comprises an error amplifying module, a buffer module, a transient enhancing module and an adjusting tube;
the first input end of the error amplification module is connected with the output end of the linear voltage stabilizer, the second input end of the error amplification module is connected with reference voltage, and the output end of the error amplification module is connected with the third input end of the buffer module;
the fourth input end of the buffer module is connected with bias voltage, the output end of the buffer module is connected with the grid electrode of the adjusting tube, and the buffer module is used for outputting control voltage to the grid electrode of the adjusting tube according to the voltages of the third input end and the fourth input end;
the transient enhancement module comprises a current mirror, and the current mirror is used for mirror-image reducing the current output of the adjusting tube to the grid electrode of the adjusting tube according to a set proportion.
2. The linear voltage regulator of claim 1, wherein the buffer module comprises a first transistor and a second transistor, a gate of the first transistor being connected to the third input terminal, a first pole of the first transistor being connected to an output terminal of the buffer module, a second pole of the first transistor being grounded;
the grid electrode of the second transistor is connected with the fourth input end, the first electrode of the second transistor is connected with a power supply, and the second electrode of the second transistor is connected with the output end of the buffer module.
3. The linear voltage regulator according to claim 1 or 2, wherein the transient enhancement module comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a current source;
the grid electrode of the third transistor is connected with the grid electrode of the adjusting transistor, the first electrode of the third transistor and the first electrode of the adjusting transistor are both connected with a power supply and the first end of the current source, and the second electrode of the third transistor is connected with the second end of the current source;
the grid electrode of the fourth transistor is connected with the grid electrode of the fifth transistor, and the first electrode of the fourth transistor and the first electrode of the fifth transistor are both connected with the power supply; a second pole of the fourth transistor is connected with the grid electrode of the adjusting transistor, and a second pole of the fifth transistor is connected with the first pole of the sixth transistor; the grid electrode of the fifth transistor is connected with the second electrode of the fifth transistor;
the gate of the sixth transistor is connected with the gate of the seventh transistor, the second pole of the sixth transistor is grounded, the first pole of the seventh transistor is connected with the second pole of the third transistor, and the second pole of the seventh transistor is grounded.
4. The linear voltage regulator of claim 3, wherein the first transistor and the second transistor of the buffer module, the third transistor, the fourth transistor, and the fifth transistor of the transient enhancement module each comprise PMOS, and the sixth transistor and the seventh transistor each comprise NMOS.
5. The linear voltage regulator of claim 1, wherein the error amplification module comprises an operational amplifier, a non-inverting input of the operational amplifier is connected to a first input of the error amplification module, an inverting input of the operational amplifier is connected to a second input of the error amplification module, and an output of the operational amplifier is connected to an output of the error amplification module.
6. The linear voltage regulator of claim 1, further comprising a voltage division output module connected between the second pole of the regulator tube and ground, the voltage division output module configured to output a voltage to an output terminal of the linear voltage regulator according to a current of the regulator tube.
7. The linear voltage regulator of claim 6, wherein the voltage division output module comprises a first resistor and a second resistor, the first resistor and the second resistor are connected in series between a second pole of the regulator tube and ground, and a common terminal of the first resistor and the second resistor is connected to an output terminal of the linear voltage regulator.
8. The linear voltage regulator of claim 6, further comprising a capacitor, a first end of the capacitor being connected to the output of the linear voltage regulator, a second end of the capacitor being grounded.
9. The linear voltage regulator of claim 1, further comprising a bias voltage supply circuit electrically connected to the fourth input for providing the bias voltage to the buffer module.
10. A system on a chip comprising a linear voltage regulator according to any one of claims 1-9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320181385.0U CN219143338U (en) | 2023-02-10 | 2023-02-10 | Linear voltage stabilizer and system on chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320181385.0U CN219143338U (en) | 2023-02-10 | 2023-02-10 | Linear voltage stabilizer and system on chip |
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| CN219143338U true CN219143338U (en) | 2023-06-06 |
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