CN116185115A - LDO composite zero tracking compensation circuit - Google Patents
LDO composite zero tracking compensation circuit Download PDFInfo
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- CN116185115A CN116185115A CN202211742890.4A CN202211742890A CN116185115A CN 116185115 A CN116185115 A CN 116185115A CN 202211742890 A CN202211742890 A CN 202211742890A CN 116185115 A CN116185115 A CN 116185115A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses an LDO composite zero tracking compensation circuit which comprises an error amplifier (AMP 1), a Buffer (BUF), a compensation MOS tube (Mc), a compensation capacitor (Cc), a first resistor (R1), a second resistor (R2), a first MOS tube (M11), a second MOS tube (M12), a third MOS tube (M13), a fourth MOS tube (M14), a fifth MOS tube (M15), a sixth MOS tube (M16), a seventh MOS tube (M17) and an eighth MOS tube (M18). The invention can solve the technical problem that the zero generated by the current single voltage-controlled resistor is not matched with the movement rate of the output pole, so that the movement rate of the zero is also in direct proportion to the load current, and the zero movement rate is ensured to be the same as the movement rate of the output pole, thereby thoroughly realizing the global effective compensation of the LDO.
Description
Technical Field
The invention belongs to the technical field of LDO compensation, and particularly relates to an LDO composite zero tracking compensation circuit.
Background
LDOs are used as the forefront of low-voltage electronic systems to provide stable power supplies for the following electronic devices, and their stability directly determines the performance and lifetime of the following electronic devices. LDO steps down the preceding stage power supply and keeps the output in a stable state based on negative feedback, and mainly comprises a voltage reference, an error amplifier, a power tube and a feedback network. When the power tube is in operation, the error amplifier amplifies the difference value between the voltage fed back by the feedback network and the reference voltage, then directly or indirectly controls the conduction degree of the power tube, and stabilizes the output voltage at a preset output value through the feedback loop.
FIG. 1 is a schematic diagram of the basic structure of an LDO. For LDOs with large load range, the output poles can change in a large range along with the load change, so that the pole distribution of the LDO system has the risk of coincidence, and therefore, an additional compensation means is needed to assist the system to achieve stability. The general method adopts a zero tracking compensation scheme, and utilizes an MOS tube as a voltage-controlled resistor to generate a dynamic zero to offset the influence of an output pole. However, the rate of change of the zero point and the output pole generated by a single voltage-controlled resistor along with the load is different, and the zero point moving speed is larger than the moving speed of the output pole in light load, so that the loop is easy to be unstable, and the ideal compensation effect cannot be obtained in the full load range. The pole-zero distribution of a conventional LDO system is shown in fig. 2. Referring to fig. 2, the values of the parameters are as follows:
wherein p1 is the output pole of the first stage of the error amplifier, R o1 C is the output impedance of the error amplifier o1 The capacitor is connected with the error amplifier. p2 is the output pole of LDO, r out For LDO output node impedance, C out Is the output capacitance. z 1 The ESR zero, which is parasitic to the output capacitance, is typically located outside the bandwidth.
Except for the light load condition, the system main pole is the output pole of the error amplifier. The secondary pole is the output pole. Since the output node impedance is inversely proportional to the load current, the output pole will move with the load size. When the load is continuously reduced, the LDO output pole coincides with the error amplifier output pole, which causes rapid deterioration of the phase margin. One possible approach is to use zero tracking to generate a zero point that also moves with the load. The system phase reduction caused by the LDO output pole can be slowed down under different load conditions. But the zero point can not completely offset the influence of the output pole, and because the pole generated by other nodes besides the primary pole and the secondary pole is also positioned in the bandwidth under the light load condition of the system, the generated zero point is required to slow down the phase drop caused by the output pole and ensure the drop of the system gain as early as possible. The overall compensated zero optimum setting effect is to follow the output pole movement while ensuring a lag behind the output pole.
The conventional compensation mode adopts a voltage-controlled resistor to generate a dynamic zero point, and the compensation mode is shown in fig. 3. Zero z generated c The method meets the following conditions:
assuming that the power tube is located in the saturation region, +.>
Namely, the output pole p 2. Alpha. I out . And the power tube controls the voltage V p The method meets the following conditions: />
For R c The resistor is positioned in the linear resistor area, and takes the value as follows:
i.e. dynamic zero z c The method meets the following conditions:
it can be seen that the output pole and the compensation zero are not consistent with the trend of load variation, so that it is difficult to realize the real state in the whole load rangeIdeal phase compensation is achieved. Zero z c And when the load current is larger, the output pole can be guaranteed to move towards the low-frequency pole along with the output pole, and the output pole is guaranteed to lag behind the output pole. However, the zero point falling speed is faster, so that the zero point gradually catches up with the pole in light load, the loop gain is reduced later, the loop stability is further unfavorable, and the relative position of the zero point is compensated in the prior art as shown in fig. 4.
The invention with the patent number of CN202111161887.9 discloses a small-area rapid transient response full-on-chip integrated LDO circuit, an output power tube is driven by a large-swing high-gain amplifier, the size and the chip area of the output power tube are reduced, the loop gain of the LDO is increased, and the recovery time of output voltage is shortened. In addition, the load current partition frequency compensation circuit is adopted for frequency compensation, so that the LDO is ensured to be stable under all load conditions without sacrificing the loop gain bandwidth, and the noise suppression capability of the high-frequency power supply is enhanced; the compensation circuit does not consume static current and has smaller area, thereby reducing the static power consumption of the LDO and the area of the chip. However, the invention cannot fundamentally change the compensation rate and cannot completely solve the problem of global compensation of the LDO.
Disclosure of Invention
The technical problems to be solved are as follows: the invention aims to overcome the defects in the prior art and provides an LDO composite zero tracking compensation circuit so as to solve the technical problem that the current single voltage-controlled resistor generates zero and the movement rate of an output pole is not matched.
The technical scheme is as follows:
an LDO composite zero tracking compensation circuit comprises an error amplifier (AMP 1), a Buffer (BUF), a compensation MOS tube (Mc), a compensation capacitor (Cc), a first resistor (R1), a second resistor (R2), a first MOS tube (M11), a second MOS tube (M12), a third MOS tube (M13), a fourth MOS tube (M14), a fifth MOS tube (M15), a sixth MOS tube (M16), a seventh MOS tube (M17) and an eighth MOS tube (M18);
the drain electrode of the compensation MOS tube (Mc) is connected with the compensation capacitor (Cc), the source electrode is connected with the FB end of the error amplifier (AMP 1) and the input end of the Buffer (BUF), and the grid electrode is connected to the drain electrode of the sixth MOS tube (M16); the output end of the Buffer (BUF) is respectively connected with the source electrodes of the first resistor (R1), the second resistor (R2), the third MOS tube (M13) and the fourth MOS tube (M14); one end of the first resistor (R1) which is not connected with the Buffer (BUF) is connected with the drain electrode of the first MOS tube (M11), and one end of the second resistor (R2) which is not connected with the Buffer (BUF) is respectively connected with the drain electrodes of the sixth MOS tube (M16) and the seventh MOS tube (M17);
the input end of the error amplifier (AMP 1) is respectively connected with a reference voltage and a feedback voltage, the OUT end of the error amplifier is connected with the input end of the Buffer (BUF) and the source end of the compensation MOS tube (Mc), and the FB end of the error amplifier is connected with one end of the compensation capacitor (Cc) far away from the compensation MOS tube (Mc);
the grid electrode of the third MOS tube (M13) is respectively connected with the drain electrode of the fourth MOS tube (M14) and the drain electrode of the fifth MOS tube (M15); the drain electrode of the third MOS tube (M13) is respectively connected with the grid electrode of the first MOS tube (M11), the grid electrode of the second MOS tube (M12) and the grid electrode of the sixth MOS tube (M16); the grid electrode of the seventh MOS tube (M17) and the grid electrode of the eighth MOS tube (M18) are connected with each other;
the sources of the first MOS tube (M11), the second MOS tube (M12), the fifth MOS tube (M15), the sixth MOS tube (M16), the seventh MOS tube (M17) and the eighth MOS tube (M18) are connected with GND;
impedance R of the compensation MOS tube (Mc) c Inversely proportional to the load current, the zero is proportional to the load current, and the zero movement rate is the same as the output pole movement rate.
Further, the impedance R of the compensation MOS tube (Mc) c The method comprises the following steps:
wherein mu is p Is electron mobility; c (C) ox A gate oxide capacitance per unit area;
the width-to-length ratio of the MOS tube is compensated; v (V) thp Is the threshold value of the PMOS tube; k is the transfer ratio of the current mirrors M17 and M18.
Further, the error amplifier (AMP 1) employs a folded cascode structure of PMOS inputs with reference and feedback voltages extending to low common mode voltage conditions.
Further, the first MOS tube (M11), the second MOS tube (M12), the sixth MOS tube (M16), the seventh MOS tube (M17) and the eighth MOS tube (M18) adopt N-channel MOS tubes; the compensation MOS tube (Mc), the fourth MOS tube (M14) and the fifth MOS tube (M15) adopt P-channel MOS tubes.
The beneficial effects are that:
the LDO composite zero tracking compensation circuit fundamentally improves the technical problem that the zero moving speed and the pole are not matched in the prior art, ensures that the moving speed of the zero is also in direct proportion to load current, ensures that the moving speed of the zero is the same as the moving speed of the output pole, and thoroughly realizes the full-domain effective compensation of the LDO.
Drawings
FIG. 1 is a schematic diagram of the basic structure of an LDO;
FIG. 2 is a schematic diagram of LDO pole-zero distribution;
FIG. 3 is a schematic diagram of a conventional zero tracking compensation circuit;
FIG. 4 is a schematic diagram of the relative positions of the conventional compensation zero poles;
FIG. 5 is a schematic diagram of an LDO composite zero tracking compensation circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a modified pole-zero distribution.
Detailed Description
The following examples will provide those skilled in the art with a more complete understanding of the invention, but are not intended to limit the invention in any way.
Fig. 5 is a schematic diagram of an LDO composite zero tracking compensation circuit according to an embodiment of the present invention. Referring to fig. 5, the LDO composite zero tracking compensation circuit includes an error amplifier AMP1, a buffer BUF, a compensation MOS tube Mc, a compensation capacitor Cc, a first resistor R1, a second resistor R2, a first MOS tube M11, a second MOS tube M12, a third MOS tube M13, a fourth MOS tube M14, a fifth MOS tube M15, a sixth MOS tube M16, a seventh MOS tube M17, and an eighth MOS tube M18.
The drain electrode of the compensation MOS tube Mc is connected with the compensation capacitor Cc, the source electrode is connected with the FB end of the error amplifier AMP1 and the input end of the buffer BUF, and the grid electrode is connected to the drain electrode of the sixth MOS tube M16; the output end of the buffer BUF is respectively connected with the source electrodes of the first resistor R1, the second resistor R2, the third MOS tube M13 and the fourth MOS tube M14; one end of the first resistor R1, which is not connected with the buffer BUF, is connected with the drain electrode of the first MOS tube M11, and one end of the second resistor R2, which is not connected with the buffer BUF, is respectively connected with the drain electrodes of the sixth MOS tube M16 and the seventh MOS tube M17.
The input end of the error amplifier AMP1 is respectively connected with the reference voltage and the feedback voltage, the OUT end is connected with the input end of the buffer BUF and the source end of the compensation MOS tube Mc, and the FB end is connected with one end of the compensation capacitor Cc far away from the compensation MOS tube Mc.
The grid electrode of the third MOS tube M13 is respectively connected with the drain electrode of the fourth MOS tube M14 and the drain electrode of the fifth MOS tube M15; the drain electrode of the third MOS tube M13 is respectively connected with the grid electrode of the first MOS tube M11, the grid electrode of the second MOS tube M12 and the grid electrode of the sixth MOS tube M16; the grid electrode of the seventh MOS tube M17 and the grid electrode of the eighth MOS tube M18 are connected with each other.
The sources of the first MOS tube M11, the second MOS tube M12, the fifth MOS tube M15, the sixth MOS tube M16, the seventh MOS tube M17 and the eighth MOS tube M18 are connected with GND.
Impedance R of the compensation MOS tube Mc c Inversely proportional to the load current, the zero is proportional to the load current, and the zero movement rate is the same as the output pole movement rate.
Impedance R of the compensation MOS tube Mc c Inversely proportional to the load current, the zero is proportional to the load current, and the zero movement rate is the same as the output pole movement rate. V in FIG. 5 b Is the bias voltage of the tail current source M15, biasing M15 in the subthreshold state.
The second MOS transistor M12, the first MOS transistor M11 and the sixth MOS transistor M16 have the same size, and the flowing currents are equal. The current of the left half part of the second resistor R2 lets the output node of the resistorVoltage equal to VDD-V thp The current in the right half of the second resistor R2 varies with the load current, and Iout' is proportional to the output current. The superimposed current flows through the second resistor R2, so that the final output voltage of the resistor is VDD-V thk X Iout' ×r. R1 and R2 have R resistance values.
When the voltage is connected to the compensation MOS tube Mc, the impedance of Mc in the linear region is:
wherein mu p Is electron mobility; c (C) ox A gate oxide capacitance per unit area;
the width-to-length ratio of the MOS tube is compensated; v (V) thp Is the threshold value of the PMOS tube; k is the transfer ratio of the current mirrors M17 and M18. That is, the impedance of Mc is inversely proportional to the load current, the zero is directly proportional to the load current, and the same speed as the movement speed of the output pole is ensured. Fig. 6 is a schematic diagram of a modified pole-zero distribution.
Compared with the traditional zero tracking compensation scheme, the LDO composite zero tracking compensation circuit provided by the embodiment can solve the problem that the voltage-controlled zero moves too fast under the light load condition, so that the moving speed of the zero is the same as the moving speed of the output pole, the zero keeps the distance from the output pole while moving along with the output pole, and the loop stability in the full load range is ensured.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (4)
1. The LDO composite zero tracking compensation circuit is characterized by comprising an error amplifier (AMP 1), a Buffer (BUF), a compensation MOS tube (Mc), a compensation capacitor (Cc), a first resistor (R1), a second resistor (R2), a first MOS tube (M11), a second MOS tube (M12), a third MOS tube (M13), a fourth MOS tube (M14), a fifth MOS tube (M15), a sixth MOS tube (M16), a seventh MOS tube (M17) and an eighth MOS tube (M18);
the drain electrode of the compensation MOS tube (Mc) is connected with the compensation capacitor (Cc), the source electrode is connected with the FB end of the error amplifier (AMP 1) and the input end of the Buffer (BUF), and the grid electrode is connected to the drain electrode of the sixth MOS tube (M16); the output end of the Buffer (BUF) is respectively connected with the source electrodes of the first resistor (R1), the second resistor (R2), the third MOS tube (M13) and the fourth MOS tube (M14); one end of the first resistor (R1) which is not connected with the Buffer (BUF) is connected with the drain electrode of the first MOS tube (M11), and one end of the second resistor (R2) which is not connected with the Buffer (BUF) is respectively connected with the drain electrodes of the sixth MOS tube (M16) and the seventh MOS tube (M17);
the input end of the error amplifier (AMP 1) is respectively connected with a reference voltage and a feedback voltage, the OUT end of the error amplifier is connected with the input end of the Buffer (BUF) and the source end of the compensation MOS tube (Mc), and the FB end of the error amplifier is connected with one end of the compensation capacitor (Cc) far away from the compensation MOS tube (Mc);
the grid electrode of the third MOS tube (M13) is respectively connected with the drain electrode of the fourth MOS tube (M14) and the drain electrode of the fifth MOS tube (M15); the drain electrode of the third MOS tube (M13) is respectively connected with the grid electrode of the first MOS tube (M11), the grid electrode of the second MOS tube (M12) and the grid electrode of the sixth MOS tube (M16); the grid electrode of the seventh MOS tube (M17) and the grid electrode of the eighth MOS tube (M18) are connected with each other;
the sources of the first MOS tube (M11), the second MOS tube (M12), the fifth MOS tube (M15), the sixth MOS tube (M16), the seventh MOS tube (M17) and the eighth MOS tube (M18) are connected with GND;
impedance R of the compensation MOS tube (Mc) c Inversely proportional to the load current, the zero is proportional to the load current, and the zero movement rate is the same as the output pole movement rate.
2. The LDO complex zero tracking compensation circuit of claim 1, wherein the compensation MOS tube (Mc) has an impedance R c The method comprises the following steps:
wherein mu is p Is electron mobility; c (C) ox A gate oxide capacitance per unit area;
the width-to-length ratio of the MOS tube is compensated; v (V) thp Threshold for PM0S pipe; k is the transfer ratio of the current mirrors M17 and M18.
3. The LDO compound zero tracking compensation circuit of claim 1, wherein the error amplifier (AMP 1) employs a folded cascode structure of PMOS inputs with reference and feedback voltages extending to low common mode voltage conditions.
4. The LDO composite zero tracking compensation circuit according to claim 1, wherein the first MOS tube (M11), the second MOS tube (M12), the sixth MOS tube (M16), the seventh MOS tube (M17) and the eighth MOS tube (M18) are N-channel MOS tubes; the compensation MOS tube (Me), the fourth MOS tube (M14) and the fifth MOS tube (M15) adopt P-channel MOS tubes.
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| CN202211742890.4A CN116185115A (en) | 2022-12-31 | 2022-12-31 | LDO composite zero tracking compensation circuit |
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| CN202211742890.4A CN116185115A (en) | 2022-12-31 | 2022-12-31 | LDO composite zero tracking compensation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116707467A (en) * | 2023-08-04 | 2023-09-05 | 核芯互联科技(青岛)有限公司 | class-AB structure voltage buffer suitable for large capacitive load |
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- 2022-12-31 CN CN202211742890.4A patent/CN116185115A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116707467A (en) * | 2023-08-04 | 2023-09-05 | 核芯互联科技(青岛)有限公司 | class-AB structure voltage buffer suitable for large capacitive load |
| CN116707467B (en) * | 2023-08-04 | 2023-12-05 | 核芯互联科技(青岛)有限公司 | class-AB structure voltage buffer suitable for large capacitive load |
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