CN113467559B

CN113467559B - Adaptive dynamic zero compensation circuit applied to LDO (low dropout regulator)

Info

Publication number: CN113467559B
Application number: CN202110768317.XA
Authority: CN
Inventors: 周泽坤; 王世杰; 李世磊; 王卓; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2021-07-07
Filing date: 2021-07-07
Publication date: 2022-03-08
Anticipated expiration: 2041-07-07
Also published as: CN113467559A

Abstract

The invention belongs to the technical field of analog circuit power management, and particularly relates to a self-adaptive dynamic zero compensation circuit applied to an LDO (low dropout regulator). The invention forms a compensation zero point related to an output pole at a feedback point through two active current paths, and the two currents are respectively an output current and an output sampling current. Since the output current passes through the load impedance when being superimposed with the output sampling current, the current path related to the output current contains information about the load impedance, and the two current branches are superimposed to form a compensation zero related to the output pole. The compensation zero point not only contains the information of the output resistor, but also contains the information of the output capacitor, so when the output capacitor changes, the compensation zero point can change along with the output pole at the same time, and the stability of a loop is ensured. And meanwhile, the problem that the response speed of the circuit is reduced due to overcompensation under heavy load conditions is avoided.

Description

Adaptive dynamic zero compensation circuit applied to LDO (low dropout regulator)

Technical Field

The invention belongs to the technical field of analog circuit power management, and particularly relates to a self-adaptive dynamic zero compensation circuit applied to an LDO (low dropout regulator).

Background

Low dropout linear regulator (LDO) is a very important module in the field of power management circuits, and functions to convert an external power supply voltage into a lower and more stable voltage. When the load changes, the LDO can automatically adjust the output current of the power tube, so that the output voltage is kept at a stable value.

The LDOs can be classified into NMOS LDOs and PMOS LDOs according to whether the power transistors used are NMOS power transistors or PMOS power transistors. In order to ensure that the power tube still has a certain gate-source voltage when the input-output voltage difference is small, the NMOS LDO needs to add an additional charge pump circuit to raise the gate voltage of the NMOS power tube, which may introduce additional power consumption. The PMOS LDO is a structure which is commonly used at present, because the grid-source voltage of the PMOS power tube can be adjusted between the input voltage and the ground potential; and the PMOS LDO does not need an additional auxiliary circuit, and the main loop of the PMOS LDO can work normally. In addition, the PMOS LDO power stage has amplification effect, so that the compensating circuit is easier to design compared with the NMOS LDO. However, with the innovation of technology, the market demands a wider input range and a wider load resistance/capacitance range for the LDO, and therefore compensation of the LDO is greatly challenged.

In the prior art, a plurality of dynamic zero point compensation circuits are arranged along with the load resistor, so that the zero point position of the compensation circuit can be changed according to the change of the load resistor, and the stability of the LDO loop is improved. However, this compensation circuit has the disadvantage that the stability of the loop changes when the load capacitance changes, and the circuit may even become unstable, especially for circuits with a wide load capacitance range.

Disclosure of Invention

The invention provides a self-adaptive dynamic zero compensation circuit applied to an LDO (low dropout regulator), aiming at the problem that the traditional dynamic zero compensation circuit cannot follow the change of load capacitance. The design idea is that a compensation zero related to an output pole is formed at a feedback point through two active current paths, wherein the two currents are respectively an output current and an output sampling current. Since the output current passes through the load impedance when being superimposed with the output sampling current, the current path related to the output current contains information about the load impedance, and the two current branches are superimposed to form a compensation zero related to the output pole. The compensation zero point not only contains the information of the output resistor, but also contains the information of the output capacitor, so when the output capacitor changes, the compensation zero point can change along with the output pole at the same time, and the stability of a loop is ensured. Meanwhile, in order to avoid the problem that the response speed is reduced due to overcompensation of the circuit under the heavy load condition, the invention also provides a load judgment circuit for adjusting the size of the compensation capacitor access under the light load and heavy load conditions.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a self-adaptive dynamic zero compensation circuit applied to LDO (low dropout regulator) comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first power sampling tube, a second power sampling tube, a power tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, an amplifier and a logic judgment circuit;

the source electrode of the first PMOS tube is connected with input voltage, and the grid electrode of the first PMOS tube is interconnected with the drain electrode of the first PMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first NMOS tube is connected with the output end of the amplifier, and the source electrode of the first NMOS tube is grounded; the non-inverting input end of the amplifier is connected with a reference voltage VREF, and the inverting input end of the amplifier is connected with a connection point of the first resistor and the second resistor; the source electrode of the power tube is connected with input voltage, the grid electrode of the power tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the power tube is grounded after passing through the first resistor and the second resistor in sequence, and the connection point of the power tube and the first resistor is an output end;

the source electrode of the first power sampling tube is connected with input voltage, and the grid electrode of the first power sampling tube is connected with the drain electrode of the first PMOS tube; the source electrode of the second PMOS tube is connected with the drain electrode of the first power sampling tube, and the grid electrode of the second PMOS tube is connected with the drain electrode of the fifth PMOS tube; the source electrode of the third PMOS tube is connected with the drain electrode of the first power sampling tube, the grid electrode of the third PMOS tube is interconnected with the drain electrode, and the drain electrode of the third PMOS tube is connected with the output end; the source electrode of the fourth PMOS tube is connected with the drain electrode of the first power sampling tube, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the output end after passing through the third resistor; the connection point of the source electrode of the second PMOS tube and the source electrode of the third PMOS tube is connected with the output end through a fourth resistor;

the source electrode of the fifth PMOS tube is connected with the drain electrode of the first power sampling tube, and the grid electrode of the fifth PMOS tube is interconnected with the drain electrode; the drain electrode of the second power sampling tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the second power sampling tube is connected with the first bias signal, and the source electrode of the second power sampling tube is grounded; the drain electrode of the second NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the second NMOS tube is connected with a second bias signal, and the source electrode of the second NMOS tube is grounded; the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the third NMOS tube is connected with a second bias signal, and the source electrode of the third NMOS tube is grounded;

the input end of the logic judgment circuit is connected with the drain electrode of the second PMOS tube, the output end of the logic judgment circuit is connected with the grid electrode of the fourth NMOS tube, and the logic judgment circuit is used for switching off the fourth NMOS tube when the current on the second PMOS tube is larger than the current on the third NMOS tube, or switching on the fourth NMOS tube when the current on the second PMOS tube is smaller than the current on the third NMOS tube; the source electrode of the fourth NMOS tube is connected with the connection point of the first resistor and the second resistor, the source electrode of the fourth NMOS tube is further connected with the drain electrode of the first power sampling tube through the first capacitor, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the first power sampling tube through the second capacitor.

The invention has the beneficial effects that: the problem that the PMOS LDO is difficult to stabilize in the conditions of wide load resistance range and wide load capacitance range is solved. The circuit can adaptively adjust the position of the compensation zero point according to the sizes of the load resistor and the load capacitor, and avoids the problem that the circuit outputs oscillation under the conditions of large load resistor and large load capacitor. When the stability of the loop is ensured, the size of the compensation capacitor is determined by using the load judgment circuit, and the response speed of the circuit under the heavy load condition is improved.

Drawings

FIG. 1 is a block diagram of an adaptive dynamic zero compensation circuit applied to LDO according to the present invention;

FIG. 2 is a specific circuit implementation diagram of an adaptive dynamic zero compensation circuit applied to an LDO according to an embodiment of the present invention;

FIG. 3 is a small signal flow diagram of an adaptive dynamic zero compensation circuit;

FIG. 4 is a small signal flow diagram of a dynamic zero compensation circuit at low frequencies;

fig. 5 is a small signal flow diagram of the dynamic zero compensation circuit at high frequencies.

Detailed Description

The technical scheme of the invention is described in detail below with reference to the accompanying drawings:

as shown in fig. 1, the present invention provides an adaptive dynamic zero compensation circuit applied to LDO, and the power transistor is a PMOS power transistor. As shown in fig. 1, the Amplifier includes an Error Amplifier (Error Amplifier), a sampling Circuit (Sense Circuit), a PMOS power transistor, and a Voltage Divider network (Voltage Divider network).

The error amplifier is a traditional five-tube operational amplifier; the sampling circuit is used for sampling the current of the power tube, and simultaneously, the sampling current and the output current are superposed to form a dynamic zero which can change along with the output pole; the power tube is a PMOS power tube and is used for providing current for a load, and meanwhile, the PMOD power tube has small dropout voltage and small conduction loss when the load is large; and the resistance voltage division network is used for dividing the output voltage of the low dropout linear regulator to obtain a feedback voltage.

The error amplifier is divided into two stages and comprises an operational amplifier, a first NMOS transistor NM1 and a first PMOS transistor PM 1. The first stage is a common five-tube operational amplifier, and the inverting input terminal of the amplifier is connected to a first feedback resistor R₁And a second feedback resistor R₂The upper end of (a); the non-inverting input terminal of the amplifier is connected with a reference voltage V_REF. The second stage is composed of a zeroth NMOS transistor NM1 and a zeroth PMOS transistor MP1, and the gate end of the zeroth NMOS transistor MN1 is connected to the output end of the error amplifier; the source end of the transformer is connected to the ground; the drain end of the PMOS transistor is connected to the gate end and the drain end of a zeroth PMOS transistor; the source end of the zeroth PMOS pipe PM1 is connected to the input voltage IN; the gate and drain terminals are connected to the gate terminal of the first sample tube MS 1.

As shown in fig. 2, the sampling circuit includes a first sampling tube MS1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first capacitor C1, a second capacitor C2, a third resistor R3, a fourth resistor R4, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a second sampling tube MS2, and a load determination LOGIC circuit LOGIC. The gate end of the first sampling tube MS1 is connected to the gate end of the first PMOS tube PM1 and the power tube M_PowerA gate terminal of (1); the source end of the power supply is connected to an input voltage IN; the drain terminal of the PMOS transistor is connected to the source terminals of the second, third, fourth and fifth PMOS transistors MP2-MP5, the upper ends of the first and second capacitors C1-C2 and the upper end of the fourth resistor R4. The gate terminal of the second PMOS transistor MP2 is connected to the gate terminal of the fourth PMOS transistor MP4The grid end and the drain end of the five PMOS tube MP 5; the drain terminal of the load logic judgment circuit is connected with the drain terminal of the third NMOS transistor MN3 and the input terminal of the load logic judgment circuit. The grid end and the drain end of the third PMOS tube are in short circuit connection and are connected to the lower ends of the third resistor R3-R4. The drain terminal of the fourth PMOS transistor MP4 is connected to the upper terminal of the third resistor R3. The drain terminal and the gate terminal of the fifth PMOS transistor MP5 are shorted together, and are connected to the drain terminal of the second sampling transistor MS2 and the drain terminal of the second NMOS transistor MN 2. The gate terminal of the second NMOS transistor MN2 is connected to a bias signal Vbias _ n 1; the source end is connected to the ground; the drain end of which is connected to the drain end of a second sample tube MS 2. The gate terminal of the third NMOS transistor MN3 is connected to the bias signal Vbias _ n2, the drain terminal thereof is connected to the drain terminal of the second PMOS transistor MP2 and the input terminal of the load logic determination circuit, and the source terminal thereof is grounded. The gate terminal of the second sampling tube MS2 is connected to the bias signal V _ sense; the source end of which is connected to ground. The lower end of the first capacitor C1 is connected to the source end of the third NMOS transistor MN 3. The lower end of the second capacitor C2 is connected to the drain terminal of the fourth NMOS transistor MN 4. The gate of the fourth NMOS transistor MN4 is connected to the output of the load logic decision circuit. The input end of the load logic judgment circuit is connected to the drain ends of the third NMOS transistor MN3 and the second PMOS transistor MP 2. The output end of the second NMOS transistor MN is connected to the gate end of the fourth NMOS transistor MN 4.

The power tube is M_PowerThe source end of the input voltage is connected to the input voltage IN; the grid end of the sampling tube MS1 is connected to the grid end of the first sampling tube MS 1; the drain terminal of which is connected to a first feedback resistor R₁The upper end of (a).

The resistor divider network comprises a first divider resistor R₁And a second voltage dividing resistor R₂. First voltage dividing resistor R₁Is connected to the power tube M_PowerThe drain terminal of (1); the lower end of which is connected to a second divider resistor R₂The upper end of (a). Second voltage dividing resistor R₂The upper end of the operational amplifier is connected to the inverting input end of the operational amplifier; the lower end of which is connected to ground.

The error amplifier is used for amplifying the difference between the feedback voltage and the reference voltage and controlling the grid voltage of the power tube through a loop, so that the current of the power tube is adjusted, and the stability of the output voltage is ensured finally. The error amplifier is divided into two stages, the first stage is a common amplifier and has the function of providing high gain; the second stage is composed of a first NMOS transistor NM1 and a first PMOS transistor MP1, and the second stage is used for converting the output of EA from low voltage to high voltage, simultaneously pushing up a parasitic pole of a grid electrode of the power tube and reducing the influence of the grid electrode of the power tube on the stability of a loop. In order to ensure that the output of the LDO has higher precision, the gain of the error amplifier needs to be larger than 60dB, and meanwhile, in order to ensure the response speed of the loop, the error amplifier needs to have larger pull-up and pull-down capabilities, and the structure of the error amplifier can be selected according to the needs.

The sampling circuit includes a first sampling tube MS1 and a sampling network. The gate-source voltage of the first sampling tube MS1 is consistent with that of the power tube Mpower, but the width-length ratio of the tubes is different, and the MS1 and the M are adjusted_PowerThe size of the sampling current is adjusted, and in the invention, the ratio of the sampling current to the current of the power tube is alpha. The sampling network has the function of generating a dynamic resistor which is in positive correlation with the load current, and simultaneously, the sampling current flows into the feedback node VFB and is superposed with the current of the power tube to form a zero point. The size of the zero point is related to the load resistance and the load capacitance, and the zero point can better follow the change of an output pole, so that the stability of a loop is ensured.

Fig. 2 shows a specific circuit implementation diagram of the sampling circuit, the power tube, the voltage-dividing resistor and the load network. The sampling circuit comprises a first sampling tube MS1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first capacitor C1, a second capacitor C2, a third resistor R3, a fourth resistor R4, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a second sampling tube MS2 and a load judgment LOGIC circuit LOGIC. The power tube is M_PowerThe voltage dividing resistor comprises a first voltage dividing resistor R₁And a second voltage dividing resistor R₂The load network comprises a load resistor R_LAnd a load capacitor C_L. The dynamic zero point generating circuit is formed by partial circuits of the sampling circuit, the power tube, the divider resistor and the load network. The fifth PMOS transistor MP5 and the second sampling transistor MS2 form a dynamic bias circuit, which provides a dynamic bias for the dynamic zero generating circuit. The second NMOS transistor MN2 provides static bias for the circuit to prevent the MP4 transistor from entering the saturation region during light load; to facilitate understanding of the circuit, a third circuit will be usedA resistor R3, a fourth resistor R4, a third PMOS tube MP3 and a fourth PMOS tube MP4 form a resistor network which is equivalent to a dynamic third resistor R5, and R5 is analyzed later; meanwhile, the first capacitor C1 and the second capacitor C2 are equivalent to a third capacitor C3; ignoring the effect of the load logic decision circuit, the small signal equivalent diagram of the circuit of fig. 2 can be represented in the form shown in fig. 3.

There are a total of four paths from the power tube current to the feedback node FB in the circuit shown in fig. 3. The Path of the first Path1 is a sampling current alpha I_OUTFlows directly into the feedback node FB through C3; the Path of the second Path2 is a sampling current alpha I_OUTThrough R5 and then through R₁Flows to the FB; the third Path3 has a Path I_OUTThrough a load network R_LAnd C_LThen flows to the node FB through R5 and C3; the fourth Path Path4 has a Path I_OUTThrough a load network R_LAnd C_LThen passing through R₁Flows to node FB.

At low frequencies, the sample current flows substantially all the way from R5, while C3 has substantially no ac current, so the sample current and the output current flow substantially all the way to the load network at low frequencies. Meanwhile, since the sampling current is negligible relative to the output current, the first Path1 and the second Path2 are negligible under the low-frequency condition, and fig. 3 can be simplified into the form shown in fig. 4. Output current I_OUTFlowing to FB via Path3 and Path4, these two paths may form a zero point Z₁. The output voltage at low frequency small signal can be expressed as

The current flowing through Path3 is

The current flowing through Path4 is

Therefore, the zero point formed by the superposition of the two currents is

As the frequency increases, the impedance of the load network decreases and the sample current begins to move toward C₃And (4) medium flow. When the frequency is much greater than Z₁At zero frequency, the sampling current can be considered as being all from C₃I.e., the current of Path2 is 0. Meanwhile, the small-signal amount of the output voltage starts to decrease due to the decrease of the load impedance, when the frequency is high enough, the currents in the paths 3 and 4 can be considered to be equivalent to the magnitude of the sampling current, and the small-signal current Path shown in fig. 3 can be equivalent to the form shown in fig. 5, C₃The ac impedance of (a) is negligible relative to R5. The current at this time is Path3

The current on Path4 is constant, and the current on Path1 is alphaI_OUTThree current paths are superposed to form a zero point Z₂。

Thus Z₂Is composed of

During heavy loading, if Z₂Is less than the first term, so Z₂The output pole can be perfectly followed to achieve the ideal compensation mode, and the MP2 has the function of ensuring that the R5 is not too small under heavy load. But at light load, Z₂Is relatively small, so that Z is determined primarily by the second term at light loads₂The position of (a). To ensure Z₂Still able to follow the output pole changes, it is necessary to make R5 follow the load changes, and the dynamic bias circuit of fig. 3 and MP3 and R1 perform this function. Since R5 is hardly larger than R1, Z₁Is relatively fixed. To ensure Z₂Is much smaller than Z₁It is necessary to limit the size of R5, and to ensure that R5 cannot be too large, R4 in fig. 3 achieves this function. The dynamic resistor composed of R1 and MP3 not only avoids the problem of too large R5, but also ensures that R5 can follow R_LAnd (4) changing.

Z is due to the high frequency of the output pole during heavy loading₁The low frequency is not needed, at this time, the load logic judgment circuit can reduce the C3 and push the Z1 to the high frequency, at this time, the stability of the loop is still good, and the small signal response speed of the loop is also accelerated as the compensation zero point is pushed to the high frequency. The MP2 and MN3 form a load judgment circuit. When the circuit is overloaded, the current on MP2 is greater than the current on MN3, so LAE _3 is high, LAE _2 is changed to low by the load logic judgment circuit, and C2 is no longer connected to the circuit. When the load is light, the current on the MP2 is less than the current on the MN3, LAE _3 is low, LAE _2 is high, and C2 is switched into the circuit.

In summary, the invention provides an adaptive dynamic zero compensation circuit applied to an LDO, which ensures the stability of the LDO in a wide load resistance range and a wide load capacitance range. Meanwhile, in order to improve the response speed of the LDO, a load logic judgment circuit is added, so that the response speed of the LDO under heavy load is ensured.

Claims

1. A self-adaptive dynamic zero compensation circuit applied to an LDO (low dropout regulator) is characterized by comprising a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first power sampling tube, a second power sampling tube, a power tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, an amplifier and a logic judgment circuit;

the source electrode of the first PMOS tube is connected with input voltage, and the grid electrode of the first PMOS tube is interconnected with the drain electrode of the first PMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first NMOS tube is connected with the output end of the amplifier, and the source electrode of the first NMOS tube is grounded; the non-inverting input terminal of the amplifier is connected with a reference voltage V_REFThe inverting input end of the amplifier is connected with the connection point of the first resistor and the second resistor; the source electrode of the power tube is connected with input voltage, the grid electrode of the power tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the power tube is grounded after passing through the first resistor and the second resistor in sequence, and the connection point of the power tube and the first resistor is an output end;