CN114253331B - Transient enhanced digital LDO circuit - Google Patents
Transient enhanced digital LDO circuit Download PDFInfo
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- CN114253331B CN114253331B CN202111476172.2A CN202111476172A CN114253331B CN 114253331 B CN114253331 B CN 114253331B CN 202111476172 A CN202111476172 A CN 202111476172A CN 114253331 B CN114253331 B CN 114253331B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention discloses a transient enhanced digital LDO circuit which comprises a comparator array, a logic controller, a power output stage and a compensation circuit, wherein the comparator array comprises a first comparator, a second comparator and a third comparator which are connected in parallel; the invention adopts a sectional dichotomy as a core control scheme of the circuit to reduce the number of transient adjustment steps and shorten the transient response time; meanwhile, an active analog feedback mode is adopted, so that the rapid compensation of the load current is realized, the secondary dive of the output voltage is avoided, and the dive amplitude of the output voltage is reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuit power management, in particular to a transient enhanced digital LDO circuit.
Background
The power management Chip is an indispensable part of a System-on-Chip (SoC) and mainly functions to provide differentiated direct-current steady-state voltages for different functional modules on the Chip. As the internal operating frequency of the SoC chip increases, the transient response requirement of the power module is higher and higher.
A Low Dropout Regulator (LDO) is a kind of power management chip, and is widely used in various portable electronic products. Traditional analog LDOs can achieve fast transient response and high power supply rejection ratio, but under a low-voltage working environment, the gain bandwidth performance of an analog LDO error amplifier is rapidly deteriorated, and the low-voltage design requirement cannot be met. Digital LDO, which is a research focus at present, employs a voltage quantizer to quantize a voltage error between a reference voltage and an output voltage into a proportional digital signal, and controls the turn-on number of a power switch array through the signal, thereby stabilizing the output voltage.
Transient recovery time and transient voltage are two important performance indexes of the digital LDO, and represent the response characteristic of the LDO under the condition of load sudden change. The transient recovery time depends on the power tube control method and the clock frequency. The traditional digital LDO adopts a single-step linear regulation mode, namely, only one power tube is increased or decreased at each clock frequency. In order to achieve a fast response speed, a high frequency clock signal must be used. The transient voltage depends mainly on the load capacitance and the load inrush quantity. When the load current sharply increases (decreases) in a short time, the power tube often fails to respond in time, causing an instantaneous discharge (increase) of load capacitance charge, resulting in a dive (overshoot) of the output voltage. Both the dive and the overshoot are very likely to cause false triggering of the subsequent logic circuit. Adding load capacitance is an effective way to suppress transient voltage changes, but large-capacitance load capacitance is not suitable for on-chip integration, and off-chip capacitance will cause the whole circuit area overhead. How to shorten the transient recovery time and reduce the transient voltage amplitude is a difficult point of the design of the fully integrated digital LDO.
Disclosure of Invention
The invention aims to solve the technical problem that aiming at the defects of the prior art, the invention provides a transient enhanced digital LDO circuit, which reduces the transient adjustment step number by a segmented binary control scheme and shortens the transient response time of the digital LDO circuit; meanwhile, an active analog feedback mode is adopted, so that the load current is quickly compensated, the secondary dive of the output voltage is avoided, and the dive amplitude of the output voltage is reduced.
The technical scheme adopted by the invention for solving the technical problems is as follows: a transient enhanced digital LDO circuit comprises a comparator array, a logic controller, a power output stage and a compensation circuit;
the comparator array comprises a first comparator, a second comparator and a third comparator which are connected in parallel, wherein the positive input end of the first comparator is connected with the output voltage of the LDO circuit, the negative input end of the first comparator is connected with a first reference voltage, and the clock end of the first comparator is connected with a sampling clock; the positive input end of the second comparator is connected with the output voltage, the negative input end of the second comparator is connected with a second reference voltage, and the clock end of the second comparator is connected with the sampling clock; the positive input end of the third comparator is connected with the output voltage, the negative input end of the third comparator is connected with a third reference voltage, and the clock end of the third comparator is connected with the sampling clock; the comparator array quantizes the error between the reference voltage and the output voltage into a digital signal to realize the control of the output voltage of the digital LDO circuit;
the logic controller comprises a shift register and a bisection controller, output signals of the first comparator, the second comparator and the third comparator are respectively connected to an input end of the shift register, one output end of the shift register is connected with an input end of the bisection controller, an output end of the bisection controller is connected with a signal input end of the power output stage, and the other output end of the shift register is connected with an input end of the compensation circuit; the control bit of the output control signal of the logic controller is N bits, and N is an integer greater than 1; the logic controller controls the conduction number of the PMOS switches through sectional dichotomy adjustment;
the power output stage comprises a PMOS switch array and a buffer array, the PMOS switch array consists of N PMOS switches which are connected in parallel, the buffer array consists of N buffers which are connected in parallel, and the compensation circuit comprises N NMOS switches which are connected in parallel and N compensation capacitors which are connected in parallel; the source ends of the N PMOS switches are respectively connected with the input voltage of the LDO circuit, the drain ends of the N PMOS switches are respectively connected with the output voltage, the power ends of the N buffers are respectively connected with the input voltage, the signal input end of each buffer is connected with one output signal of the binary controller, the signal output end of each buffer is connected with the gate end of one PMOS switch, the grounding signal end of each buffer is connected with the drain end of one NMOS switch, the drain end of each NMOS switch is connected with the upper polar plate of one compensation capacitor, the gate end of each NMOS switch is connected with one output signal of the shift register, the source end of each NMOS switch is grounded, the lower polar plate of each compensation capacitor is connected with the output voltage, and the output voltage is connected with a grounded load; the power output stage and the compensation circuit form an active analog feedback loop, and when the load changes, the power output stage rapidly provides load current for the active analog feedback loop so as to reduce the dive amplitude of the output voltage and regulate and stabilize the output voltage near the rated voltage;
when the digital LDO circuit works normally, only N control signals of the logic controller are in an activated state, N is an integer smaller than N, and the other control signals are in a high-level turn-off state; the threshold voltages of the first comparator, the second comparator and the third comparator are respectively marked as V H 、V M 、V L Let the output voltage of the digital LDO circuit be V OUT (ii) a When the digital LDO circuit works in a steady-state mode, V L <V OUT <V H In each clock period, the least significant bit of the n-bit control signal is added or subtracted to output a voltage V OUT The fluctuation amplitude of the voltage is the voltage amplitude generated by the PMOS switch corresponding to the lowest effective bit;
when the load suddenly changes, the output voltage V OUT Will fluctuate greatly, causing V OUT >V H Or V OUT <V L And when the digital LDO circuit enters a transient regulation mode, the first comparator or the third comparator sends a signal to the logic controller, and the logic controller starts the segmented bisection regulation: when V is OUT >V H The first comparator sends a signal of right shifting n bit control bits to the logic controller to greatly reduce the conduction number of the PMOS switches until V OUT <V H After the shift operation is finished, entering a binary execution stage; when V is OUT <V L The third comparator sends a signal of shifting control bit by n bits to the logic controller to greatly increase the conduction number of the PMOS switches until V OUT >V L After the shift operation is finished, entering a binary execution stage; in the binary execution phase, when V OUT <V M The second comparator sends a signal to the logic controller, and the conduction number of the PMOS switches is increased by a small amplitude; when V is OUT >V M The second comparator sends a signal to the logic controller to reduce the PMOS on by a small marginThe number of off passes.
The invention relates to a transient enhanced digital LDO circuit which comprises a comparator array, a logic controller, a power output stage and a compensation circuit, wherein in the working process, when the comparator array detects that the output voltage fluctuates greatly due to load jump, an active analog feedback loop formed by the power output stage and the compensation circuit directly couples the fluctuation of the output voltage to a grounding signal end of a buffer and then feeds the fluctuation back to a grid electrode of a PMOS switch, so that the grid end voltage of the PMOS switch is reduced, so as to provide instant compensation current, then the logic controller adjusts the output voltage through a segmentation bisection method, so that the output voltage is quickly recovered to be near a rated voltage, meanwhile, in order to avoid secondary dive of the output voltage, an NMOS switch is kept in a disconnected state when the output voltage is in a stable state, and the NMOS switch is not turned on step by step until the PMOS switch array starts to execute transient compensation.
Compared with the prior art, the invention has the following advantages:
(1) The invention adopts a sectional bisection method as a core control scheme of the circuit, after the load is suddenly changed, the logic controller can control the number of the PMOS switches which are switched on at present to be doubled or halved, the current load range is quickly determined, and then fine bisection adjustment is carried out, so that the invention has the advantages of less adjustment steps and short transient response time;
(2) The invention adopts the active analog feedback loop formed by the power output stage and the compensation circuit, directly couples the fluctuation of the output voltage to the grounding signal end of the buffer and then feeds the fluctuation back to the grid of the PMOS switch, thereby realizing the rapid compensation of the load current, avoiding the output voltage fluctuation caused by the secondary dive of the output voltage and reducing the dive amplitude of the output voltage.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a transient enhanced digital LDO circuit;
FIG. 2 is a schematic flow chart of a stepwise binary adjustment according to an embodiment;
FIG. 3 is a load transient response characteristic curve of the digital LDO circuit of the present embodiment;
FIG. 4 is a diagram illustrating a comparison of the dive effect of the digital LDO circuit and the LDO circuit without the compensation circuit in this embodiment.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The transient enhanced digital LDO circuit of an embodiment, as shown in fig. 1, includes a comparator array, a logic controller, a power output stage, and a compensation circuit.
The comparator array comprises a first comparator, a second comparator and a third comparator which are connected in parallel, wherein the positive input end of the first comparator and the output voltage V of the LDO circuit OUT Connected, the negative input of the first comparator and a first reference voltage V H The clock end of the first comparator is connected with the sampling clock CLK; positive input terminal of the second comparator and output voltage V OUT Connected to the negative input of the second comparator with a second reference voltage V M The clock end of the second comparator is connected with the sampling clock CLK; positive input terminal and output voltage V of third comparator OUT Connected, the negative input of the third comparator to a third reference voltage V L The clock end of the third comparator is connected with the sampling clock CLK; the comparator array will reference voltage V H 、V M 、V L And an output voltage V OUT The error of (2) is quantized into a digital signal, and the control of the output voltage of the digital LDO circuit is realized.
The logic controller includes a shift register and a binary controller, in this embodiment, the binary controller adopts the prior art, output signals of a first comparator, a second comparator and a third comparator are respectively connected to an input terminal of the shift register, one output terminal Y [11 [ 0] of the shift register is connected to an input terminal of the binary controller, an output terminal G [11 [ 0] of the binary controller is connected to a signal input terminal of the power output stage, and the other output terminal P [11 ] of the shift register is connected to an input terminal of the compensation circuit; the control bit of the output control signal of the logic controller is 12 bits; the logic controller controls the conduction number of the PMOS switches through sectional dichotomy adjustment.
The power output stage comprises a PMOS switch array and a buffer array, wherein the PMOS switch array consists of 12 PMOS switches connected in parallel, and the buffer arrayThe buffer circuit consists of 12 buffers connected in parallel, and the compensation circuit comprises 12 NMOS switches connected in parallel and 12 compensation capacitors C connected in parallel i I =0,1,2 …; the source ends of the 12 PMOS switches are respectively connected with the input voltage V of the LDO circuit IN Connected to the drain terminals of 12 PMOS switches respectively OUT Connected, the power supply terminals of the 12 buffers are respectively connected with an input voltage V IN The signal input end of each buffer is connected with an output signal of the binary controller, the signal output end of each buffer is connected with the grid end of a PMOS (P-channel metal oxide semiconductor) switch, the grounding signal end of each buffer is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) switch, and the drain end of each NMOS switch is connected with a compensation capacitor C i The grid end of each NMOS switch is connected with an output signal of the shift register, the source end of each NMOS switch is grounded, and each compensation capacitor C i Lower plate and output voltage V OUT Connected to output a voltage V OUT Connected to a load connected to ground; the power output stage and the compensation circuit form an active analog feedback loop, and when the load changes, the power output stage rapidly provides load current for the active analog feedback loop so as to reduce the dive amplitude of the output voltage and regulate and stabilize the output voltage near the rated voltage.
When the digital LDO circuit works normally, only n control signals of the logic controller are in an activated state, n is an integer smaller than 12, and the other control signals are in a high-level turn-off state; when the digital LDO circuit works in a steady-state mode, V L <V OUT <V H In each clock period, the least significant bit of the n-bit control signal is added and subtracted to output a voltage V OUT The fluctuation amplitude of (a) is the voltage amplitude generated by the PMOS switch corresponding to the least significant bit.
In the working process of the digital LDO circuit, the comparator array detects the output voltage V OUT Fluctuation with respect to reference voltage: if the output voltage V is L <V OUT <V H The output signal HML of the comparator array is 1X0, which indicates that the digital LDO is in steady-state mode, wherein X indicates that the value is in an unsteady state, i.e. either 0 or 1 is possible, and the logic controller is based on the output of the comparator arrayThe number of the conducted PMOS switches is controlled by signals, and the increase and decrease of the number of the conducted PMOS switches are realized; if the output voltage V OUT >V H Or V OUT <V L The output signal HML of the comparator array is 000 or 111, and at the moment, the sectional dichotomy triggering of the logic controller quickly changes the conduction number of the PMOS switches to realize the output voltage V OUT The stability of (2).
The logic controller controls the conduction number of the PMOS switches by adopting a sectional dichotomy method. The logic controller determines the current load range in a first phase of shift execution and then makes a fine binary adjustment in a second phase of binary execution to cause the output voltage V to be applied OUT The voltage can be quickly recovered to be near the rated voltage, and the quick transient response and the dive voltage optimization of the digital LDO circuit are realized.
Output signal G [11]With 12-bit logic, 12 groups of PMOS switch arrays are controlled, and the total number is 2 0 +2 1 +2 2 +2 3 +…+2 12-1 ≈2 12 The PMOS switches are switched in state. The specific operation flow is as follows: when the digital LDO circuit is in a steady state, the 6 control bits G [5+x: x is the number of]Performing addition and subtraction operation of the least significant bit; if V OUT >V M The least significant bit x is subtracted from 1, otherwise x is added with 1 to control the corresponding PMOS switch, other control bits are all in a high-order turn-off state, and the output voltage V is OUT At around the rated voltage.
When the load suddenly changes, the digital LDO circuit enters a transient regulation mode. At this point, in the first step, the 6 control bits will first perform a shift left or right operation. Assume the initial stage, G [8:3]These 6 control signals are in active mode; if V OUT >V H When the circuit is in overshoot state, the 6-bit control bit is shifted to the right to reduce the conduction number of PMOS switches, and G [7:2 ] is shifted to the right after operation]These 6 bits will be active; second, the output voltage V is continuously compared OUT And a first reference voltage V H Size of (V) if OUT >V H The 6-bit control bit is shifted to the right and the output voltage V is compared again OUT And a first reference voltage V H The size of (d); if move to the rightAfter that, V OUT <V H Then the shift operation ends and the binary execution phase is entered. During the first step of operation, if V OUT <V L Indicating that the circuit is in a dive state, the 6-bit control bit is shifted to the left to increase the number of PMOS switches turned on, and G [9:4 ] is shifted to the left after the shift operation]These 6 bits will be active; second, the output voltage V is continuously compared OUT And a third reference voltage V L Size of (V) if OUT <V L The 6-bit control bit is shifted to the left and the output voltage V is compared again OUT And a third reference voltage V L The size of (d); if left shift operation is performed, V OUT >V L Then the shift operation is finished and the binary execution phase is entered.
The binary execution operation of the binary execution stage can perform finer adjustment on the 6-bit signal to realize the output voltage V OUT The stability of (2). The specific process is as follows: setting the conducting number of the PMOS switches in the initial stage as K, the step factor i =0, and the number M = Y/2 of the PMOS switches adjusted in each time in the two-stage i Wherein Y =2 x +2 x+1 +2 x+2 +2 x+3 +2 x+4 +2 x+5 . Comparing the output voltage V OUT And a second reference voltage V M Size of (V) if OUT <V M Increasing the conduction number of the PMOS switches by M, otherwise, reducing the conduction number of the PMOS switches by M; a second step of performing i = i +1; third, comparing the output voltage V OUT And a second reference voltage V M Size of (2), if V OUT <V M Increasing the number of PMOS switches by M, or decreasing the number of PMOS switch tubes by M; and repeating the second step of operation until i =5, ending the binary execution operation, and enabling the circuit to enter a steady-state mode.
The flow chart of the segmented binary adjustment is shown in fig. 2.
In this embodiment, the transient response of the digital LDO is optimized to reduce the output voltage V OUT The nose-down amplitude of (c). The specific process is as follows: when the digital LDO is in a steady-state mode, all NMOS switches of the compensation circuit are in an off state, and the compensation circuit presents a high-impedance characteristic; when LDO just enters transient regulationMode, the NMOS switch continues to be kept in the off state, and the output signal V of the compensation circuit is avoided i The rising causes the reduction of the compensation current of the PMOS switch array and the output voltage V OUT Secondary dive; when the PMOS switch array starts to shift, the NMOS switch is gradually started; the opening state of the NMOS switch depends on the output signal of the shift register, if a certain output signal of the shift register changes, the NMOS switch connected with the output signal is conducted; after the LDO circuit resumes steady state mode, all NMOS switches are turned off again.
The load transient response characteristic curve of the digital LDO circuit in this embodiment is shown in fig. 3. The stable output voltage V of the digital LDO circuit OUT 0.55V, and when the load current jumps between 5mA and 20mA at 1ns edge time, the output voltage V OUT The dive voltage and the overshoot voltage are 95mV and 39mV, respectively, and the maximum recovery time is 206nS.
The comparison of the diving effect of the digital LDO circuit and the LDO circuit without the compensation circuit in this embodiment with the compensation circuit is shown in fig. 4. The dive voltage of the digital LDO circuit without the compensation circuit reaches 342mV, the output dive voltage of the whole digital LDO circuit is only 95mV after the compensation circuit is added, and the output voltage V is obviously improved OUT The dive phenomenon of (c).
Claims (1)
1. A transient enhanced digital LDO circuit is characterized by comprising a comparator array, a logic controller, a power output stage and a compensation circuit;
the comparator array comprises a first comparator, a second comparator and a third comparator which are connected in parallel, wherein a positive input end of the first comparator is connected with the output voltage of the LDO circuit, a negative input end of the first comparator is connected with a first reference voltage, and a clock end of the first comparator is connected with a sampling clock; the positive input end of the second comparator is connected with the output voltage, the negative input end of the second comparator is connected with a second reference voltage, and the clock end of the second comparator is connected with the sampling clock; the positive input end of the third comparator is connected with the output voltage, the negative input end of the third comparator is connected with a third reference voltage, and the clock end of the third comparator is connected with the sampling clock; the comparator array quantizes the error between the reference voltage and the output voltage into a digital signal, and the control of the output voltage of the digital LDO circuit is realized;
the logic controller comprises a shift register and a bisection controller, output signals of the first comparator, the second comparator and the third comparator are respectively connected to an input end of the shift register, one output end of the shift register is connected with an input end of the bisection controller, an output end of the bisection controller is connected with a signal input end of the power output stage, and the other output end of the shift register is connected with an input end of the compensation circuit; the control bit of the output control signal of the logic controller is N bits, and N is an integer greater than 1; the logic controller controls the conduction number of the PMOS switches through sectional dichotomy adjustment;
the power output stage comprises a PMOS switch array and a buffer array, the PMOS switch array consists of N PMOS switches which are connected in parallel, the buffer array consists of N buffers which are connected in parallel, and the compensation circuit comprises N NMOS switches which are connected in parallel and N compensation capacitors which are connected in parallel; the source ends of the N PMOS switches are respectively connected with the input voltage of the LDO circuit, the drain ends of the N PMOS switches are respectively connected with the output voltage, the power ends of the N buffers are respectively connected with the input voltage, the signal input end of each buffer is connected with one output signal of the binary controller, the signal output end of each buffer is connected with the gate end of one PMOS switch, the grounding signal end of each buffer is connected with the drain end of one NMOS switch, the drain end of each NMOS switch is connected with the upper polar plate of one compensation capacitor, the gate end of each NMOS switch is connected with one output signal of the shift register, the source end of each NMOS switch is grounded, the lower polar plate of each compensation capacitor is connected with the output voltage, and the output voltage is connected with a grounded load; the power output stage and the compensation circuit form an active analog feedback loop, and when the load changes, the power output stage rapidly provides load current for the active analog feedback loop so as to reduce the dive amplitude of the output voltage and regulate and stabilize the output voltage near the rated voltage;
when the digital LDO circuit works normally, only N control signals of the logic controller are in an activated state, N is an integer smaller than N, and the other control signals are in a high-level turn-off state; the threshold voltages of the first comparator, the second comparator and the third comparator are respectively marked as V H 、V M 、V L Let the output voltage of the digital LDO circuit be V OUT (ii) a When the digital LDO circuit works in a steady-state mode, V L <V OUT <V H In each clock period, the least significant bit of the n-bit control signal is added and subtracted to output a voltage V OUT The fluctuation amplitude of the voltage is the voltage amplitude generated by the PMOS switch corresponding to the lowest effective bit;
when the load suddenly changes, the output voltage V OUT Will fluctuate greatly, causing V OUT >V H Or V OUT <V L And when the digital LDO circuit enters a transient regulation mode, the first comparator or the third comparator sends a signal to the logic controller, and the logic controller starts the segmented bisection regulation: when V is OUT >V H The first comparator sends a signal of right shifting n bit control bits to the logic controller to greatly reduce the conduction number of the PMOS switches until V OUT <V H After the shift operation is finished, entering a binary execution stage; when V is OUT <V L The third comparator sends a signal of shifting control bit by n bits to the logic controller to greatly increase the conduction number of the PMOS switches until V OUT >V L After the shift operation is finished, entering a binary execution stage; in the two-phase execution stage, when V OUT <V M The second comparator sends a signal to the logic controller, and the conduction number of the PMOS switches is increased by a small amplitude; when V is OUT >V M The second comparator sends a signal to the logic controller in small amplitudeThe number of conduction of the PMOS switches is reduced.
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| CN105471230B (en) * | 2016-01-07 | 2018-05-22 | 成都芯源系统有限公司 | Switching power converter and control method thereof |
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| CN109164861A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | A kind of low pressure difference linear voltage regulator of fast transient response |
| CN110162130A (en) * | 2019-05-08 | 2019-08-23 | 宁波大学 | A kind of LDO circuit of power supply rejection ratio and transient response enhancing |
| CN112068630A (en) * | 2020-10-10 | 2020-12-11 | 华南理工大学 | Digital low dropout regulator with quick response |
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