CN115411922A - Buffer for absorbing current - Google Patents
Buffer for absorbing current Download PDFInfo
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- CN115411922A CN115411922A CN202210969145.7A CN202210969145A CN115411922A CN 115411922 A CN115411922 A CN 115411922A CN 202210969145 A CN202210969145 A CN 202210969145A CN 115411922 A CN115411922 A CN 115411922A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
- H02M1/344—Active dissipative snubbers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/322—Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock
Abstract
A buffer for sinking a sink current, comprising: the buffer is an operational amplifier connected in a negative feedback mode, and further comprises a clamping unit and an instantaneous response unit; the clamping unit is connected with the output end of the operational amplifier and is used for clamping the highest level of the output signal of the operational amplifier; the instantaneous response unit is connected with the voltage swing capacitor of the operational amplifier and used for receiving the clock signal and generating instantaneous low-level signals at the rising edge and the falling edge of the clock signal, so that the sink current generated at the clock jumping moment outside the buffer is absorbed. The invention has clear thought and accurate effect, can fully improve the slew rate of the buffer aiming at the sink current characteristic in the switch switching circuit and clamp the output voltage of the buffer, so that the buffer is not influenced by the switching of the state of the switch grid in the switch switching circuit and keeps stable and accurate output.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a buffer for absorbing a sink current.
Background
The switched capacitor voltage converter can realize dynamic change or relative stability of output voltage through switching control of the MOS switching tube, and the circuit can realize different working modes of a charge pump, a low dropout linear regulator and the like along with the adjustment of the MOS switching tube, so that the switched capacitor voltage converter is widely applied to various industries. In the present invention, such a voltage converter circuit is collectively referred to as a switching circuit.
In such a switching circuit, the on or off mode of the MOS switch tube is feedback-adjusted by the magnitude of the output voltage, so that the circuit operates in a charge pump mode or a low dropout linear regulator mode, which is a very common modulation mode. Meanwhile, in order to isolate the original error amplifier and the power transistor in the voltage converter circuit, so as to prevent the power transistor from influencing the node state of the output end of the error amplifier, and simultaneously improve the slew rate, so as to accelerate the turn-on speed of the power transistor, a buffer is usually added in the circuit in the prior art.
When the buffer is in an operating state, the level state of the output terminal of the buffer may be used as a reference signal, and input to the switching tube control unit, and the switching tube state is adjusted by Modulation of the switching tube control unit, such as a Pulse Width Modulation (PWM) unit. Due to the function of the switching tube control unit, the signal for adjusting the state of the switching tube is usually just turned over at the positions of the rising edge and the falling edge of the clock, so the switching tube also switches the state at the rising edge and the falling edge of the clock, and changes from on to off or from off to on.
In this case, due to the state switching of the switching tubes, the output end of the buffer receives larger injection currents generated by the gates of different switching tubes at the rising edge and the falling edge of the clock in turn, so that the performance of the buffer connected in a negative feedback mode is affected, and therefore the output end signal of the buffer is not accurate any more.
Further, in order to realize the fast recovery of the sinking current, in the circuit design, an operational amplifier with a relatively high slew rate needs to be selected as a buffer, which also increases the cost of the switch switching circuit to a certain extent.
In view of the above problems, the present invention provides a buffer for absorbing a sink current.
Disclosure of Invention
In order to solve the defects in the prior art, an object of the present invention is to provide a buffer for absorbing a sink current, in which a clamping unit and a transient response unit are added to the buffer, so that the buffer does not excessively increase an output level under the action of the sink current, and simultaneously absorbs and discharges a surplus transient sink current in time in a transient response manner.
The invention adopts the following technical scheme.
The invention relates to a buffer for absorbing a sink current, which is an operational amplifier connected in a negative feedback mode and further comprises a clamping unit and an instantaneous response unit; the clamping unit is connected with the output end of the operational amplifier and is used for clamping the highest level of an output signal of the operational amplifier; and the instantaneous response unit is connected with the voltage swing capacitor of the operational amplifier and used for receiving the clock signal and generating instantaneous low-level signals at the rising edge and the falling edge of the clock signal so as to absorb the sink current generated at the clock transition moment outside the buffer.
Preferably, the buffer is applied in a switch switching circuit; the non-inverting input end of the buffer receives an output signal from an error amplifier of the switch switching circuit; the negative phase input end of the buffer is connected with the output end, and the buffer signals are respectively and directly or indirectly input to the grids of a plurality of switching tubes in the switch switching circuit; the error amplifier is used for realizing comparison between the reference voltage and the output voltage division of the switch switching circuit.
Preferably, the clamping unit comprises a clamping MOS tube; the source electrode of the clamping MOS tube is connected with the output end of the buffer, the drain electrode of the clamping MOS tube is grounded, and the grid electrode of the clamping MOS tube is connected with an output signal of an error amplifier in the switch switching circuit.
Preferably, when the sum of the output voltage of the error amplifier and the threshold turn-on voltage of the clamp MOS tube is greater than the output voltage of the buffer, the clamp MOS tube is turned off; when the sum of the output voltage of the error amplifier and the threshold opening voltage of the clamping MOS tube is smaller than the output voltage of the buffer, the clamping MOS tube is conducted, and the output voltage of the buffer is clamped based on the output voltage of the error amplifier.
Preferably, the transient response unit comprises a forward logic unit, a reverse logic unit, a logic NOR gate, a current source and a control switch; the device comprises a positive logic unit, a negative logic unit, a positive logic unit and a negative logic unit, wherein the positive logic unit and the negative logic unit are connected in parallel, and simultaneously receive a clock signal and respectively output a positive logic signal and a negative logic signal; the logic NOR gate receives the positive logic signal and the negative logic signal respectively to generate an instantaneous low level signal; the grid electrode of the control switch is connected with an instantaneous low level signal, and the source electrode and the drain electrode are connected between the current source and the lower polar plate of the voltage swing capacitor, so that the injection of the reference current of the current source to the voltage swing capacitor is realized under the control of the instantaneous low level signal.
Preferably, the positive logic unit comprises a first inverter, a first PMOS transistor, a first NMOS transistor, a first resistor, a first capacitor, a second inverter, and a first nor gate; the input end of the first reverser is a clock signal, and the output end of the first reverser is respectively connected with the grids of the first PMOS tube and the first NMOS tube; the source electrode of the first PMOS tube is connected with power supply voltage, the drain electrode of the first PMOS tube is connected to the drain electrode of the first NMOS tube after passing through the first resistor, and the drain electrode of the first NMOS tube is grounded; one end of the first capacitor is connected with the drain electrode of the first PMOS tube and the input end of the second reverser, and the other end of the first capacitor is grounded; the output end of the second inverter is connected with one input end of the first NOR gate, the other input end of the first NOR gate is connected with the power supply voltage, and the output end of the second inverter is connected with the second input end of the logic NOR gate.
Preferably, the inversion logic unit comprises a third inverter, a fourth inverter, a second PMOS transistor, a second NMOS transistor, a second resistor, a second capacitor, a fifth inverter, and a second nor gate; the input end of the third phase inverter is connected with the clock signal, and the output end of the third phase inverter is connected with the input end of the fourth phase inverter; the connection modes of a fourth phase inverter, a second PMOS (P-channel metal oxide semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a second resistor, a second capacitor, a fifth phase inverter and a second NOR gate correspond to the connection modes of a first phase inverter, a first PMOS tube, a first NMOS tube, a first resistor, a first capacitor, a second phase inverter and a first NOR gate in the positive logic unit one by one; the output of the second nor gate is connected to the first input of the logical nor gate.
Preferably, when the clock signal is at a rising edge, the output of the positive logic unit is at a low level, the output of the negative logic unit is at a high level, and the logic nor gate outputs a low level; when the clock signal is at a falling edge, the output of the positive logic unit is at a high level, the output of the negative logic unit is at a low level, and the logic NOR gate outputs the low level; when the clock signal is in a high level or low level state, the outputs of the positive logic unit and the negative logic unit are both low level, and the logic NOR gate outputs high level.
Preferably, when the output of the logic nor gate is at a high level, the control switch is turned off; when the output of the logic NOR gate is at a low level, the control switch is switched on, and the reference current of the current source is injected into the lower pole plate of the voltage swing capacitor, so that the voltage difference between the upper pole plate and the lower pole plate of the voltage swing capacitor during the level switching of the clock signal is reduced.
Preferably, when the clock signal is at a rising edge or a falling edge, the output end of the buffer receives the sink current of the switch switching circuit under the influence of the switch switching in the switch switching circuit; meanwhile, the transient response unit controls the grid voltage of the output pipe Mn1 of the buffer to rise so as to effectively absorb the sink current.
Compared with the prior art, the buffer for absorbing the filling current has the advantages that the clamping unit and the transient response unit are additionally arranged on the buffer, so that the output level of the buffer cannot be excessively increased under the action of the filling current, and redundant transient filling current is absorbed and discharged in time in a transient response mode, so that the stability of the output signal of the buffer, the absorption of the filling current and the increase of the slew rate of the buffer are realized at the same time. The invention has clear thought and accurate effect, can fully improve the slew rate of the buffer aiming at the current sinking characteristic in the switch switching circuit and clamp the output voltage of the buffer, so that the buffer is not influenced by the state switching of the switch grid in the switch switching circuit and keeps stable and accurate output.
The beneficial effects of the invention also include:
1. in the method, the highest output level of the buffer is controlled by adding the clamping tube, and the grid electrode of the clamping tube is also regulated by the output signal of the error amplifier, so that the clamping tube and the original structure of the buffer respond to the output feedback of the circuit at the same time, and the output voltage of the buffer is limited when the sink current is larger, so as to further prevent the logic error of the feedback signal.
2. According to the invention, by adding the transient response unit consisting of the logic gate and the RC circuit, accurate time delay and absorption of the sink current can be realized by simply adjusting parameters of related elements. The value of the element parameter can be conveniently adjusted according to the current filling characteristic of the switch tube, and the switch tube has good adaptability.
Drawings
FIG. 1 is a schematic diagram of a switch switching circuit in the prior art;
FIG. 2 is a schematic circuit diagram of a buffer applied to a switch switching circuit in the prior art;
FIG. 3 is a schematic circuit diagram of a buffer for sinking a sink current according to the present invention;
FIG. 4 is a timing diagram of the output signals of the transient response unit of a buffer for sinking sink current according to the present invention;
FIG. 5 is a timing diagram comparing the sinking current sinking capabilities of a buffer of the present invention with a prior art buffer.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only used to illustrate the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.
Fig. 1 is a schematic structural diagram of a switch switching circuit in the prior art. As shown in fig. 1, a switch switching circuit in the prior art is composed of a plurality of switching tubes capable of rapidly adjusting and cyclically switching the switch state. In fig. 1, the four switching tubes are Mp1 and Mp2, respectively, and two other switching tubes Mp3 and Mp4 are located below Mp1 and Mp 2. The four switching tubes are connected through nonlinear alternating current elements such as capacitors and inductors. In fig. 1, the sources of Mp1 and Mp2 are connected to the input voltage Vin, and the source of Mp4 is the output terminal of the output voltage Vout. Through the action of the nonlinear capacitance element and the cyclic switching-off and switching-on of the switching tube, the output voltage can be distinguished from the level of the input voltage Vin in a voltage boosting or voltage reducing mode, and the output is still realized in another stable level state.
In the circuit, a clock signal is input into an associated logic control unit, which is called a switching tube control unit in the invention, the output signal of the unit can be switched between high and low levels, and the adjustment of the output voltage of the switching circuit is realized by controlling the grid levels of a plurality of switching tubes.
It should be noted that, in order to keep the output voltage relatively stable, in the prior art, the output voltage is usually divided, and after comparing with the reference voltage Vref, the error amplifier is used to output the EAOUT signal. The EAOUT signal can directly or indirectly affect the signal of the switching tube control unit, for example, adjust the duty ratio of the signal, and realize feedback adjustment of the state of the switching tube.
In order to effectively isolate the feedback circuit from the switch tube and the switch tube control unit and to make a reasonable time difference between the time of the feedback signal and the time of the control signal, the access of a buffer is generally increased on the EAOUT signal output port. Fig. 2 is a schematic circuit diagram of a buffer applied to a switch switching circuit in the prior art. As shown in fig. 2, the structure of the buffer is similar to that of a general class AB op-amp in the prior art.
However, although the buffer isolates the switching tube from directly affecting the EAOUT signal, the output signal of the buffer is still affected by the gate of the switching tube. Frequent switching of the switching tube requires an extremely high slew rate of the snubber circuit, which imposes severe requirements on the selection of snubber elements. In addition, even if the operational amplifier with high slew rate is used as the buffer in the present application, a certain time is required to eliminate the influence of the sink current and to return to the normal level. And the switching tube frequently switches the state, so that the current is more frequently generated, and the operational amplifier with the high-voltage slew rate still has difficulty in ensuring that the output voltage of the buffer cannot deviate under the condition of long-time operation.
Therefore, the structure of the buffer is improved in the invention, so that the buffer can realize effective absorption of the sink current.
The invention relates to a buffer for absorbing a sink current, which is an operational amplifier connected in a negative feedback mode and further comprises a clamping unit and an instantaneous response unit; the clamping unit is connected with the output end of the operational amplifier and is used for clamping the highest level of an output signal of the operational amplifier; and the instantaneous response unit is connected with the voltage swing capacitor of the operational amplifier and is used for receiving the clock signal and generating instantaneous low-level signals at the rising edge and the falling edge of the clock signal so as to absorb the sink current generated outside the buffer at the clock transition moment.
It can be understood that the clamping unit in the present invention is connected to the output terminal of the operational amplifier for controlling the voltage at the output terminal of the operational amplifier, and if the voltage at the output terminal of the operational amplifier does not rise to the clamping voltage, the clamping unit will not affect the output of the operational amplifier, and if the voltage at the output terminal of the operational amplifier rises to a value higher than the clamping voltage, the clamping unit will modify the voltage to the clamping voltage.
On the other hand, the instantaneous response unit in the invention performs output adjustment according to the state of the clock signal, and when the clock signal is continuously in a high level or low level state, the instantaneous response unit continuously outputs a high level. The transient response unit switches to a low level when the clock signal is in a transition state, such as in a rising or falling edge phase. The high and low levels output by the transient response unit act on the inside of the buffer operational amplifier, so that the sink current inside the buffer operational amplifier changes instantaneously. Specifically, when the transient response is low, the sink current inside the buffer will rapidly increase by a reference current, so that the sink current outside the buffer is fully absorbed and drained through the grounding element.
Preferably, the buffer is applied to the switch switching circuit; the non-inverting input end of the buffer receives an output signal from an error amplifier of the switch switching circuit; the negative phase input end of the buffer is connected with the output end, and the buffer signals are respectively and directly or indirectly input to the grids of a plurality of switching tubes in the switch switching circuit; the error amplifier is used for realizing comparison between the reference voltage and the output voltage division of the switch switching circuit.
In the invention, the position of the buffer in the whole switch switching circuit or the whole chip is specifically defined, and the buffer is connected by an operational amplifier in a negative feedback mode, so that the buffer is actually used as a voltage follower of an EAOUT signal and is changed along with the change of the EAOUT signal. Therefore, the improved buffer of the present invention realizes the control of the output end signal and the absorption of the sink current with determined characteristics at the position of the chip.
FIG. 3 is a schematic circuit diagram of a buffer for sinking a sink current according to the present invention. As shown in fig. 3, preferably, the clamping unit comprises a clamping MOS transistor; the source electrode of the clamping MOS tube is connected with the output end of the buffer, the drain electrode of the clamping MOS tube is grounded, and the grid electrode of the clamping MOS tube is connected with an output signal of an error amplifier in the switch switching circuit.
It will be readily appreciated that the invention can be implemented with a clamp MOS transistor having reasonable parameters, on the gate of which the EAOUT signal is also used to control the state of the transistor.
Preferably, when the sum of the output voltage of the error amplifier and the threshold opening voltage of the clamping MOS tube is greater than the output voltage of the buffer, the clamping MOS tube is switched off; when the sum of the output voltage of the error amplifier and the threshold opening voltage of the clamping MOS tube is smaller than the output voltage of the buffer, the clamping MOS tube is conducted, and the output voltage of the buffer is clamped based on the output voltage of the error amplifier.
It will be appreciated that the output signal of the buffer, i.e., bufout in fig. 1, should remain approximately equal to EAOUT, as controlled by the EAOUT signal. However, if a large instantaneous current is generated on one side of the switching tube, so that bufout is increased instantaneously, bufout may be larger than EAOUT.
Specifically, through the design of the clamping unit, if EAOUT and bufout are consistent, the Mp2 transistor is turned off, which means that the circuit is not affected by the one element. Once bufout is raised to a higher state due to a large current in the circuit, the sum of EAOUT and the threshold-on voltage Vth of Mp2 may be checked, and Mp2 is turned on, so that the voltage of bufout is smoothly lowered.
At this time, mp2 also serves as a part of the sinking current sinking element, so that it can just lower bufout when the sinking current is generated, and when the sinking current is not large enough, the original logic of the circuit is maintained.
Preferably, the transient response unit comprises a forward logic unit, a reverse logic unit, a logic NOR gate, a current source and a control switch; the positive logic unit and the reverse logic unit are connected in parallel, receive a clock signal and output a positive logic signal and a negative logic signal respectively; the logic NOR gate receives the positive logic signal and the negative logic signal respectively to generate an instantaneous low level signal; the grid of the control switch is connected with an instantaneous low level signal, and the source and the drain are connected between the current source and the lower electrode plate of the voltage swing capacitor, so that the injection of the reference current of the current source to the voltage swing capacitor is realized under the control of the instantaneous low level signal.
It can be understood that the transient response unit in the present invention may be substantially a compensation unit for sinking current inside the operational amplifier. The characteristic of the external current filling compensation unit is provided according to the application scene of the buffer, the compensation unit only follows the states of the rising edge and the falling edge of the clock to realize the instantaneous compensation of the internal current filling, and therefore the external current filling of the operational amplifier is effectively balanced.
The invention comprises a positive logic unit and a negative logic unit, therefore, the rising edge and the falling edge of the clock can be respectively obtained, and the compensation current is only input at two moments of the rising edge and the falling edge according to the subsequent logic gate structure, the control switch and the current source.
Preferably, the positive logic unit comprises a first inverter, a first PMOS transistor, a first NMOS transistor, a first resistor, a first capacitor, a second inverter, and a first nor gate; the input end of the first reverser is a clock signal, and the output end of the first reverser is respectively connected with the grids of the first PMOS tube and the first NMOS tube; the source electrode of the first PMOS tube is connected with power supply voltage, the drain electrode of the first PMOS tube is connected to the drain electrode of the first NMOS tube after passing through the first resistor, and the drain electrode of the first NMOS tube is grounded; one end of the first capacitor is connected with the drain electrode of the first PMOS tube and the input end of the second reverser, and the other end of the first capacitor is grounded; the output end of the second inverter is connected with one input end of the first NOR gate, the other input end of the first NOR gate is connected with the power supply voltage, and the output end of the second inverter is connected with the second input end of the logic NOR gate.
It can be understood that in the forward logic unit of the present invention, after receiving the falling edge signal of the clock, the output terminal of the first inverter is switched from low to high, and since the RC circuit is maintained at a higher voltage in the last period, the output of the second inverter is low and the output of the first nor gate is low at the last time. And as soon as the clock signal CLK switches from high to low, point B will briefly go high, and its rising time delay is related to the RC circuit parameters.
Specifically, after the RC circuit receives a high level signal of the first inverter at the present time, the RC circuit starts to discharge, so as to gradually reduce the voltage thereof, and the output end of the second inverter is switched from the low level to the high level after the delay, so that the output is turned low again after passing through the nor gate.
It can be seen that during the one-shot time, the delay of the RC circuit causes the circuit to generate a short low signal according to the falling edge of the clock, and before and after that, the circuit is maintained at a high level.
Preferably, the inversion logic unit comprises a third inverter, a fourth inverter, a second PMOS transistor, a second NMOS transistor, a second resistor, a second capacitor, a fifth inverter, and a second nor gate; the input end of the third phase inverter is connected with the clock signal, and the output end of the third phase inverter is connected with the input end of the fourth phase inverter; the connection modes of a fourth phase inverter, a second PMOS (P-channel metal oxide semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a second resistor, a second capacitor, a fifth phase inverter and a second NOR gate correspond to the connection modes of a first phase inverter, a first PMOS tube, a first NMOS tube, a first resistor, a first capacitor, a second phase inverter and a first NOR gate in the positive logic unit one by one; the output of the second nor gate is connected to the first input of the logic nor gate.
It is understood that the reverse logic unit functions similarly to the forward logic unit in the present invention, except that it can generate an One-shot low signal at the rising edge of the clock.
Preferably, when the clock signal is at a rising edge, the output of the positive logic unit is at a low level, the output of the negative logic unit is at a high level, and the logic nor gate outputs a low level; when the clock signal is at a falling edge, the output of the positive logic unit is at a high level, the output of the negative logic unit is at a low level, and the logic NOR gate outputs a low level; when the clock signal is in a high level or low level state, the outputs of the positive logic unit and the negative logic unit are both low level, and the logic NOR gate outputs high level.
FIG. 4 is a timing diagram of an output signal of an instantaneous response unit of a buffer for sinking current. As shown in fig. 4, due to the action of the transient response unit, the voltage states of the two points a and B will generate short-time low-voltage signals when the clock signals are switched, and the short-time low-voltage signals are synthesized into the signal state at the One-shot point.
Preferably, when the output of the logic nor gate is at a high level, the control switch is turned off; when the output of the logic NOR gate is at a low level, the control switch is switched on, and the reference current of the current source is injected into the lower polar plate of the voltage swing capacitor, so that the voltage difference between the upper polar plate and the lower polar plate of the voltage swing capacitor when the level of the clock signal is switched is reduced.
It can be understood that, in the circuit, the control switch can be implemented by referring to the MOS transistor in the prior art, when the MOS transistor is turned on, the reference current of the current source can be injected into the operational amplifier, and when the MOS transistor is turned off, the reference current cannot be injected. The reference current can be adjusted and controlled according to the level of the external sink current in the whole circuit.
After current is injected, the grid voltage of the NMOS power tube Mn1 at the output end of the operational amplifier is properly increased, so that the source-drain current of the NMOS power tube Mn1 in a linear state is increased, and the absorption of external sink current is effectively realized. In addition, when the external sink current is provided, the lower plate voltage of the lower half-part voltage division swing capacitor C will be increased. When the voltage of the upper plate of the piezoelectric oscillation capacitor C is increased along with the external current, the voltage of the lower plate of the piezoelectric oscillation capacitor C is also increased according to the injection of the internal current source, so that the voltage difference of the upper plate and the lower plate of the piezoelectric oscillation capacitor is basically not changed too much. Therefore, the slew capacitor C does not undergo abnormal charging and discharging after the output voltage changes, and further affects the slew time.
Preferably, when the clock signal is at a rising edge or a falling edge, the output end of the buffer receives the current of the switch switching circuit under the influence of the switch switching in the switch switching circuit; meanwhile, the instantaneous response unit controls the grid voltage of the output pipe Mn1 of the buffer to rise so as to effectively absorb the sink current.
It can be understood that the transient response unit in the invention is basically synchronous with the external sink current, and when the external sink current is input, the internal reference current is input to the gate of Mn1, so that the source-drain current of Mn1 is increased, and the external sink current is absorbed and rapidly discharged.
FIG. 5 is a timing diagram comparing the sinking current sinking capabilities of a buffer of the present invention with a prior art buffer. As shown in fig. 5, the third layer in the figure is the rising edge switching state of the clock signal. The clock switches from low to high for a very short time, maintaining a stable voltage after a very small oscillation. The second layer in the figure is the absorption condition of the buffer to the external current, in the prior art, the buffer absorbs the switch tube current caused by a clock rising edge after 0.00025ms from 1.19089ms to 1.19104ms of cutoff.
The first layer in the figure is the improved buffer in the invention, after the buffer receives the maximum sink current from 1.19090ms, the sink current is completely absorbed and discharged only from 1.19095ms, and the absorption speed of the external sink current is shortened to one third of the original absorption speed.
Compared with the prior art, the buffer for absorbing the sink current has the advantages that the clamping unit and the instantaneous response unit are additionally arranged on the buffer, so that the output level of the buffer cannot be excessively increased under the action of the sink current, and redundant instantaneous sink current is absorbed and discharged in time in an instantaneous response mode, so that the stability of the output signal of the buffer, the absorption of the sink current and the increase of the slew rate of the buffer are realized at the same time. The invention has clear thought and accurate effect, can fully improve the slew rate of the buffer aiming at the current sinking characteristic in the switch switching circuit and clamp the output voltage of the buffer, so that the buffer is not influenced by the state switching of the switch grid in the switch switching circuit and keeps stable and accurate output.
The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are merely preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for limiting the scope of the present invention, and on the contrary, any improvement or modification made based on the spirit of the present invention should fall within the scope of the present invention.
Claims (10)
1. A buffer for sinking a sink current, comprising:
the buffer is an operational amplifier connected in a negative feedback mode, and further comprises a clamping unit and an instantaneous response unit; wherein the content of the first and second substances,
the clamping unit is connected with the output end of the operational amplifier and is used for clamping the highest level of the output signal of the operational amplifier;
the instantaneous response unit is connected with the voltage swing capacitor of the operational amplifier and used for receiving the clock signal and generating instantaneous low-level signals at the rising edge and the falling edge of the clock signal, so that the sink current generated at the clock jumping moment outside the buffer is absorbed.
2. A current sinking buffer as claimed in claim 1, wherein:
the buffer is applied to a switch switching circuit;
the non-inverting input end of the buffer receives an output signal from an error amplifier of the switch switching circuit;
the negative phase input end of the buffer is connected with the output end, and buffer signals are respectively and directly or indirectly input to the grids of a plurality of switching tubes in the switch switching circuit;
wherein the error amplifier is used for realizing comparison between a reference voltage and the output voltage division of the switch switching circuit.
3. A current sinking buffer as claimed in claim 2, wherein:
the clamping unit comprises a clamping MOS tube;
and the source electrode of the clamping MOS tube is connected with the output end of the buffer, the drain electrode of the clamping MOS tube is grounded, and the grid electrode of the clamping MOS tube is connected with an output signal of the error amplifier in the switch switching circuit.
4. A current sinking buffer as claimed in claim 3, wherein:
when the sum of the output voltage of the error amplifier and the threshold opening voltage of the clamping MOS tube is larger than the output voltage of the buffer, the clamping MOS tube is turned off;
when the sum of the output voltage of the error amplifier and the threshold opening voltage of the clamping MOS tube is smaller than the output voltage of the buffer, the clamping MOS tube is conducted, and the output voltage of the buffer is clamped based on the output voltage of the error amplifier.
5. The current sinking buffer of claim 4, wherein:
the transient response unit comprises a forward logic unit, a reverse logic unit, a logic NOR gate, a current source and a control switch; wherein, the first and the second end of the pipe are connected with each other,
the positive logic unit and the reverse logic unit are connected in parallel, and simultaneously receive a clock signal and respectively output a positive logic signal and a negative logic signal;
the logic NOR gate receives the positive logic signal and the negative logic signal respectively to generate an instantaneous low level signal;
the grid electrode of the control switch is connected to the instantaneous low level signal, and the source electrode and the drain electrode of the control switch are connected between the current source and the lower pole plate of the voltage swing capacitor, so that the injection of the current source reference current into the voltage swing capacitor is realized under the control of the instantaneous low level signal.
6. The current sinking buffer of claim 5, wherein:
the positive logic unit comprises a first phase inverter, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a first resistor, a first capacitor, a second phase inverter and a first NOR gate;
the input end of the first reverser is a clock signal, and the output end of the first reverser is respectively connected with the grids of the first PMOS tube and the first NMOS tube;
the source electrode of the first PMOS tube is connected with a power supply voltage, the drain electrode of the first PMOS tube is connected to the drain electrode of the first NMOS tube after passing through the first resistor, and the drain electrode of the first NMOS tube is grounded;
one end of the first capacitor is connected with the drain electrode of the first PMOS tube and the input end of the second reverser, and the other end of the first capacitor is grounded;
the output end of the second inverter is connected with one input end of the first NOR gate, the other input end of the first NOR gate is connected with power supply voltage, and the output end of the second inverter is connected with the second input end of the logic NOR gate.
7. The current sinking buffer of claim 6, wherein:
the reverse logic unit comprises a third phase inverter, a fourth phase inverter, a second PMOS (P-channel metal oxide semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a second resistor, a second capacitor, a fifth phase inverter and a second NOR gate;
the input end of the third phase inverter is connected with a clock signal, and the output end of the third phase inverter is connected with the input end of the fourth phase inverter;
the connection modes of the fourth phase inverter, the second PMOS tube, the second NMOS tube, the second resistor, the second capacitor, the fifth phase inverter and the second NOR gate correspond to the connection modes of the first phase inverter, the first PMOS tube, the first NMOS tube, the first resistor, the first capacitor, the second phase inverter and the first NOR gate in the positive logic unit one by one;
the output terminal of the second nor gate is connected to the first input terminal of the logic nor gate.
8. The current sinking buffer of claim 7, wherein:
when the clock signal is at a rising edge, the output of the positive logic unit is at a low level, the output of the negative logic unit is at a high level, and the logic NOR gate outputs a low level;
when the clock signal is at a falling edge, the output of the positive logic unit is at a high level, the output of the negative logic unit is at a low level, and the logic NOR gate outputs a low level;
when the clock signal is in a high level or low level state, the outputs of the positive logic unit and the negative logic unit are both low levels, and the logic NOR gate outputs high levels.
9. A current sinking buffer as claimed in claim 8, wherein:
when the output of the logic NOR gate is at a high level, the control switch is turned off;
when the output of the logic NOR gate is at a low level, the control switch is switched on, and the reference current of the current source is injected into the lower pole plate of the swing capacitor, so that the voltage difference between the upper pole plate and the lower pole plate of the swing capacitor during the level switching of the clock signal is reduced.
10. A current sinking buffer as claimed in claim 9, wherein:
when the clock signal is at a rising edge or a falling edge, the output end of the buffer receives the current of the switch switching circuit under the influence of the switch switching in the switch switching circuit;
meanwhile, the transient response unit controls the grid voltage of the output pipe Mn1 of the buffer to rise so as to effectively absorb the sink current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210969145.7A CN115411922A (en) | 2022-08-12 | 2022-08-12 | Buffer for absorbing current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210969145.7A CN115411922A (en) | 2022-08-12 | 2022-08-12 | Buffer for absorbing current |
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|---|---|
| CN115411922A true CN115411922A (en) | 2022-11-29 |
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| CN202210969145.7A Pending CN115411922A (en) | 2022-08-12 | 2022-08-12 | Buffer for absorbing current |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117118429A (en) * | 2023-10-25 | 2023-11-24 | 苏州领慧立芯科技有限公司 | Wide-range super power rail buffer and input signal sampling method |
| CN117453605A (en) * | 2023-12-26 | 2024-01-26 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
-
2022
- 2022-08-12 CN CN202210969145.7A patent/CN115411922A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117118429A (en) * | 2023-10-25 | 2023-11-24 | 苏州领慧立芯科技有限公司 | Wide-range super power rail buffer and input signal sampling method |
| CN117118429B (en) * | 2023-10-25 | 2024-03-26 | 苏州领慧立芯科技有限公司 | Wide-range super power rail buffer and input signal sampling method |
| CN117453605A (en) * | 2023-12-26 | 2024-01-26 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
| CN117453605B (en) * | 2023-12-26 | 2024-04-12 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
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