CN114244339A

CN114244339A - Gate drive circuit and electronic device

Info

Publication number: CN114244339A
Application number: CN202210001600.4A
Authority: CN
Inventors: 王侠; 刘富梅; 李润德; 王强; 张树春
Original assignee: Silicon Content Technology Beijing Co ltd
Current assignee: Xinzhou Technology Beijing Co ltd
Priority date: 2022-01-04
Filing date: 2022-01-04
Publication date: 2022-03-25
Anticipated expiration: 2042-01-04
Also published as: CN114244339B

Abstract

The present disclosure provides a gate driving circuit and an electronic device. The gate driving circuit includes: a drive logic circuit configured to generate a first drive voltage selection signal of a second level in response to the control signal being at the first level, and to generate a second drive voltage selection signal of the second level in response to the delay on signal being at the first level, the delay on signal becoming the first level indicating that a first preset time period has elapsed after the control signal becoming the first level; and an on-voltage generation circuit configured to: generating a first turn-on voltage to make the transistor in a linear turn-on state in response to the first driving voltage selection signal being at the second level and the second driving voltage selection signal being at the first level; and generating a second turn-on voltage to make the transistor in a saturated turn-on state in response to the second driving voltage selection signal being at a second level. By applying different gate drive voltages in stages, the transistors can be reliably switched and damage to the transistors is avoided.

Description

Gate drive circuit and electronic device

Technical Field

The present disclosure relates to electronic circuits, and more particularly, to gate drive circuits.

Background

Gate driving circuits are widely used in various power devices to convert a weak control signal into a strong driving signal to drive the power devices to turn on and off. Due to the miller effect, positive and negative voltage spikes may occur in the gate voltage of the power device when the power device is turned on and off, which is particularly significant when the switching speed of the power device is high. When the positive voltage spike of the grid voltage is too large, the power device can be conducted by mistake, so that overcurrent or damage is generated; when the negative voltage spike of the gate voltage is too large, the gate oxide of the power device may be damaged by overvoltage, and the service life and reliability of the power device are affected, which is not desirable for the power device.

Disclosure of Invention

To avoid misconduction and damage of the power device caused by the miller effect, the present disclosure provides a gate driving circuit.

In an aspect of the present disclosure, a gate driving circuit is provided. The gate driving circuit is used for driving the power transistor based on the control signal, and comprises: a drive logic circuit configured to generate a first drive voltage selection signal of a second level in response to the control signal being at the first level, and to generate a second drive voltage selection signal of the second level in response to the delay on signal being at the first level, the delay on signal becoming the first level indicating that a first preset time period has elapsed after the control signal becoming the first level; and a turn-on voltage generation circuit coupled to the drive logic circuit and configured to generate a first turn-on voltage for placing the power transistor in a linear turn-on state when applied to the gate of the power transistor in response to the first drive voltage selection signal being at a second level and the second drive voltage selection signal being at a second level, and generate a second turn-on voltage for placing the power transistor in a saturated turn-on state when applied to the gate of the power transistor in response to the second drive voltage selection signal being at the second level.

In a second aspect of the present disclosure, an electronic device is provided. The electronic device comprises a gate drive circuit according to the first aspect and a power transistor driven by the gate drive circuit.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Drawings

The above and other objects, structures and features of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

fig. 1 shows a schematic diagram of a half-bridge circuit including a conventional gate drive circuit;

FIG. 2A shows a schematic waveform timing diagram of the gate voltage of the low-side transistor at the time of switching of the high-side transistor in FIG. 1;

FIGS. 2B and 2C show schematic waveform timing diagrams of source-drain voltages of the transistor of FIG. 1 at turn-on and turn-off, respectively;

fig. 3 shows a schematic block diagram of a gate drive circuit according to a first embodiment of the present disclosure;

fig. 4 shows a schematic circuit diagram of a gate drive circuit according to a first embodiment of the present disclosure;

fig. 5 shows a schematic waveform timing diagram of a turn-on delay block in a gate driving circuit according to a first embodiment of the present disclosure;

fig. 6 shows another schematic circuit diagram of a gate driver circuit according to a first embodiment of the present disclosure;

fig. 7 shows a schematic block diagram of a gate drive circuit according to a second embodiment of the present disclosure;

fig. 8 shows a schematic circuit diagram of a gate drive circuit according to a second embodiment of the present disclosure;

FIG. 9 shows a truth table for the action of the selector according to an embodiment of the present disclosure;

fig. 10 shows another schematic circuit diagram of a gate driver circuit according to a second embodiment of the present disclosure;

fig. 11 shows a schematic circuit diagram of a low dropout voltage regulator according to an embodiment of the present disclosure;

FIG. 12A shows a schematic waveform timing diagram of gate drive voltages according to an embodiment of the present disclosure;

FIG. 12B shows another schematic waveform timing diagram of gate drive voltages in accordance with an embodiment of the present disclosure; and

fig. 13A and 13B show schematic waveform timing diagrams of source-drain voltages at the time of turning on and off of a transistor, respectively, using a gate driving circuit according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure. It may be evident in some or all instances that any of the embodiments described below may be practiced without the specific design details described below. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

In the description of the embodiments of the present disclosure, the words "comprise" and variations such as "comprises" and "comprising" should be understood to be open-ended, i.e., "including but not limited to. The expression "based on" should be understood as "based at least in part on". The expression "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The expressions "first", "second", etc. may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Power devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), etc. may be applied in applications of electrical energy conversion, e.g., motors, solar energy, traditional power grids, solid state transformers, etc.

As described above, due to the miller effect, the gate voltage of a power device driven by a conventional gate driving circuit may have positive and negative voltage spikes when the power device is turned on and off, which may cause misturn-on and damage of the power device, affecting the lifetime and reliability of the power device.

For example, fig. 1 shows a schematic diagram of a half-bridge circuit including a conventional gate driving circuit, fig. 2A shows a schematic waveform timing diagram of a gate voltage of a low-side transistor at the time of switching of a high-side transistor in fig. 1, and fig. 2B and 2C show schematic waveform timing diagrams of a source-drain voltage at the time of turning on and off of the transistor in fig. 1, respectively. As shown in fig. 1, the high-side transistor N1 and the low-side transistor N2 are alternately turned on under the drive of the drivers DRV1 and DRV2, such that the high-side transistor N1 connects the voltage source HVDC to the intermediate node SW during a first conduction interval, and the low-side transistor N2 connects the intermediate node SW to the reference node during a second conduction interval. To avoid connecting the voltage source HVDC directly to the reference node, the high-side transistor N1 and the low-side transistor N2 are typically not conducting at the same time. As shown in FIG. 2A, Miller capacitance C exists between the gate and drain of the transistor_gdDuring the time that the low-side transistor N2 is off, the voltage at the intermediate node SW changes rapidly as the high-side transistor N1 changes from on to off, or from off to on. Due to the miller effect, higher transient voltages are coupled to the gate of the turned-off low-side transistor N2 through the miller capacitance, resulting in its gate voltage V_g2Positive voltage spike 2 and negative voltage spike 4 occur. When the generated positive voltage spike is too large, the half-bridge can be caused to be in through connection to generate overcurrent or damage; when the negative voltage spike is too large, the gate oxide of the low-side transistor N2 may be over-stressed and damaged. The same problem occurs with the high-side transistor N1. Further, as shown in fig. 2B and 2C, when the transistor N1 or N2 is turned on from off, or turned on to off, the source-drain voltage V of the transistor_dsIt will change rapidly and voltage overshoot (as shown by the dashed box) may occur, easily causing transistor damage.

In order to avoid the misconduction caused by the voltage spike, in a conventional gate driving circuit, a miller clamping circuit is added to the gate of a transistor, so that the gate and the source are short-circuited when the transistor is turned off, and the misconduction of the transistor during the turn-off period is avoided. However, this will increase the design complexity and size of the chip, and sufficient reliability cannot be ensured.

In an embodiment of the present disclosure, an improved gate driving circuit is provided which does not require a device to be built outside a gate series resistance or the like of a transistor, but directly controls on and off of the transistor by controlling the behavior of a driving signal itself. By applying different gate driving voltages in stages, embodiments of the present disclosure can avoid voltage overshoot of source-drain voltages when switching transistors, thereby reliably switching transistors and avoiding damage to transistors.

Fig. 3 shows a schematic block diagram of the gate driving circuit 10 according to the first embodiment of the present disclosure. The gate driving circuit 10 may include a driving logic circuit 12, an on-voltage generating circuit 13, and an on-delay block 14, and is configured to drive the power transistor 11 based on the control signal IN. IN one embodiment, the gate driving circuit 10 is configured to turn on the power transistor 11 IN response to the control signal IN becoming a first level (e.g., a high level), and to turn off the power transistor 11 IN response to the control signal IN becoming a second level (e.g., a low level).

IN one embodiment, the turn-on delay module 14 is configured to generate the delayed turn-on signal S based on the control signal IN_ON. The on-delay module 14 is configured to generate a delayed on-signal S of a first level when a first preset time period Tson elapses after the control signal IN changes to the first level_ON. The drive logic circuit 12 is coupled to the conduction delay module 14 and is configured to: generating a first driving voltage selection signal S of a second level IN response to the control signal IN being of a first level_V1(ii) a And is responsive to a delayed turn-on signalS_ONGenerating a second driving voltage selection signal S of a second level for the first level_V2. The on-voltage generation circuit 13 is coupled to the drive logic circuit 12 and is configured to: responsive to a first drive voltage selection signal S_V1Is at a second level and selects the signal S with a second driving voltage_V2For a first level, a first on-voltage V is generated_SON(ii) a And in response to a second drive voltage selection signal S_V2For the second level, a second on-voltage V is generated_IN. In one embodiment, when the first on-voltage V is applied_SONVia pin G_ONWhen applied to the gate of the power transistor 11, the power transistor 11 is in a linear on state; and when the second on-voltage V_INVia pin G_ONWhen applied to the gate of the power transistor 11, the power transistor 11 is in a saturated on state. It can be understood that the first turn-on voltage V_SONLower than the second on-voltage V_IN. In one embodiment, the gate driving circuit 10 may further include a low dropout voltage regulator 17. The low dropout voltage regulator 17 is coupled to the turn-on voltage generating circuit 13 and is configured to be based on the second turn-on voltage V_INGenerating a first turn-on voltage V_SONTo be supplied to the on voltage generating circuit 13. With the on-voltage generating circuit 13, when the control signal IN instructs to turn on the power transistor 11, the first on-voltage V may be first applied to the gate of the power transistor 11_SONThen, a second turn-on voltage V is applied to the gate of the power transistor 11 after a first preset time period Tson_IN. By providing different gate turn-on voltages in stages, the source-drain voltage V of the transistor 11 can be made to be on_dsThe change of the voltage is more moderate, the influence of the Miller effect is reduced, voltage oscillation and voltage overshoot are avoided, the transistor 11 is reliably turned on, and the misconduction and damage of the transistor 11 and other transistors in the bridge arm are avoided.

In one embodiment, the gate driving circuit 10 may further include an off-voltage generating circuit 15 and an off-delay module 16. The turn-off delay module 16 is coupled to the drive logic circuit 12 and is configured to generate a control signal IN based on which is provided to the driveDelayed turn-off signal S of logic circuit 12_OFF. IN one embodiment, the turn-off delay module 16 is configured to generate the first level of the delayed turn-off signal S when a second preset time period Toff has elapsed after the control signal IN changes to the second level_OFF. The drive logic circuit 12 is configured to: generating a third driving voltage selection signal S of a first level IN response to the control signal IN being of a second level_V3(ii) a And in response to a delayed off signal S_OFFGenerating a fourth driving voltage selection signal S of the first level_V4. The off-voltage generation circuit 15 is coupled to the drive logic circuit 12 and is configured to: responsive to a third drive voltage selection signal S_V3Is at the first level and the fourth driving voltage selects the signal S_V4At the second level, a first off voltage (for example, ground voltage GND) for being applied to the gate of the power transistor 11 is generated; and selecting signal S in response to the fourth driving voltage_V4At a first level, a second off-voltage V is generated for being applied to the gate of the power transistor 11_EE. Second off voltage V_EELower than the first off-voltage. In one embodiment, the gate driving circuit 10 may further include a negative voltage charge pump 18. The negative voltage charge pump 18 is coupled to the off-voltage generation circuit 15 and is configured to provide the conducting voltage generation circuit 13 with a second off-voltage V having a negative voltage value_EE. By the off-voltage generating circuit 15, it is possible to first apply a first off-voltage to the gate of the power transistor 11 and then apply a second off-voltage V to the gate of the power transistor 11 after a second preset time period when the control signal IN indicates to turn off the power transistor 11_EE. By providing different gate turn-off voltages in stages, the source-drain voltage V of the transistor 11 can be made to be at turn-off_dsThe change of (3) is relatively mild, voltage overshoot is avoided, so that the transistor is reliably turned off, and the misconduction and damage of the transistor 11 and other transistors in the bridge arm are avoided.

Fig. 4 shows a schematic circuit diagram of the gate driving circuit 10 according to the first embodiment of the present disclosure. In one embodiment, the drive logic circuit 12 includes a first inverter INV1 and a second inverter INV1 connected in seriesA first buffer BUF1, and generates a first driving voltage selection signal S of a second level IN response to the control signal IN being at a first level_V1. The on-voltage generating circuit 13 includes a second switch Q2. In one embodiment, the second switch Q2 is a PMOS transistor. The second switch Q2 is responsive to the first driving voltage selection signal S_V1Is turned on for the second level to lead to the pin G_ONProviding a first turn-on voltage V_SON。

The turn-on delay module 14 includes a first switch Q1, a first capacitor C1, and a first comparator CMP 1. The first switch Q1 and the first capacitor C1 are connected in parallel between ground and a current source. In one embodiment, the first switch Q1 is an NMOS transistor. The first switch Q1 is coupled to an output of the first inverter INV1, and is configured to be turned off IN response to the control signal IN being at the first level and to be turned on IN response to the control signal IN being at the second level. When the first switch Q1 is turned off, the first capacitor C1 is charged by the constant current source; and when the first switch Q1 is turned on, the first capacitor C1 is discharged through the turned-on first switch Q1. The turn-on delay voltage V is generated by charging the first capacitor C1_CSON. The first comparator CMP1 is coupled to the first capacitor C1 and is configured to respond to the turn-on delay voltage V_CSONHigher than the first reference voltage V_REF1To generate a delayed turn-on signal S of a first level_ON. The fourth inverter INV4 in the drive logic circuit 12 is responsive to the delayed turn-on signal S_ONGenerating a second drive voltage selection signal S of a second level for the first level_V2. The on-voltage generating circuit 13 includes a third switch Q3. In one embodiment, the third switch Q3 is a PMOS transistor. The third switch Q3 is responsive to the second driving voltage selection signal S_V2Is turned on for the second level to lead to the pin G_ONProviding a second turn-on voltage V_IN. The on-voltage generating circuit 13 further includes a first diode D1, an anode of the first diode D1 is coupled to the second switch Q2, and a cathode of the first diode D1 is coupled to the third switch Q3. When the third switch Q3 is turned on, the second on-state voltage V is applied_INGreater than the first on-voltage V_SONThe first diode D1 is turned off to ensure that pin G is connected_ONFrom a first on-voltage V_SONIs pulled up to a second breakover voltage V_IN。

Fig. 5 shows a schematic waveform timing diagram of the on-delay module 14 in the gate driving circuit 10 according to the first embodiment of the present disclosure. At time t1, the control signal IN changes from the first level to the second level, and the second switch Q2 is turned on to the pin G_ONProviding a first turn-on voltage V_SON(ii) a At the same time, the first switch Q1 is turned off, and the first capacitor C1 is charged. After a first preset time period Tson, at time t2, the delay voltage V is turned on_CSONHigher than the first reference voltage V_REF1Delayed turn-on signal S_ONTo the first level, the third switch Q3 is turned on to the pin G_ONProviding a second turn-on voltage V_IN. In one embodiment, the first capacitor C1 is disposed off-chip and is a tunable capacitor. The first preset time period Tson may be adjusted by adjusting the capacitance value of the external first capacitor C1, so as to adjust the conduction speed of the transistor 11.

Returning to fig. 4, the first to third inverters INV1 to INV3 are connected IN series, and generate the third driving voltage selection signal S of the first level IN response to the control signal IN being the second level_V3. The off-voltage generating circuit 15 includes a fourth switch Q4. In one embodiment, the fourth switch Q4 is an NMOS transistor. The fourth switch Q4 is responsive to the third driving voltage selection signal S_V3Is turned on for the first level to lead to the pin G_OFFA first off-voltage GND is provided.

The turn-off delay module 16 includes a sixth switch Q6, a second capacitor C2, and a second comparator CMP 2. In the off-delay module 16, a sixth switch Q6 and a second capacitor C2 are connected in parallel between ground and the current source. The sixth switch Q6 is coupled to an output of the second inverter INV2, and is configured to be turned off IN response to the control signal IN being at the second level so that the second capacitor C2 is charged, and to be turned on IN response to the control signal IN being at the first level so that the second capacitor C2 is discharged. The second comparator CMP2 is coupled to the second capacitor C2 and is configured to be based on the turn-off delay voltage V_CSOFFAnd a second reference voltage V_REF2To generate a delayed turn-off signal. After the control signal IN changes to the second level, the delay voltage V is turned off for a second preset time period Toff_CSOFFHigher than the second reference voltage V_REF2Delayed turn-off signal S_OFFBecomes generating a first level. The second buffer BUF24 in the drive logic circuit 12 is responsive to the delayed off signal S_OFFGenerating a fourth driving voltage selection signal S of the first level for the first level_V4. The off-voltage generating circuit 15 includes a fifth switch Q5. In one embodiment, the fifth switch Q5 is an NMOS transistor. The fifth switch Q5 is responsive to the fourth driving voltage selection signal S_V4Is turned on for the first level to lead to the pin G_OFFProviding a second turn-off voltage V_EE. Similar to the on-voltage generating circuit 13, the off-voltage generating circuit 15 further includes a second diode D2, an anode of the second diode D2 is coupled to the fifth switch Q5, and a cathode of the second diode D2 is coupled to the fourth switch Q4. When the fifth switch Q5 is turned on, the second off voltage V_EEBelow the first turn-off voltage GND, the second diode D2 is turned off to ensure that pin G is connected_OFFIs pulled down from the first off-voltage GND to the second off-voltage V_EE。

Similar to the on-delay module 14, the second capacitor C2 is an adjustable capacitor, and the off-speed of the transistor 11 can be adjusted by adjusting the capacitance value of the external second capacitor C2 to adjust the second preset time period Tsoff.

Fig. 6 shows another schematic circuit diagram of the gate driving circuit 10' according to the first embodiment of the present disclosure. The gate drive circuit 10' of fig. 6 is similar to the gate drive circuit 10 of fig. 4, except that: in the drive logic circuit 12', an OR gate OR1 and a NAND gate NAND1 are connected in series between the output of the first comparator CMP1 and the gate of the third switch Q3, and a first NOR gate NOR1 and a second NOR gate NOR2 are connected in series between the output of the second comparator CMP2 and the gate of the fifth switch Q5.

It will be appreciated that in addition to the drive logic circuit 12 of fig. 4 and the drive logic circuit 12' of fig. 6, the drive logic circuits are alsoOther arrangements may be adopted as long as it is possible to provide different gate drive voltages V in stages_g. By applying different gate driving voltages in stages, the gate driving circuit according to the first embodiment of the present disclosure can prevent voltage overshoot of the source-drain voltage when the transistor is turned on and off, thereby reliably switching the transistor and preventing damage of the transistor.

Fig. 7 shows a schematic block diagram of a gate driving circuit 70 according to a second embodiment of the present disclosure. The gate driving circuit 70 of fig. 7 is similar to the gate driving circuit 10 of fig. 4, except that: the gate driving circuit 70 further includes an overcurrent detection circuit 74. The over-current detection circuit 74 is coupled to the drive logic circuit 12, and is configured to detect the current flowing through the power transistor 11 based on a current detection signal I representing the current_DSGenerating an over-current signal S_ODS. When the current detection signal I_DSHigher than the reference current I_REFThe over-current detection circuit 74 generates the over-current signal S of the first level_ODS(ii) a And when the current detects the signal I_DSBelow the reference current I_REFThe over-current detection circuit 74 generates the over-current signal S of the second level_ODS. When overcurrent signal S_ODSAt a first level, the drive logic circuit 72 is configured to: generating a third driving voltage selection signal S of a first level IN response to the control signal IN being of a second level_V3(ii) a And in response to a delayed off signal S_OFFGenerating a fourth driving voltage selection signal S of the first level_V4. When overcurrent signal S_ODSAt the second level, the drive logic circuit 72 is configured to: generating a fourth driving voltage selection signal S of the first level IN response to the control signal IN being of the second level_V4. With the overcurrent detecting circuit 74, the gate drive circuit 70 can supply different gate-off voltages in time-division stages when the current flowing through the power transistor 11 is high, and directly connect the pin G when the current flowing through the power transistor 11 is high_OFFPull down to a second turn-off voltage V_EEThus, the switching speed of the transistor can be increased while ensuring reliable turning off of the transistor.

FIG. 8 illustrates a second embodiment according to the present disclosureA schematic circuit diagram of a gate drive circuit 70 of an embodiment. The gate driving circuit 70 of fig. 8 is similar to the gate driving circuit 10 of fig. 4, except that: the drive logic circuit 72 is based on the over-current signal S_ODSGenerating a fourth driving voltage selection signal S_V4To control the conduction of the fifth switch Q5.

The over-current detection circuit 74 includes a second comparator CMP2, the second comparator CMP2 being configured to respond to the current detection signal I_DSHigher than the reference current I_REFTo generate an over-current signal S of a first level_ODS. The drive logic circuit 72 includes an alternative data selector 82. The one-out-of-two data selector 82 is coupled to the gates of the over-current detection circuit 74, the turn-off delay module 16, the third inverter INV3, and the fifth switch Q5. A first input S of the one-of-two data selector 82 receives an output signal of the third inverter INV3, which is inverted with respect to the control signal IN; a third input B of the alternative data selector 82 receives the delayed turn-off signal S from the turn-off delay module 16_OFF. The output Y of the one-out-of-two data selector 82 generates the fourth drive voltage selection signal S that is supplied to the gate of the fifth switch Q5_V4。

Fig. 9 shows a truth table for the action of the alternative data selector 82. When the value of the first input S of the one-of-two data selector 82 is 0, the output Y is the output signal (input a) of the third inverter INV 3; when the value of the first input S of the alternative data selector 82 is 1, the output Y is a time-delay turn-off signal S_OFF(input B).

Fig. 10 shows another schematic circuit diagram of a gate driving circuit 70' according to a second embodiment of the present disclosure. The gate driving circuit 70 'of fig. 10 is similar to the gate driving circuit 10' of fig. 6, except that: the driving logic circuit 72' is based on the over-current signal S_ODSGenerating a fourth driving voltage selection signal S_V4To control the conduction of the fifth switch Q5. In the driving logic circuit 72', the fifth inverter INV5 receives the over-current signal S_ODSTwo inputs of the first AND gate AND1 are respectively connected to an output of the fifth inverter INV5 AND an output of the third inverter INV3, AND the sixth inverter INV6 receives the delayed off signal S_OFFThird or notTwo inputs of the gate NOR3 are connected to an output of the fifth inverter INV5 AND an output of the sixth inverter INV6, respectively, two inputs of the second or gate NOR2 are connected to an output of the first AND gate AND1 AND an output of the third or gate NOR3, respectively, AND an output of the second or gate NOR2 is connected to a gate of the fifth switch Q5.

It will be appreciated that the drive logic circuit may take other arrangements than the drive logic circuit 72 of fig. 8 and the drive logic circuit 72' of fig. 10, provided that it is possible to provide different gate turn-off voltages in stages when overcurrent is present and to turn off the transistors quickly when overcurrent is not present. By controlling the supplied gate-off voltage based on the over-current detection, the gate drive circuit according to the second embodiment of the present disclosure can improve the switching speed of the transistor while ensuring reliable turn-off of the transistor.

Fig. 11 shows a schematic circuit diagram of a low dropout voltage regulator 17 according to an embodiment of the present disclosure. In one embodiment, the divided voltage of the first resistor R1 and the second resistor R2 is used as the feedback voltage V_RSONIs supplied to the error amplifier EA. Error amplifier EA based on feedback voltage V_RSONAnd a third reference voltage V_REF3A voltage control signal is generated to control the transistor Q7. The transistor Q7 receives an input voltage (e.g., a second turn-on voltage V)_IN) And generates a first on-voltage V according to the control of the error amplifier EA_SON. In one embodiment, the first and second resistors R1 and R2 may be disposed off-chip and have adjustable resistance values. By adjusting the ratio of the resistance values of the first resistor R1 and the second resistor R2, the first on voltage V can be adjusted_SONThereby adjusting the impedance during the conduction of the transistor 11.

FIG. 12A shows a gate drive voltage V according to an embodiment of the disclosure_gSchematic waveform timing diagram of (1). IN the embodiments of fig. 3, 4 and 6, when the control signal IN becomes the first level, the gate driving voltage V_gFirst up to a first turn-on voltage V_SONAfter a first preset time period Tson, the gate driving voltage V_gIs raised to a second on-voltage V_IN. When the control signal IN changes to the second level, the gate drive voltage V_gFirstly, the voltage is reduced to a first turn-off voltage GND, and after a second preset time period Toff, a gate driving voltage V is obtained_gDown to a second turn-off voltage V_EE. In the embodiments of fig. 7, 8 and 10, when the current detection signal I_DSHigher than the reference current I_REFTime, the gate drive voltage V_gAlso having a similar waveform.

Fig. 12B illustrates another schematic waveform timing diagram of a gate drive voltage according to an embodiment of the disclosure. In the embodiments of fig. 7, 8 and 10, when the current detection signal I_DSBelow the reference current I_REFIN response to the control signal IN changing to the second level, the gate drive voltage V_gIs directly pulled down to a second turn-off voltage V_EE。

Fig. 13A and 13B show schematic waveform timing diagrams of source-drain voltages at the time of turning on and off of a transistor, respectively, using a gate driving circuit according to an embodiment of the present disclosure. As shown in fig. 13A and 13B, when the transistor 11 changes from off to on, or from on to off, the source-drain voltage V of the transistor 11_dsIs relatively gradual so as to avoid voltage overshoot and prolong the life of the transistor 11.

According to the technical scheme of the embodiment of the disclosure, different grid driving voltages are applied in stages, so that voltage overshoot of source and drain voltages can be avoided when the transistor is switched, the transistor is reliably switched, and the damage of the transistor is avoided. Compared with a conventional gate driving circuit, the embodiment of the disclosure does not need to stand devices outside a gate series resistor and the like of a transistor, but directly controls the on and off of the transistor by controlling the behavior of a driving signal, so that the voltage spike and oscillation generated during the switching of the transistor are reduced, reliable transistor switching can be ensured, the anti-interference capability of the gate driving circuit can be improved, the influence of crosstalk is reduced, higher integration level can be realized, and the board level design of an output stage is simplified. Compared with a conventional grid driving circuit with passive protection, the grid electrode of the transistor can be prevented from voltage spike and voltage oscillation in a step switch mode, and active protection of the transistor is achieved. Through the alternative embodiment of the present disclosure, the delay time of the step driving may be adjusted by adjusting the external capacitance value, thereby adjusting the switching speed of the transistor, and the first on-voltage may be adjusted by adjusting the resistance value of the external resistor, thereby adjusting the on-resistance of the transistor. These flexible parameter adjustment ways enable the gate driving circuit according to the embodiments of the present disclosure to be suitable for various application scenarios. By adjusting these parameters according to the actual application, it is possible to reliably switch the transistor with a faster switching speed and reduced loss, and to avoid damage to the transistor.

The embodiments may be further described using the following clauses:

clause 1. a gate drive circuit (10) for driving a power transistor (11) based on a control signal (IN), the gate drive circuit (10) comprising:

a drive logic circuit (12) configured to generate a first drive voltage selection signal (S) of a second level IN response to the control signal (IN) being of a first level_V1) And is responsive to the delayed turn-on signal (S)_ON) Generating a second driving voltage selection signal (S) of a second level for the first level_V2) Said delayed on signal (S)_ON) The change to the first level indicates the elapse of a first preset time period (Tson) after the control signal (IN) changes to the first level; and

an on-voltage generation circuit (13) coupled to the drive logic circuit (12) and configured to:

selecting a signal (S) in response to the first driving voltage_V1) Is at a second level and the second drive voltage selects a signal (S)_V2) For a first level, a first turn-on voltage (V) is generated_SON) The first on-voltage (V)_SON) For bringing the power transistor (11) into a linear conducting state when applied to the gate of the power transistor (11); and

selecting a signal (S) in response to the second driving voltage_V2) For a second level, a second turn-on voltage (V) is generated_IN) The second on-voltage (V)_IN) For putting the power transistor (11) in a saturated conducting state when applied to the gate of the power transistor (11).

Clause 2. the gate driving circuit (10) according to clause 1, further comprising:

a turn-on delay module (14) coupled to the drive logic circuit (12) and configured to generate the delayed turn-on signal (S) provided to the drive logic circuit (12) based on the control signal (IN)_ON)。

Clause 3. the gate drive circuit (10) of clause 2, wherein the turn-on delay module (14) comprises:

a first switch (Q1) coupled to the drive logic circuit (12) and configured to turn off IN response to the control signal (IN) being at a first level and to turn on IN response to the control signal (IN) being at a second level;

a first capacitor (C1) in parallel with the first switch (Q1) and configured to be charged in response to the first switch (Q1) being off and discharged in response to the first switch (Q1) being on to generate an on-delay voltage (V1)_CSON) (ii) a And

a first comparator (CMP1) coupled to the first capacitor (C1) and the drive logic circuit (12) and configured to be responsive to the turn-on delay voltage (V)_CSON) Higher than the first reference voltage (V)_REF1) While generating said delayed turn-on signal (S) at a first level_ON)。

Clause 4. the gate driving circuit (10) according to clause 1, wherein the turn-on voltage generating circuit (13) includes:

a second switch (Q2) coupled to the drive logic circuit (12) and configured to select a signal (S) in response to the first drive voltage_V1) Is turned on for a second level to generate the first turn-on voltage (V)_SON)；

A third switch (Q3) coupled to the drive logic circuit (12) and configured to select a signal (S) in response to the second drive voltage_V2) Is turned on for a second level to generate the second turn-on voltage (V)_IN) (ii) a And

a first diode (D1), an anode of the first diode (D1) being coupled to the second switch (Q2), and a cathode of the first diode (D1) being coupled to the third switch (Q3).

Clause 5. the gate drive circuit (10) of clause 1, wherein the drive logic circuit (12) is further configured to generate a third drive voltage selection signal (S) of the first level IN response to the control signal (IN) being of the second level_V3) And in response to a delayed off signal (S)_OFF) Generating a fourth driving voltage selection signal of the first level for the first level (S)_V4) Said delayed off signal (S)_OFF) The change to the first level indicates the elapse of a second preset time period (Tsoff) after the control signal (IN) changes to the second level; and is

Wherein the gate drive circuit (10) further comprises an off-voltage generation circuit (15), the off-voltage generation circuit (15) being coupled to the drive logic circuit (12) and configured to:

selecting a signal (S) in response to the third driving voltage_V3) Is at a first level and the fourth drive voltage selects a signal (S)_V4) Generating a first off-voltage (GND) for being applied to a gate of the power transistor (11) at a second level; and

in response to the fourth driving voltage selection signal (S)_V4) Generating a second turn-off voltage (V) for application to the gate of the power transistor (11) at a first level_EE)，

The second turn-off voltage (V)_EE) Below the first off-voltage (GND).

Clause 6. the gate driving circuit (10) according to clause 1, further comprising:

an over-current detection circuit (74) coupled to the drive logic circuit (12) and configured to detect an over-current based on a current detection signal (I) representing a current flowing through the power transistor (11)_DS) Generating an over-current signal (S)_ODS)；

Wherein the drive logic circuit (12) is further configured to:

when the over-current signal (S)_ODS) While at the first level, generating a third driving voltage selection signal (S) at the first level IN response to the control signal (IN) being at the second level_V3) And in response to a delayed off signal (S)_OFF) Generating a fourth driving voltage selection signal of the first level for the first level (S)_V4) Said delayed off signal (S)_OFF) The change to the first level indicates the elapse of a second preset time period (Tsoff) after the control signal (IN) changes to the second level, the overcurrent signal (S)_ODS) Indicating the current detection signal (I) for a first level_DS) Higher than the reference current (I)_REF) (ii) a And is

When the over-current signal (S)_ODS) IN response to the control signal (IN) being at the second level while at the second level, the fourth driving voltage selection signal (S) being at the first level is generated_V4)；

The second turn-off voltage (V)_EE) Below the first off-voltage (GND).

Clause 7. the gate driving circuit (10) according to clause 5 or 6, wherein the off-voltage generating circuit (15) includes:

a fourth switch (Q4) coupled to the drive logic circuit (12) and configured to select a signal (S) in response to the third drive voltage_V3) Is turned on for a first level to generate the first off voltage (GND);

a fifth switch (Q5) coupled to the drive logic circuit (12) and configured to select a signal (S) in response to the fourth drive voltage_V4) Is turned on for a first level to generate the second off voltage (V)_EE) (ii) a And

a second diode (D2), an anode of the second diode (D2) being coupled to the fifth switch (Q5), and a cathode of the second diode (D2) being coupled to the fourth switch (Q4).

Clause 8. the gate driving circuit (10) according to clause 5 or 6, further comprising:

a turn-off delay module (16) coupled to the drive logic circuit (12) and configured to generate the delayed turn-off signal (S) provided to the drive logic circuit (12) based on the control signal (IN)_OFF)。

Clause 9. the gate drive circuit (10) of clause 8, wherein the turn-off delay module (16) comprises:

a sixth switch (Q6) coupled to the drive logic circuit (12) and configured to turn off IN response to the control signal (IN) being at a second level and to turn on IN response to the control signal (IN) being at a first level;

a second capacitor (C2) in parallel with the sixth switch (Q6) and configured to be charged in response to the sixth switch (Q6) being off and discharged in response to the sixth switch (Q6) being on to generate an off delay voltage (V6)_CSOFF) (ii) a And

a second comparator (CMP2) coupled to the second capacitor (C2) and the drive logic circuit (12) and configured to be responsive to the turn-off delay voltage (Vdelay)_CSOFF) Higher than the second reference voltage (V)_REF2) While generating said delayed turn-off signal (S) at a first level_OFF)。

Clause 10. the gate drive circuit (10) according to clause 3, wherein the first capacitor (C1) is a tunable capacitor.

Clause 11. the gate drive circuit (10) according to clause 9, wherein the second capacitor (C2) is a tunable capacitor.

Clause 12. the gate drive circuit (10) of clause 1, further comprising a low-dropout voltage regulator (17), the low-dropout voltage regulator (17) being coupled to the turn-on voltage generation circuit (13) and configured to be based on the first turn-on voltage (V)_SON) Generating the second turn-on voltage (V)_IN)。

Clause 13, an electronic device, comprising

The gate drive circuit (10) of any of clauses 1-12; and

the power transistor (11) is driven by the gate drive circuit (10).

Further, the present disclosure provides various example embodiments, as described and as shown in the accompanying drawings. However, the present disclosure is not limited to the embodiments described and illustrated herein, but may extend to other embodiments, as known or as would be known to those skilled in the art. Reference in the specification to "one embodiment," "the embodiment," "these embodiments," or "some embodiments" means that a particular feature, structure, or characteristic described is included in at least one embodiment, and the appearances of the phrases in various places in the specification are not necessarily all referring to the same embodiment.

Finally, although various embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended drawings is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claimed subject matter.

Claims

1. A gate drive circuit (10) for driving a power transistor (11) based on a control signal (IN), the gate drive circuit (10) comprising:

2. The gate drive circuit (10) of claim 1, further comprising:

3. The gate drive circuit (10) of claim 2, wherein the turn-on delay module (14) comprises:

4. The gate drive circuit (10) of claim 1, wherein the turn-on voltage generation circuit (13) comprises:

5. The gate drive circuit (10) of claim 1, wherein the drive logic circuit (12) is further configured to generate a third drive voltage selection signal (S) of a first level IN response to the control signal (IN) being of a second level_V3) And in response to a delayed off signal (S)_OFF) Generating a fourth driving voltage selection signal of the first level for the first level (S)_V4) Said delayed off signal (S)_OFF) The change to the first level indicates the elapse of a second preset time period (Tsoff) after the control signal (IN) changes to the second level; and is

in response to the fourth driving voltage selection signal (S)_V4) Generating a second turn-off voltage (V) for application to the gate of the power transistor (11) at a first level_EE) Said second off-voltage (V)_EE) Below the first off-voltage (GND).

6. The gate drive circuit (10) of claim 1, further comprising:

Wherein the drive logic circuit (12) is further configured to:

7. The gate drive circuit (10) of claim 5 or 6, wherein the turn-off voltage generation circuit (15) comprises:

8. The gate drive circuit (10) of claim 5 or 6, further comprising:

9. The gate drive circuit (10) of claim 8, wherein the turn-off delay module (16) comprises:

10. A gate drive circuit (10) as claimed in claim 3, wherein the first capacitor (C1) is a tunable capacitor.

11. A gate drive circuit (10) as claimed in claim 9, wherein the second capacitor (C2) is a tunable capacitor.

12. The gate drive circuit (10) of claim 1, further comprising a low-dropout voltage regulator (17), the low-dropout voltage regulator (17) being coupled to the turn-on voltage generation circuit (13) and configured to be based on the first turn-on voltage (V ™)_SON) Generating the second turn-on voltage (V)_IN)。

13. An electronic device comprises

A gate drive circuit (10) according to any one of claims 1 to 12; and

the power transistor (11) is driven by the gate drive circuit (10).