CN108736863A - A kind of output driving circuit - Google Patents
A kind of output driving circuit Download PDFInfo
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- CN108736863A CN108736863A CN201710262766.0A CN201710262766A CN108736863A CN 108736863 A CN108736863 A CN 108736863A CN 201710262766 A CN201710262766 A CN 201710262766A CN 108736863 A CN108736863 A CN 108736863A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
- H03K2005/00215—Layout of the delay element using FET's where the conduction path of multiple FET's is in parallel or in series, all having the same gate control
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Present invention is primarily about the drive circuits switched for semiconductor power, design a kind of output driver circuit with pre-driver, first drive signal of pre-driver output be used to drive output stage pull up transistor and the second drive signal of pre-driver output is used to drive the pull-down transistor of output stage, the pre-driver devises delay cell, to be simultaneously turned on to avoid the complementary transistor of output stage in the complementary transistor stage of control output stage.
Description
Technical field
Present invention is primarily about the drive circuits switched for semiconductor power, more precisely, being that design is a kind of
Output driver circuit, the output driver circuit is with delay effect, in the complementary transistor stage of control output stage
It can be simultaneously turned on to avoid the complementary transistor of output stage.
Background technology
In the drive circuit switched applied to semiconductor power, to obtain maximum output power and reducing crystalline substance to the greatest extent
The power consumption of body pipe, output stage transistor would generally drive via control signal caused by pre-driver, execute complementary
Switching driving P-type transistor and N-type transistor, the damage of power caused by being simultaneously turned on to avoid P-type transistor and N-type transistor
Consumption, while also needing to avoid simultaneously turning on because of P-type transistor and N-type transistor, the P-type transistor being otherwise both turned on is brilliant with N-type
Body pipe is directly series between power supply and ground terminal, may lead to irreversible cause thermal damage.
Existing open source literature such as Chinese patent application (CN103890682) discloses one kind and is opened for semiconductor power
The drive circuit of pass, including the first analog line driver transistor and the second analog line driver transistor for being complementary to, two
The output end of analog line driver transistor is connected to the input terminal of power switch, and the input terminal of the second analog line driver transistor connects
It is connected to a half-bridge circuit, the latter includes the first pre-driver transistor and the second pre-driver transistor for being complementary to,
The output end of two pre-driver transistors is connected to the input terminal of the second analog line driver transistor, and then is pre-driver
Transistor provides fast switching time, greatly reduces the power consumption of transistor.
Existing open source literature such as Chinese patent application (CN102904423) discloses a kind of pre-driver circuitry and work(
Rate module driver, wherein pre-driver circuitry include the first N-channel EMOS enhancement metal oxide semiconductor type field-effect tube MOS
Pipe and the enhanced metal-oxide-semiconductor of the second N-channel：The enhanced metal-oxide-semiconductor of first N-channel is connected to the first pulse width of pre-driver circuitry
Between modulation (PWM) signal input part and the second input terminal of drive control module；Before the enhanced metal-oxide-semiconductor of second N-channel is connected to
Between the second pwm signal input terminal and the first input end of drive control module of stage drive circuit.When two inputs of controller
When end can all export high level, high level is converted to low level and is exported to power transistor inverter by metal-oxide-semiconductor, prevents power brilliant
The same phase upper and lower bridge arm (Bridge-Legs) of body pipe inverter receives high level signal in the same period and short circuit occurs now
As to improve the reliability and stability of motor driven systems.
None is not to use framework of a large amount of component as pre-driver circuitry, industry in existing such scheme
Tool usually intellectual all knows that large number of component can directly increase the area of domain, especially in the wafer for throwing piece
Preparatory phase needs a large amount of light shield, causes high cost.
Invention content
In one alternate embodiment, the present invention provided a kind of output driving circuit, including a pre-driver,
For driving pulling up transistor and pull-down transistor alternate conduction for output stage, so that one that the output stage is provided
Output signal switches between the first, second logic state, and the first drive signal of pre-driver output is used for
The second drive signal for pulling up transistor and exporting described in driving is for driving the pull-down transistor, the pre-driver
Including：First, second transistor, each all have a first end and a second end and a control terminal, and one defeated
Enter signal while being input to the control terminal of first, second transistor, first, second transistor is respective described
First end correspondence is connected respectively to the first, second reference voltage source and first, second transistor respective described second
Connection is there are one the delay cell controlled by the output signal between end, the delay cell for avoiding described first, the
The logic state of two driving signal generates the overturning of rising edge or failing edge simultaneously.
Above-mentioned output driving circuit, when first drive signal is turned to described second by first logic state
When logic state, the delay cell generates delay effect, second driving after making first drive signal overturn
Signal is just turned to second logic state by first logic state.
Above-mentioned output driving circuit, when second drive signal is turned to described first by second logic state
When logic state, the delay cell generates delay effect, first driving after making second drive signal overturn
Signal is just turned to first logic state by second logic state.
Above-mentioned output driving circuit, the delay cell include third, the 4th transistor, and each all has one
First end and a second end and a control terminal；The first end of the wherein described third transistor and the 4th transistor
The second end be all connected to the second end of the first transistor and the second end of the third transistor
Be all connected to the second end of the second transistor with the first end of the 4th transistor, and the third,
The control terminal of 4th transistor inputs the inversion signal of the output signal.
Above-mentioned output driving circuit, further includes first buffer, and input terminal is connected to the first transistor
Second end and its output end then provides first drive signal.
Above-mentioned output driving circuit, further includes second buffer, and input terminal is connected to the second transistor
Second end and its output end then provides second drive signal.
Above-mentioned output driving circuit, when the input signal is the first logic state (such as low level), described first
Transistor turns and the second transistor turn off so that the voltage of the second end of the first transistor is lifted and causes
First drive signal is overturn by first logic state to second logic state (such as high level)；The delay is single
Member slows down the voltage lifting speed of the second end of second crystal, after first drive signal is overturn, institute
The voltage for stating the second end of the second crystal just starts to be lifted and second drive signal is further made to start by described the
One logic state is turned to second logic state.
Above-mentioned output driving circuit, when the input signal is the second logic state (such as high level), described first
Transistor turns off and the second transistor is connected so that the voltage pull-down of the second end of the second transistor simultaneously causes
Second drive signal is overturn by second logic state to first logic state (such as low level)；The delay is single
Member slows down the voltage drop low velocity of the second end of the first crystal, after second drive signal is overturn, institute
The voltage for stating the second end of first crystal just starts to reduce and first drive signal is further made to start by described the
Two logic state is turned to first logic state.
Above-mentioned output driving circuit, further includes a phase inverter, and the input terminal of the phase inverter receives the output letter
Number and the output end of the phase inverter is connected to the third, the control terminal of the 4th transistor.
Above-mentioned output driving circuit, the conducting channel type of the third transistor and the 4th transistor on the contrary,
One CMOS complementary type channel switch, the inversion signal control of the output signal are constituted by the third, the 4th transistor
Another one is connected when making the shutdown of one of both the third, the 4th transistor.
Description of the drawings
Read it is described further below and with reference to the following drawings after, feature and advantage of the invention will be evident：
Fig. 1 is the basic framework for driving the pre-driver of output stage transistor to use delay cell.
Fig. 2 is the basic framework for driving the pre-driver of output stage transistor to use NAND NAND gates.
Fig. 3 is the basic framework for driving the pre-driver of output stage transistor to use NOR nor gates.
Fig. 4 is the basic framework for driving the pre-driver of output stage transistor to abandon using NAND, NOR logic gate.
Fig. 5 is the signal V for driving output stage transistorNGRelative signal VPGThe carryover effects of generation.
Fig. 6 is the signal V for driving output stage transistorPGRelative signal VNGThe carryover effects of generation.
Specific implementation mode
Below in conjunction with each embodiment, technical scheme of the present invention is clearly completely illustrated, but described reality
It is the present invention embodiment not all with the embodiment being described herein used in explanation to apply example only, is based on such embodiment, this field
The scheme that is obtained without making creative work of technical staff belong to protection scope of the present invention.
Understand present invention spirit in order to deeper, the use of our leading explanation figures 1 to Fig. 3 is compared with multicomponent device
May be implemented delay Conventional implementations, compare again thereafter it is provided by the invention show in Fig. 4 can be greatly reduced
A kind of delay embodiment of component number.
Referring to Fig. 1, an input signal Q is receivedINPre-driver 10 include first control there are two controlling brancher
Branch includes that there are one delay cells 1 and additional buffer etc., and postpone there are one including then in second controlling brancher
Unit 2 and additional buffer etc..Wherein first controlling brancher mainly generates a control signal VPGFor driving PMOS brilliant
Body pipe MP1, second controlling brancher then mainly generate a control signal VNGFor driving NMOS transistor MN1.Output stage
The source electrode of PMOS transistor MP1 is connected to supply voltage VDD, and the source electrode of the NMOS transistor MN1 of output stage then connects
To ground terminal GND, and between the drain electrode of transistor MP1 and the drain electrode node being connected with each other and ground terminal GND of transistor MN1
There are one capacitance C for connection, and an expected output signal Q is generated at the node that they are interconnectedOUT.Based in view of
It is required that such delay cell 1 and 2 has effects that signal generation time in transmittance process is promoted to postpone, pre-driver 10
The drive signal V for controlling high-side transistor MP1 that first controlling brancher generatesPGWhat compared with second controlling brancher generated
Drive signal V for controlling low side transistors MN1NGThe two is each other with putting off on timing node, so that crystal
Pipe MP1 and transistor MN1 will not be simultaneously turned on, avoid supply voltage VDD directly penetrate through transistor MP1 in the conduction state and
Transistor MN1 to ground terminal GND, and transistor MP1 and transistor MN1 will not be damaged by ensureing.
Referring to Fig. 2, first controlling brancher of pre-driver 11 includes a NAND NAND gates 11a and additional anti-
Second controlling brancher of phase device, buffer etc., pre-driver 11 includes a NOR nor gates 11b and additional reverse phase
Device, buffer etc., NAND gate 11a and nor gate 11b belong to digital logic gate, are required to multiple transistors to build, in view of
Their specific composition structure belongs to common knowledge for industry has usual skill, because it will not go into details.When second
The control signal V that controlling brancher namely NOR nor gates 11b are generatedNGFor logic low potential/level when, control signal VNGPass through one
The inversion signal namely logic high that a phase inverter generates be input to the NAND gate 11a in first controlling brancher one are defeated
Enter end, so the output V of NAND gate 11a at this timePGIt is likely to be to be turned to low level by high level, and this stage is because of driving
The control signal V of NMOS transistor MN1NGIt is that low level makes transistor MN1 not turn on, but drives PMOS transistor MP1
Control signal VPGLow level can be turned under such condition and connect transistor MP1, thereby come avoid occur transistor
MN1 and the situation connected while transistor MP1.Vice versa, when first controlling brancher namely NAND NAND gates 11a generate
Control signal VPGFor logic high potential/level when, control signal VPGIt the inversion signal that is generated by phase inverter namely patrols
The input terminal that low level is input to the nor gate 11b in second controlling brancher is collected, so the output of nor gate 11b at this time
VNGIt is likely to be to be turned to high level by low level, and this stage is because drive the control signal V of PMOS transistor MP1PGIt is
High level makes transistor MP1 not turn on, but drives the control signal V of NMOS transistor MN1NGIt under such condition can be with
It is turned to high level and connects transistor MN1, thus in this way, to avoid that both transistor MN1 and transistor MP1 occurs
The situation being also turned on.
Referring to Fig. 3, first controlling brancher of pre-driver 12 includes a NAND NAND gates 12a and additional anti-
Second controlling brancher of phase device, buffer etc., pre-driver 11 includes a NAND NAND gates 12b and additional reverse phase
Device etc..The control generated after the output result of second controlling brancher namely NAND NAND gates 12b are high level but reverse phase
Signal VNGFor logic low potential when, control signal VNGThe inversion signal namely high level generated by a phase inverter is input to
An input terminal of NAND NAND gates 12a in first controlling brancher, so the output V of NAND gate 11a at this timePGBe likely to be
Low level is turned to by high level, and this stage is because drive the control signal V of NMOS transistor MN1NGIt is that low level makes
Transistor MN1 is not turned on, but drives the control signal V of PMOS transistor MP1PGIt can be turned to low electricity under such condition
It puts down and connects transistor MP1, thereby the situation to avoid generation transistor MN1 be connected while transistor MP1.Otherwise also
So, as the control signal V that first controlling brancher namely NAND NAND gates 12a are generatedPGFor logic high potential when, control signal
VPGAn input terminal of the NAND gate 12b in second controlling brancher is directly inputted to, so the output knot of NAND gate 12b at this time
Fruit is likely to be to be turned to low level by high level, but what the output result of NAND gate 12b generated after inverter
Control signal VNGFor logic high potential, and this stage because driving PMOS transistor MP1 control signal VPGIt is high level to make
It obtains transistor MP1 not turning on, but drives the control signal V of NMOS transistor MN1NGIt can be turned to high level with this condition
And transistor MN1 is connected, the thereby situation to avoid transistor MN1, MP1 from being also turned on.
In above content of the discussions, because they are not the emphasis of the present invention, not individually to each first device
Part is completely illustrated, only exemplary simple introduction, wherein by multiple transistors come build topology NAND gate or
The drawbacks of complicated structure of the digital logic gates such as NOT gate, is to occupy larger chip area and brings high cost problem,
New simplicity driver topology is built in view of abandoning the driver of this high complexity as far as possible, is opened up in Fig. 4
A kind of new embodiment of the present invention is shown, that replace the digital logic gates that original mode largely uses.
Referring to Fig. 4, in the topological structure, a kind of output driving circuit (Output Driver Circuit) is provided,
It includes mainly a pre-driver (Pre-driver) 20 and output stage (Output stage) circuit.Output stage packet
The pull-down transistor MN1 of the MP1 and NMOS types that pull up transistor of PMOS types is included, the source electrode for the MP1 that pulls up transistor is connected to
One the first reference voltage source (such as supply voltage VDD) of high voltage level, and the source electrode of pull-down transistor MN1 is then connected to phase
To second reference voltage source (such as ground terminal GND) of low-voltage level, the former current potential level is more than the latter.And pull-up
The drain electrode of transistor MP1 and the drain electrode of pull-down transistor MN1 are interconnected at node N4, it is contemplated that output signal QOUTIt generates
At node N4.Pre-driver 20 is used to drive both MP1 and pull-down transistor the MN1 alternating that pulls up transistor of output stage
Conducting, specifically, pull up transistor MP1 conductings when pull-down transistor MN1 shutdown, or pull up transistor MP1 shutdowns when
Pull-down transistor MN1 is then connected, so that the output signal Q that the output stage provides at node N4OUTThe first logic state (such as
Low level) switch between the second logic state (such as high level).The output signal Q when pull-down transistor MN1 is connectedOUTElectricity
Position is close to the second reference voltage source, the output signal Q when the MP1 that pulls up transistor is connectedOUTCurrent potential close to the first reference voltage
Source.
The control signal V that pre-driver 20 exportsPG(i.e. the first drive signal) is coupled to the grid for the MP1 that pulls up transistor
Control signal V of the control terminal for driving pull up transistor MP1 and pre-driver 20 to exportNG(i.e. the second drive signal)
It is coupled to the grid control terminal of pull-down transistor MN1 for driving pull-down transistor MN1.
Referring to Fig. 4, pre-driver 20 includes the first transistor T1 and second transistor T2, the first transistor T1 and the
Two-transistor T2 respectively all has a first end and a second end and a control terminal, and the first transistor T1 is, for example, one
The field-effect transistor of PMOS types, the first transistor T1 are, for example, the field-effect transistor of a NMOS type, their
One end is, for example, source electrode, and second end is, for example, drain electrode and control terminal is, for example, grid.Wherein the second of the first transistor T1
There are one by output signal Q for connection between end and the second end of second transistor T2OUTThe delay cell 20a of control, delay cell
The meaning of 20a is to avoid the first drive signal VPG, the second drive signal VNGHigh low logic state simultaneously overturn.Tool
It says to body, the delay cell 20a that can generate delay effect makes the first drive signal VPGIt is turned to high level from low level
Rising edge redirects after action terminates, the second drive signal VNGJust start to execute the rising edge jump for being turned to high level from low level
Rotation is made, and the expected purpose generated is, only as the first drive signal VPGFor high potential when (guarantee pulls up transistor
What MP1 was off), the second drive signal VNGHigh potential can just be turned from low potential to attempt to turn on pull-down transistor MN1 conductings.
Either, delay cell 20a makes the second drive signal VNGIt is turned to low level failing edge from high level and redirects action and terminates
Later, the first drive signal VPGJust start to execute and is turned to low level failing edge from high level and redirects action, the one of generation
A expected purpose is, only as the second drive signal VNG(to ensure what pull-down transistor MN1 was off) when low potential, first
Drive signal VPGJust it can turn low potential from high potential to attempt to turn on the MP1 that pulls up transistor.
Referring to Fig. 4, delay cell 20a includes third transistor T3 and the 4th transistor T4, and each all has one
First end (such as source electrode) and a second end (such as drain electrode) and a control terminal (such as grid).The of third transistor T3
The second end of one end and the 4th transistor T4 interconnect and the second end of third transistor T3 and the 4th transistor
First end interconnect, also require third transistor T3 conducting channel type and the 4th transistor T4 on the contrary, example
If third transistor T3 is pmos fet and the 4th transistor T4 is NMOS fet, it is equivalent to third crystalline substance
Both body pipe T3 and the 4th transistor T4 constitute a CMOS complementary switch.And the phase inverter that pre-driver 20 includes
The input terminal of INV is connected to node N4 and output end (at a node N3) while to be connected to third transistor T3 and the 4th brilliant
The respective grid control terminals of body pipe T4, so the section of the drain interconnection in the drain electrode and pull-down transistor MN1 for the MP1 that pulls up transistor
The output signal Q generated at point N4OUTInversion signal third transistor T3 and the 4th transistor are transported to by phase inverter INV
The respective grids of T4.Because no matter conducting channel type and the 4th transistor T4 of third transistor T3 are on the contrary, export letter
Number QOUTBe high level or low level (namely no matter output signal QOUTInversion signal be low level or high level), then
It is conducting that must have one in both three transistor T3 and the 4th transistor T4, and what another one was off, therefore postpone single
First 20a can be always maintained at the state of normally opened (Normally-ON) in pre-driver 20.Specifically, such as output letter
Number QOUTInversion signal be that then third transistor T3 is connected and the 4th transistor T4 shutdown low level, in another example, output signal
QOUTInversion signal be high level then third transistor T3 shutdowns and the 4th transistor T4 is connected.
In order to facilitate narration, the first end of setting third transistor T3 and the second end of the 4th transistor T4 are interconnected on
The a port P1 of delay cell 20a, and the second end of setting third transistor T3 and the first end of the 4th transistor it is mutual
It is connected to a port P2 in delay cell 20a.The specifically first end of third transistor T3 and the 4th transistor T4
Second end is connected to the second end of the first transistor T1 and the second end of third transistor T3 and the 4th transistor T4's together
First end is all connected to the second end of second transistor T2.Because by an input signal QINIt is input to the first, second crystalline substance simultaneously
The respective grid control terminals of body pipe T1, T2, so if working as input signal QINFor the first logic state (such as low level state)
When, the first transistor T1 of PMOS is connected and the second transistor T2 shutdowns of NMOS, or if works as input signal QINIt is
When two logic state (such as high level state), the first transistor T1 of PMOS is turned off and the second transistor T2 of NMOS is connected.
In the first scenario, the first transistor T1 is connected, second transistor T2 shutdowns can lead to the first transistor T1
Voltage V at the node N1 of second endARapid rising, voltage VACan rise to close to the first transistor T1 first end institute it is defeated
The high voltage level of the first reference voltage source (such as supply voltage VDD) entered, and based in second transistor T2 turn-off criterions
Lower voltage VARising can also tend to be lifted the voltage V at the node N2 of the second end of second transistor T2B, but delay cell
The delay effect of 20a leads to voltage VBRising opportunity lag behind voltage VARise time node.It is opposite with the first situation
It is that in the latter case, the first transistor T1 shutdowns, second transistor T2 connect the second end that can lead to second transistor T2
Node N2 at voltage VBRapid decline, voltage VBThe first end close to second transistor T2 is inputted can be dropped to
The low-voltage level of two reference voltage sources (such as GND or negative potential VSS), and based on electric under the first transistor T1 turn-off criterions
Press VBDecline can also tend to reduce the voltage V at the node N1 of the first end of the first transistor T1A, but delay cell 20a
Delay effect leads to voltage VADecline opportunity lag behind voltage VBReduction timing node.
Voltage V at the node N1 of the second end of the first transistor T1ARapid ascent stage, from low level to high electricity
The voltage V of flat rapid translating roleAThe similar step signal that essence is input into the port P1 of delay cell 20a (has and rises
Edge), this stage, delay cell 20a was equivalent to a resistance element, and the equivalent resistance having is enough to postpone second transistor
The voltage V of (voltage signal exported from the port P2 of delay cell 20a) at the node N2 of the second end of T2BRising, especially
It is that there is also inevitable parasitic capacitances at node N2 and between on the ground.Vice versa, second transistor T2's
Voltage V at the node N2 of second endBThe rapid decline stage, from high level to the voltage V of low level rapid translating roleBIt is real
Matter is input into the similar step signal (have failing edge) of the port P2 of delay cell 20a, this stage delay cell 20a also phases
When in a resistance element, the equivalent resistance having be enough to postpone at the node N1 of the second end of the first transistor T1 (i.e. from
Delay cell 20a port P1 output voltage signal) voltage VADecline, at especially node N1 and between on the ground
There is also inevitable parasitic capacitances.
In order to more intuitively learn voltage VASignal and voltage VBThe relative time of both signals risen or fallen is stagnant
Relationship afterwards thereby generates a time delay, and makes VPG/VNGPMOS/NMOS transistor npn npns are controlled in a manner of non-overlapping
The grid voltage of MP1/MN1, is finally reached the switching of MP1/MN1 transistor complementary formulas, and the present invention specially illustrates the in figures 5-6
One, the second drive signal VPG/VNGResponse mechanism.
Referring to Fig. 4 and Fig. 5, as input signal QINFor the first logic state (such as low level) when, the first transistor T1 conducting
And second transistor T2 shutdowns so that the voltage V of the second end (at node N1) of the first transistor T1ALifting, voltage VAIt is defeated
Enter to a buffer B1 either voltage follower/followers, level shift effect can be carried, from the defeated of buffer B1
Outlet exports and provides a first drive signal V for being coupled to the MP1 grids that pull up transistorPG, voltage VALifting leads to first
Drive signal VPGBy the first logic state (such as low level) overturning to the second logic state (such as high level).At the same time, as
Described above, delay cell 20a slows down the voltage V of the second end (at node N2) of second transistor T2BIt is lifted speed, this
Kind carryover effects embody in Figure 5.Only in the first drive signal VPGOverturn to the second logic state action after, second
The voltage V of the second end of transistor T2BJust start to be lifted, voltage V is shown in Fig. 5AThe timing node of rotary movement is executed to electric
Press VBIt is T to execute the delay time between the timing node of overturningDelay1, voltage VBAfter being input to a buffer B2, postpone
The output end for rushing device B2 exports and provides a second drive signal V for being coupled to pull-down transistor MN1 gridsNG, voltage VBLift
Rising further makes the second drive signal VNGStart to be turned to the second logic state by the first logic state.Finally, the second driving letter
Number VNGThe timing node of overturning (rising edge) action is executed than the first drive signal VPGExecute the time of overturning (rising edge) action
The time that node will put off backward on a timeline is TDelay1, embodied in Figure 5.
Referring to Fig. 4 and Fig. 6, as input signal QINFor the second logic state (such as high level) when, the first transistor T1 shutdown
And second transistor T2 conductings so that the voltage V of the second end (at node N2) of second transistor T2BDecline, voltage VBIt is defeated
Enter to a buffer B2 either voltage follower/followers, level shift effect can be carried, from the defeated of buffer B2
Outlet exports and provides a second drive signal V for being coupled to pull-down transistor MN1 gridsNG, voltage VBDecline leads to second
Drive signal VNGFirst logic state (such as low level) is back to by the second logic state (such as high level) overturning.At the same time,
As described above, delay cell 20a slows down the voltage V of the second end (at node N1) of the first transistor T1ADrop-down
Speed, this carryover effects embody in figure 6.Only in the second drive signal VNGIt overturns to the action of the first logic state and terminates
Afterwards, the voltage V of the second end of the first transistor T1AJust start to pull down, voltage V is shown in Fig. 6BExecute the time of rotary movement
Node is to voltage VAIt is T to execute the delay time between the timing node of overturningDelay2, voltage VAIt is input to a buffer B1
Afterwards, it is exported from the output end of buffer B1 and a first drive signal V for being coupled to the MP1 grids that pull up transistor is providedPG, electricity
Press VADecline further makes the first drive signal VPGStart to return to the first logic state by the overturning of the second logic state.Finally,
First drive signal VPGThe timing node of overturning (failing edge) action is executed than the second drive signal VNGExecute overturning (failing edge)
The time that the timing node of action will put off backward on a timeline is TDelay2, embodied in figure 6.
Realize that the mechanism that the mechanism of delay and Fig. 4 realize delay can be known by comparison diagram 2-3, it is provided by the present invention
Pre-driver 20 may finally efficiently reduce the number of transistor because the use of NAND, NOR logic gate can be reduced
Amount, to realize diminution chip area, while using the equivalent resistance of delay cell 20a a pair of of the bias transistors having, also
The use of high resistance measurement (being typically kilohm K Ω ranks) can be reduced and additional light shield can be reduced, such advantage is for industry
Boundary have be undoubtedly for the usual skill in this field be happy to see its at.
More than, by description and accompanying drawings, give the exemplary embodiments of the specific structure of specific implementation mode, foregoing invention
Existing preferred embodiment is proposed, but these contents are not intended as limiting to.For a person skilled in the art, in reading
State it is bright after, various changes and modifications undoubtedly will be evident.Therefore, appended claims, which should be regarded as, covers the present invention
True intention and range whole variations and modifications.In Claims scope the range of any and all equivalences with it is interior
Hold, is all considered as still belonging to the intent and scope of the invention.
Claims (10)
1. a kind of output driving circuit, which is characterized in that including a pre-driver, the pull-up for driving an output stage
Transistor and pull-down transistor alternate conduction, so that the output signal that the output stage is provided is in the first, second logic state
Between switch, and the first drive signal of pre-driver output is used to driving and described pull up transistor and export
Second drive signal is for driving the pull-down transistor, the pre-driver to include：
First, second transistor, each all have a first end and a second end and a control terminal, an input
Signal is input to the control terminal of first, second transistor simultaneously, first, second transistor respective described the
One end corresponds to and is connected respectively to the first, second reference voltage source and the respective second end of first, second transistor
Between connection there are one the delay cell controlled by the output signal, the delay cell is for avoiding described first, second
The logic state of drive signal generates the overturning of rising edge or failing edge simultaneously.
2. output driving circuit according to claim 1, which is characterized in that when first drive signal is by described first
When logic state is turned to second logic state, the delay cell generates delay effect, makes first drive signal
Second drive signal is just turned to second logic state by first logic state after overturning.
3. output driving circuit according to claim 1, which is characterized in that when second drive signal is by described second
When logic state is turned to first logic state, the delay cell generates delay effect, makes second drive signal
First drive signal is just turned to first logic state by second logic state after overturning.
4. output driving circuit according to claim 1, which is characterized in that the delay cell includes third, the 4th crystalline substance
Body pipe, each all have a first end and a second end and a control terminal；Wherein
It is brilliant that the first end of the third transistor and the second end of the 4th transistor are all connected to described first
The second end of body pipe and the second end of the third transistor and the first end of the 4th transistor are all
It is connected to the second end of the second transistor, and the output is inputted in the third, the control terminal of the 4th transistor
The inversion signal of signal.
5. output driving circuit according to claim 1, which is characterized in that further include first buffer, input
End is connected to the second end of the first transistor and its output end then provides first drive signal.
6. output driving circuit according to claim 1, which is characterized in that further include second buffer, input
End is connected to the second end of the second transistor and its output end then provides second drive signal.
7. output driving circuit according to claim 2, which is characterized in that when the input signal is the first logic state
When, the first transistor is connected and the second transistor turns off so that the electricity of the second end of the first transistor
Pressure is lifted and first drive signal is caused to be overturn to second logic state by first logic state；
The delay cell slows down the voltage lifting speed of the second end of second crystal, in first drive signal
After overturning, the voltage of the second end of second crystal just starts to be lifted and further make second drive signal
Start to be turned to second logic state by first logic state.
8. output driving circuit according to claim 3, which is characterized in that when the input signal is the second logic state
When, the first transistor turns off and the second transistor is connected so that the electricity of the second end of the second transistor
Pressure drags down and second drive signal is caused to be overturn to first logic state by second logic state；
The delay cell slows down the voltage drop low velocity of the second end of the first crystal, in second drive signal
After overturning, the voltage of the second end of the first crystal just starts to reduce and further make first drive signal
Start to be turned to first logic state by second logic state.
9. output driving circuit according to claim 4, which is characterized in that further include a phase inverter, the phase inverter
Input terminal receive the output signal and the output end of the phase inverter is connected to the control of the third, the 4th transistor
End processed.
10. output driving circuit according to claim 4, which is characterized in that the conducting channel class of the third transistor
Type and the 4th transistor are on the contrary, the inversion signal of the output signal controls both the third, the 4th transistor
One of shutdown when another one be connected.
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| CN201710262766.0A CN108736863B (en) | 2017-04-20 | 2017-04-20 | Output driving circuit |
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| CN201710262766.0A CN108736863B (en) | 2017-04-20 | 2017-04-20 | Output driving circuit |
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| CN108736863B CN108736863B (en) | 2022-02-25 |
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| CN111682873A (en) * | 2020-05-08 | 2020-09-18 | 北京中电华大电子设计有限责任公司 | Low-power-consumption output buffer circuit |
| CN114155893A (en) * | 2020-09-07 | 2022-03-08 | 长鑫存储技术有限公司 | Driving circuit |
| CN114244339A (en) * | 2022-01-04 | 2022-03-25 | 芯洲科技（北京）有限公司 | Gate drive circuit and electronic device |
| US11444619B2 (en) | 2020-09-07 | 2022-09-13 | Changxin Memory Technologies, Inc. | Driving circuit |
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| CN108736863B (en) | 2022-02-25 |
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Address after: 1568 Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201506 Patentee after: Shanghai Hehui optoelectronic Co.,Ltd. Address before: 1568 Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201506 Patentee before: EVERDISPLAY OPTRONICS (SHANGHAI) Ltd. |