CN108736863B - Output driving circuit - Google Patents

Output driving circuit Download PDF

Info

Publication number
CN108736863B
CN108736863B CN201710262766.0A CN201710262766A CN108736863B CN 108736863 B CN108736863 B CN 108736863B CN 201710262766 A CN201710262766 A CN 201710262766A CN 108736863 B CN108736863 B CN 108736863B
Authority
CN
China
Prior art keywords
transistor
output
terminal
signal
logic state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710262766.0A
Other languages
Chinese (zh)
Other versions
CN108736863A (en
Inventor
邹文安
邱卫斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EverDisplay Optronics Shanghai Co Ltd
Original Assignee
EverDisplay Optronics Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EverDisplay Optronics Shanghai Co Ltd filed Critical EverDisplay Optronics Shanghai Co Ltd
Priority to CN201710262766.0A priority Critical patent/CN108736863B/en
Publication of CN108736863A publication Critical patent/CN108736863A/en
Application granted granted Critical
Publication of CN108736863B publication Critical patent/CN108736863B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H03K2005/00215—Layout of the delay element using FET's where the conduction path of multiple FET's is in parallel or in series, all having the same gate control

Abstract

The invention mainly relates to a driver circuit for a semiconductor power switch, and designs an output driver circuit with a predriver, wherein a first driving signal output by the predriver is used for driving a pull-up transistor of an output stage and a second driving signal output by the predriver is used for driving a pull-down transistor of the output stage, and the predriver is provided with a delay unit, so that complementary transistors of the output stage can be prevented from being simultaneously conducted in a complementary transistor stage of the control output stage.

Description

Output driving circuit
Technical Field
The present invention relates generally to driver circuits for semiconductor power switches, and more particularly to an output driver circuit with a delay effect to prevent complementary transistors of an output stage from turning on at the same time during the control of the complementary transistors of the output stage.
Background
In a driver circuit applied to a semiconductor power switch, in order to obtain the maximum output power and reduce the power consumption of transistors as much as possible, an output stage transistor is usually driven by a control signal generated by a pre-driver to perform complementary switching to drive a P-type transistor and an N-type transistor, so as to avoid power loss caused by simultaneous conduction of the P-type transistor and the N-type transistor, and to avoid irreversible thermal damage caused by simultaneous conduction of the P-type transistor and the N-type transistor, otherwise, the P-type transistor and the N-type transistor which are both conducted are directly connected in series between a power supply and a ground terminal.
Prior publications such as chinese patent application (CN103890682) disclose a driver circuit for a semiconductor power switch, comprising a first power driver transistor and a second power driver transistor complementary thereto, the output terminals of the two power driver transistors being connected to the input terminal of the power switch, the input terminal of the second power driver transistor being connected to a half bridge circuit, the latter comprising a first pre-driver transistor and a second pre-driver transistor complementary thereto, the output terminals of the two pre-driver transistors being connected to the input terminal of the second power driver transistor, thereby providing a fast switching time for the pre-driver transistors and greatly reducing the power consumption of the transistors.
Prior publications such as chinese patent application (CN102904423) disclose a preceding stage driving circuit and a power module driver, wherein the preceding stage driving circuit includes a first N-channel enhancement type metal oxide semiconductor type field effect transistor MOS transistor and a second N-channel enhancement type MOS transistor: the first N-channel enhancement type MOS tube is connected between a first Pulse Width Modulation (PWM) signal input end of the preceding-stage driving circuit and a second input end of the driving control module; the second N-channel enhancement type MOS tube is connected between the second PWM signal input end of the preceding-stage driving circuit and the first input end of the driving control module. When the two input ends of the controller can output high level, the MOS tube converts the high level into low level to output to the power transistor inverter, and the phenomenon of short circuit caused by that upper and lower Bridge arms (Bridge-Legs) of the same phase of the power transistor inverter receive high level signals in the same time period is prevented, so that the reliability and the stability of a motor driving system are improved.
In none of the existing solutions, it is not an architecture that uses a large number of components as a pre-driver, and it is known to those skilled in the art that the area of the layout is directly increased by the large number of components, and especially, a large number of photomasks are needed in the wafer preparation stage of the wafer casting, which results in a significant cost.
Disclosure of Invention
In an alternative embodiment, the present invention provides an output driving circuit including a predriver for driving pull-up and pull-down transistors of an output stage to be alternately turned on to switch an output signal provided by the output stage between first and second logic states, and outputting a first driving signal for driving the pull-up transistors and outputting a second driving signal for driving the pull-down transistors, the predriver comprising: the first and second transistors are respectively provided with a first end, a second end and a control end, an input signal is simultaneously input to the control ends of the first and second transistors, the first ends of the first and second transistors are correspondingly and respectively connected to a first reference voltage source and a second reference voltage source, a delay unit controlled by the output signal is connected between the second ends of the first and second transistors, and the delay unit is used for avoiding the logic states of the first and second driving signals from simultaneously generating the inversion of a rising edge or a falling edge.
In the output driving circuit, when the first driving signal is inverted from the first logic state to the second logic state, the delay unit generates a delay effect, so that the second driving signal is inverted from the first logic state to the second logic state only after the inversion of the first driving signal is finished.
In the output driving circuit, when the second driving signal is inverted from the second logic state to the first logic state, the delay unit generates a delay effect, so that the first driving signal is inverted from the second logic state to the first logic state only after the inversion of the second driving signal is finished.
In the above output driving circuit, the delay unit includes third and fourth transistors each having a first terminal, a second terminal and a control terminal; wherein the first terminal of the third transistor and the second terminal of the fourth transistor are both connected to the second terminal of the first transistor, and the second terminal of the third transistor and the first terminal of the fourth transistor are both connected to the second terminal of the second transistor, and inverted signals of the output signals are input at control terminals of the third and fourth transistors.
The output driving circuit further includes a first buffer, an input terminal of which is connected to the second terminal of the first transistor, and an output terminal of which provides the first driving signal.
The output driving circuit further includes a second buffer, an input terminal of the second buffer is connected to the second terminal of the second transistor, and an output terminal of the second buffer provides the second driving signal.
In the above output driving circuit, when the input signal is at a first logic state (e.g., low level), the first transistor is turned on and the second transistor is turned off, so that the voltage at the second terminal of the first transistor is raised and the first driving signal is caused to flip from the first logic state to a second logic state (e.g., high level); the delay unit slows down the voltage rising speed of the second end of the second crystal, and after the first driving signal is turned over, the voltage of the second end of the second crystal starts rising to further enable the second driving signal to start to be turned over from the first logic state to the second logic state.
In the above output driving circuit, when the input signal is in a second logic state (e.g. high level), the first transistor is turned off and the second transistor is turned on, so that the voltage at the second terminal of the second transistor is pulled low and the second driving signal is caused to flip from the second logic state to the first logic state (e.g. low level); the delay unit slows down the voltage reduction speed of the second end of the first crystal, and after the second driving signal is turned over, the voltage of the second end of the first crystal starts to be reduced, so that the first driving signal starts to be turned over from the second logic state to the first logic state.
The output driving circuit further comprises an inverter, wherein an input end of the inverter receives the output signal and an output end of the inverter is connected to the control ends of the third and fourth transistors.
In the above output driving circuit, the third transistor has a conduction channel type opposite to that of the fourth transistor, the third and fourth transistors constitute a CMOS complementary channel switch, and the inverted signal of the output signal controls one of the third and fourth transistors to be turned off and the other to be turned on.
Drawings
The features and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the following drawings:
fig. 1 is a basic architecture of a predriver using a delay cell for driving an output stage transistor.
Fig. 2 is a basic architecture of a predriver driving output stage transistors using NAND gates.
Fig. 3 is a basic architecture of a predriver driving output stage transistors using NOR gates.
Fig. 4 is a basic architecture of a predriver driving output stage transistors that eliminates the use of NAND, NOR logic gates.
FIG. 5 is a signal V driving the output stage transistorNGRelative signal VPGThe resulting delay effect.
FIG. 6 is a signal V driving the output stage transistorPGRelative signal VNGThe resulting delay effect.
Detailed Description
The technical solutions of the present invention will be clearly and completely described below with reference to various embodiments, but the described embodiments are only used for describing and illustrating the present invention and not for describing all embodiments, and the solutions obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.
In order to understand the spirit of the present invention more deeply, we first explain the conventional implementation of fig. 1 to 3 that can implement delay by using more components, and then compare with the delay implementation of fig. 4 that can greatly reduce the number of components provided by the present invention.
Referring to fig. 1, an input signal Q is receivedINThe predriver 10 of (a) comprises two control branches, a first control branch comprising a delay unit 1 and additional buffers etc., and a second control branch comprising a delay unit 2 and additional buffers etc. Wherein the first control branch mainly generates a control signal VPGFor driving the PMOS transistor MP1, the second control branch mainly generates a control signal VNGFor driving NMOS transistor MN 1. The source of the PMOS transistor MP1 of the output stage is connected to a power supply voltage VDD, the source of the NMOS transistor MN1 of the output stage is connected to a ground terminal GND, and a capacitor C is connected between a node where the drain of the transistor MP1 and the drain of the transistor MN1 are connected to each other and the ground terminal GND, and a desired output signal Q is generated at the node where they are connected to each otherOUT. Based on the consideration that the delay units 1 and 2 are required to have the function of causing the signal to generate time delay in the transmission processIn effect, the first control branch of the predriver 10 generates the drive signal V for controlling the high-side transistor MP1PGCompared with the drive signal V generated by the second control branch for controlling the low-side transistor MN1NGThe two transistors have time delay on time nodes, so that the transistor MP1 and the transistor MN1 are not conducted simultaneously, the power supply voltage VDD is prevented from directly penetrating through the transistor MP1 and the transistor MN1 which are in a conducting state to the ground terminal GND, and the transistor MP1 and the transistor MN1 are not damaged.
Referring to fig. 2, a first control branch of the predriver 11 includes a NAND gate 11a and additional inverters, buffers, etc., a second control branch of the predriver 11 includes a NOR gate 11b and additional inverters, buffers, etc., the NAND gate 11a and the NOR gate 11b both belong to digital logic gates, and both of them need a plurality of transistors for construction. When the second control branch, i.e. the control signal V generated by the NOR gate 11bNGAt logic low/level, the control signal VNGThe inverted signal generated by an inverter, i.e. a logic high level, is input to an input of the nand-gate 11a in the first control branch, so that the output V of the nand-gate 11a is now presentPGIt is possible to switch from high level to low level, and this stage is due to the control signal V driving the NMOS transistor MN1NGIs low so that the transistor MN1 will not conduct, but the control signal V driving the PMOS transistor MP1PGUnder such a condition, the transistor MP1 can be turned on by falling to a low level, thereby preventing the simultaneous turn-on of the transistor MN1 and the transistor MP 1. Vice versa, when the first control branch is also the control signal V generated by the NAND gate 11aPGAt logic high level, the control signal VPGAn inverted signal, i.e., a logic low level, generated by an inverter is input to one input terminal of the nor gate 11b in the second control branch, so that the output V of the nor gate 11b is now presentNGIt is possible to flip from low to high due to the control signal driving the PMOS transistor MP1VPGIs high so that the transistor MP1 does not conduct, but drives the control signal V of the NMOS transistor MN1NGIn this condition, the transistor MN1 can be turned on by toggling to the high level, thereby avoiding the occurrence of a situation in which both the transistor MN1 and the transistor MP1 are turned on at the same time.
Referring to fig. 3, the first control branch of the predriver 12 includes a NAND gate 12a and additional inverters, buffers, etc., and the second control branch of the predriver 11 includes a NAND gate 12b and additional inverters, etc. When the output of the second control branch, that is, the NAND gate 12b, is at high level but inverted, the control signal V is generatedNGAt logic low potential, the control signal VNGThe inverted signal generated by an inverter, i.e. high level, is input to an input of the NAND gate 12a in the first control branch, so that the output V of the NAND gate 11a is now outputPGIt is possible to switch from high level to low level, and this stage is due to the control signal V driving the NMOS transistor MN1NGIs low so that the transistor MN1 will not conduct, but the control signal V driving the PMOS transistor MP1PGUnder such a condition, the transistor MP1 can be turned on by falling to a low level, thereby preventing the simultaneous turn-on of the transistor MN1 and the transistor MP 1. Vice versa, when the first control branch is also the control signal V generated by the NAND gate 12aPGWhen it is logic high, the control signal VPGDirectly input to an input terminal of the nand gate 12b in the second control branch, so that the output result of the nand gate 12b may be inverted from high level to low level, but the output result of the nand gate 12b is inverted by the inverter to generate the control signal VNGIs logic high, and the control signal V for driving the PMOS transistor MP1 is used at this stagePGIs high so that the transistor MP1 will not be turned on, but the control signal V for driving the NMOS transistor MN1NGUnder this condition, the transistor MN1 can be turned to high level to turn on the transistor MN1 and MP 1.
In the above discussion, since they are not the focus of the present invention, each component is not fully explained individually, but is merely an exemplary simple introduction, in which the complex configuration of digital logic gates such as nand gate and nor gate, which are constructed by multiple transistors, has disadvantages of occupying a large layout area and bringing a significant cost problem, and in view of abandoning such a highly complex driver as much as possible to construct a new simplified driver topology, a new embodiment of the present invention is shown in fig. 4, which replaces the digital logic gates largely used in the original manner.
Referring to fig. 4, in the topology, an Output Driver Circuit (Output Driver Circuit) is provided, which mainly includes a Pre-Driver (Pre-Driver)20 and an Output stage (Output stage) Circuit. The output stage comprises a pull-up transistor MP1 of PMOS type and a pull-down transistor MN1 of NMOS type, the source of the pull-up transistor MP1 being connected to a first reference voltage source (e.g. supply voltage VDD) of high voltage level, and the source of the pull-down transistor MN1 being connected to a second reference voltage source (e.g. ground GND) of relatively low voltage level, the former having a higher potential level than the latter. And the drain of pull-up transistor MP1 and the drain of pull-down transistor MN1 are interconnected at node N4, the desired output signal QOUTGenerated at the node N4. Predriver 20 is configured to drive pull-up transistor MP1 and pull-down transistor MN1 of the output stage to be alternately turned on, and specifically, pull-up transistor MP1 is turned on while pull-down transistor MN1 is turned off, or pull-down transistor MN1 is turned off while pull-up transistor MP1 is turned off, so that output signal Q provided at node N4 by the output stageOUTSwitching between a first logic state (e.g., low) and a second logic state (e.g., high). Output signal Q when pulldown transistor MN1 is onOUTIs close to the second reference voltage source, outputs the signal Q when the pull-up transistor MP1 is turned onOUTIs close to the first reference voltage source.
Control signal V output by predriver 20PG(i.e., the first driving signal) is coupled to the gate control terminal of pull-up transistor MP1 for driving pull-up transistor MP1, and control signal V output from pre-driver 20NG(i.e. theA second drive signal) is coupled to the gate control terminal of the pull-down transistor MN1 for driving the pull-down transistor MN 1.
Referring to fig. 4, the predriver 20 includes a first transistor T1 and a second transistor T2, the first transistor T1 and the second transistor T2 each having a first terminal and a second terminal and a control terminal, the first transistor T1 being, for example, a PMOS type field effect transistor, the first transistor T1 being, for example, an NMOS type field effect transistor, having a first terminal, for example, a source, and a second terminal, for example, a drain, and the control terminal, for example, a gate. Wherein an output signal Q is connected between the second terminal of the first transistor T1 and the second terminal of the second transistor T2OUTControlled delay unit 20a, the significance of the delay unit 20a being to avoid the first drive signal VPGA second drive signal VNGAre flipped simultaneously. Specifically, the delay unit 20a, which can generate a delay effect, makes the first driving signal VPGAfter the rising edge jump action of switching from low level to high level is finished, the second drive signal VNGThe execution of the rising edge jump action from a low level to a high level is only started, which results in a desired aim only when the first drive signal V is presentPGAt high potential (ensuring that pull-up transistor MP1 is off), the second drive signal V is set to zeroNGIt may go from low to high in an attempt to turn on pull-down transistor MN1 to conduct. Alternatively, the delay unit 20a makes the second drive signal VNGAfter the falling edge jump action of switching from high level to low level is finished, the first drive signal VPGThe falling-edge jump action of the transition from high level to low level is only started, which has as one intended purpose that only when the second drive signal V is presentNGWhen the voltage is low (ensuring that the pull-down transistor MN1 is turned off), the first driving signal V is set to be lowPGCan go from high to low in an attempt to turn on pull-up transistor MP 1.
Referring to fig. 4, the delay cell 20a includes a third transistor T3 and a fourth transistor T4, each having a first terminal (e.g., source) and a second terminal (e.g., drain) and a control terminal (e.g., gate)). The first terminal of the third transistor T3 and the second terminal of the fourth transistor T4 are connected to each other, and the second terminal of the third transistor T3 and the first terminal of the fourth transistor are connected to each other, which also requires that the conductivity channel type of the third transistor T3 is opposite to that of the fourth transistor T4, such as the third transistor T3 is a PMOS field effect transistor and the fourth transistor T4 is an NMOS field effect transistor, which corresponds to both the third transistor T3 and the fourth transistor T4 constituting a CMOS complementary switch. And the pre-driver 20 includes an inverter INV having an input terminal connected to the node N4 and an output terminal (at a node N3) connected to the gate control terminals of the third and fourth transistors T3 and T4, respectively, an output signal Q generated at a node N4 where the drain of the pull-up transistor MP1 and the drain of the pull-down transistor MN1 are interconnectedOUTIs supplied to the respective gates of the third transistor T3 and the fourth transistor T4 through the inverter INV. Since the third transistor T3 has the opposite conduction channel type to the fourth transistor T4, regardless of the output signal QOUTWhether high or low (i.e. regardless of the output signal Q)OUTIs low or high), one of the third transistor T3 and the fourth transistor T4 must be turned ON and the other is turned off, so that the delay cell 20a is always kept in a Normally-ON state in the front-stage driver 20. Specifically, for example, the output signal QOUTIs low, the third transistor T3 is turned on and the fourth transistor T4 is turned off, and for example, the output signal QOUTThe third transistor T3 is turned off and the fourth transistor T4 is turned on if the inverted signal of (b) is a high level.
For convenience of description, the first terminal of the third transistor T3 and the second terminal of the fourth transistor T4 are set to be connected to each other at one port P1 of the delay unit 20a, and the second terminal of the third transistor T3 and the first terminal of the fourth transistor are set to be connected to each other at one port P2 of the delay unit 20 a. Specifically, the first terminal of the third transistor T3 and the second terminal of the fourth transistor T4 are connected together to the second terminal of the first transistor T1, and the second terminal of the third transistor T3 and the first terminal of the fourth transistor T4 are connected to the second terminal of the second transistor T2.Because of one input signal QINAre simultaneously inputted to the respective gate control terminals of the first and second transistors T1, T2, so that if a signal Q is inputtedINIn a first logic state (e.g., a low state), the first transistor T1 of the PMOS is turned on and the second transistor T2 of the NMOS is turned off, or if the input signal Q is assertedINIn a second logic state (e.g., a high state), the first transistor T1 of the PMOS is turned off and the second transistor T2 of the NMOS is turned on.
In the first case, the first transistor T1 being turned on and the second transistor T2 being turned off results in the voltage V at the node N1 of the second terminal of the first transistor T1AIs rapidly raised, voltage VARises to a high voltage level close to the first reference voltage source (e.g., the power voltage VDD) inputted to the first terminal of the first transistor T1, and is based on the voltage V at the off condition of the second transistor T2AAlso tends to raise the voltage V at the node N2 of the second terminal of the second transistor T2BHowever, the delay effect of the delay cell 20a causes the voltage VBLags behind the voltage VAThe rise time node of (2). In the second case, the first transistor T1 is turned off and the second transistor T2 is turned on, which results in the voltage V at the node N2 of the second terminal of the second transistor T2, opposite to the first caseBIs rapidly reduced, voltage VBDrops to a low voltage level close to the second reference voltage source (e.g., GND or negative potential VSS) inputted to the first terminal of the second transistor T2 based on the voltage V at the off condition of the first transistor T1BAlso tends to lower the voltage V at the node N1 of the first terminal of the first transistor T1AHowever, the delay effect of the delay cell 20a causes the voltage VALags behind the voltage VBThe reduced time node of (2).
A voltage V at a node N1 of the second terminal of the first transistor T1ARapid rising phase of the voltage V for rapidly switching roles from low level to high levelAEssentially a step-like signal (with a rising edge) input to port P1 of delay cell 20 a. the phase delay cell 20a acts as a resistive element with an equivalent resistance valueIt is sufficient to delay the voltage V at the node N2 (i.e., the voltage signal output from the port P2 of the delay cell 20 a) of the second terminal of the second transistor T2BThere is also an inevitable parasitic capacitance between node N2 and ground, in particular. Vice versa, the voltage V at the node N2 at the second terminal of the second transistor T2BDuring the rapid falling phase, the voltage V of the role is rapidly switched from high level to low levelBSubstantially like a step signal (having a falling edge) inputted to the port P2 of the delay unit 20a, the delay unit 20a also acts as a resistive element having an equivalent resistance value sufficient to delay the voltage V at the node N1 of the second terminal of the first transistor T1 (i.e., the voltage signal outputted from the port P1 of the delay unit 20 a)AThere is also an inevitable parasitic capacitance between node N1 and ground, in particular.
To be able to learn the voltage V more intuitivelyASignal and voltage VBThe relative time lag relationship between the rise and fall of the two signals is used to generate a time delay, so that VPG/VNGThe gate voltages of the PMOS/NMOS transistors MP1/MN1 are controlled in a non-overlapping manner to achieve complementary switching of the transistors MP1/MN 1. the present invention specifically shows the first and second driving signals V in FIGS. 5-6PG/VNGThe response mechanism of (2).
Referring to fig. 4 and 5, when the signal Q is inputtedINIn a first logic state (e.g., low level), the first transistor T1 is turned on and the second transistor T2 is turned off, such that the voltage V at the second terminal (at the node N1) of the first transistor T1AIs raised by a voltage VAIs input to a buffer B1 or voltage follower/follower with level shifting effect, outputs from the output terminal of the buffer B1 and provides a first drive signal V coupled to the gate of the pull-up transistor MP1PGVoltage V ofAThe lifting results in a first drive signal VPGFrom a first logic state (e.g., low) to a second logic state (e.g., high). Meanwhile, as described above, the delay unit 20a buffers the voltage V at the second terminal (at the node N2) of the second transistor T2BThe lifting speed, whichThis delay effect is shown in figure 5. Only at the first drive signal VPGAfter the action of turning to the second logic state is finished, the voltage V of the second terminal of the second transistor T2BOnly begins to rise, and the voltage V is shown in fig. 5ATime node to voltage V for performing a flipping actionBThe delay time between the time nodes performing the roll-over is TDelay1The voltage V isBIs input to a buffer B2, and is output from the output terminal of the buffer B2 to provide a second driving signal V coupled to the gate of a pull-down transistor MN1NGVoltage V ofBThe lifting further makes the second driving signal VNGA transition from the first logic state to the second logic state is initiated. Finally, the second drive signal VNGThe time node at which the flip (rising edge) action is performed is larger than the first drive signal VPGThe time node performing the flip (rising edge) action is delayed backwards on the time axis by TDelay1As is shown in fig. 5.
Referring to fig. 4 and 6, when the signal Q is inputtedINIn a second logic state (e.g., high level), the first transistor T1 is turned off and the second transistor T2 is turned on, so that the voltage V at the second terminal (at the node N2) of the second transistor T2BDecrease of the voltage VBIs input to a buffer B2 or voltage follower/follower with level shifting effect, and is output from the output terminal of the buffer B2 to provide a second driving signal V coupled to the gate of the pull-down transistor MN1NGVoltage V ofBThe drop results in a second drive signal VNGToggles from the second logic state (e.g., high) back to the first logic state (e.g., low). Meanwhile, as described above, the delay unit 20a buffers the voltage V at the second terminal (at the node N1) of the first transistor T1ASuch a delay effect is shown in fig. 6. Only at the second drive signal VNGAfter the action of turning to the first logic state is finished, the voltage V of the second terminal of the first transistor T1AThe pull-down is started and the voltage V is shown in fig. 6BTime node to voltage V for performing a flipping actionAThe delay time between the time nodes performing the roll-over is TDelay2The voltage V isAAfter being input to a buffer B1, a first driving signal V coupled to the gate of a pull-up transistor MP1 is output from the output terminal of the buffer B1PGVoltage V ofAThe first drive signal V is further decreasedPGBegin to flip from the second logic state back to the first logic state. Finally, the first drive signal VPGThe time node performing the flip (falling edge) action is larger than the second drive signal VNGThe time node performing the roll-over (falling edge) action is delayed backwards on the time axis by TDelay2As embodied in fig. 6.
As can be seen from comparing the delay mechanism implemented in fig. 2-3 with the delay mechanism implemented in fig. 4, the predriver 20 provided by the present invention can effectively reduce the number of transistors and thus the layout area because the use of NAND and NOR logic gates can be reduced, and the equivalent resistance of the pair of bias transistors provided in the delay unit 20a can also reduce the use of high-resistance resistors (usually in the kiloohm K Ω level) and thus reduce the additional mask.
While the present invention has been described with reference to the preferred embodiments and illustrative embodiments, it is to be understood that the invention as described is not limited to the disclosed embodiments. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims (9)

1. An output driver circuit comprising a predriver for driving pull-up and pull-down transistors of an output stage to alternately conduct to switch an output signal provided by the output stage between first and second logic states, and a first drive signal output by the predriver for driving the pull-up transistors and a second drive signal output by the predriver for driving the pull-down transistors, the predriver comprising:
a first transistor and a second transistor, each of which has a first terminal and a second terminal and a control terminal, an input signal is simultaneously inputted to the control terminals of the first transistor and the second transistor, the first terminals of the first transistor and the second transistor are correspondingly and respectively connected to a first reference voltage source and a second reference voltage source, and a delay unit controlled by the output signal is connected between the second terminals of the first transistor and the second transistor, the delay unit is used for preventing the logic states of the first driving signal and the second driving signal from simultaneously generating the inversion of a rising edge or a falling edge;
the delay unit comprises a third transistor and a fourth transistor, wherein each transistor is provided with a first end, a second end and a control end; wherein
The first terminal of the third transistor and the second terminal of the fourth transistor are both connected to the second terminal of the first transistor, and the second terminal of the third transistor and the first terminal of the fourth transistor are both connected to the second terminal of the second transistor, and inverted signals of the output signals are input at control terminals of the third and fourth transistors.
2. The output driving circuit according to claim 1, wherein when the first driving signal is flipped from the first logic state to the second logic state, the delay unit generates a delay effect, so that the second driving signal is flipped from the first logic state to the second logic state only after the flipping of the first driving signal is finished.
3. The output driving circuit according to claim 1, wherein when the second driving signal is flipped from the second logic state to the first logic state, the delay unit generates a delay effect, so that the first driving signal is flipped from the second logic state to the first logic state only after the flipping of the second driving signal is finished.
4. The output driver circuit of claim 1, further comprising a first buffer having an input terminal coupled to the second terminal of the first transistor and an output terminal providing the first driving signal.
5. The output driver circuit of claim 1, further comprising a second buffer having an input terminal coupled to the second terminal of the second transistor and an output terminal providing the second driving signal.
6. The output driving circuit according to claim 2, wherein when the input signal is in a first logic state, the first transistor is turned on and the second transistor is turned off, so that the voltage at the second terminal of the first transistor is raised and the first driving signal is caused to flip from the first logic state to the second logic state;
the delay unit slows down the voltage rising speed of the second end of the second transistor, and after the first driving signal is turned over, the voltage of the second end of the second transistor starts rising, so that the second driving signal starts to be turned over from the first logic state to the second logic state.
7. The output driving circuit according to claim 3, wherein when the input signal is in a second logic state, the first transistor is turned off and the second transistor is turned on, so that the voltage at the second terminal of the second transistor is pulled low and the second driving signal is caused to flip from the second logic state to the first logic state;
the delay unit slows down the voltage reduction speed of the second end of the first transistor, and after the second driving signal is turned over, the voltage of the second end of the first transistor starts to be reduced, so that the first driving signal starts to be turned over from the second logic state to the first logic state.
8. The output driver circuit of claim 1, further comprising an inverter, wherein an input of said inverter receives said output signal and an output of said inverter is coupled to said control terminals of said third and fourth transistors.
9. The output driving circuit according to claim 1, wherein the third transistor has a conduction channel type opposite to that of the fourth transistor, and the inverted signal of the output signal controls one of the third and fourth transistors to be turned on while the other is turned off.
CN201710262766.0A 2017-04-20 2017-04-20 Output driving circuit Active CN108736863B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710262766.0A CN108736863B (en) 2017-04-20 2017-04-20 Output driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710262766.0A CN108736863B (en) 2017-04-20 2017-04-20 Output driving circuit

Publications (2)

Publication Number Publication Date
CN108736863A CN108736863A (en) 2018-11-02
CN108736863B true CN108736863B (en) 2022-02-25

Family

ID=63933243

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710262766.0A Active CN108736863B (en) 2017-04-20 2017-04-20 Output driving circuit

Country Status (1)

Country Link
CN (1) CN108736863B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111682873A (en) * 2020-05-08 2020-09-18 北京中电华大电子设计有限责任公司 Low-power-consumption output buffer circuit
CN114155893B (en) * 2020-09-07 2023-07-14 长鑫存储技术有限公司 Driving circuit
US11444619B2 (en) 2020-09-07 2022-09-13 Changxin Memory Technologies, Inc. Driving circuit
CN114244339B (en) * 2022-01-04 2022-08-02 芯洲科技（北京）有限公司 Gate drive circuit and electronic device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355028A (en) * 1992-10-23 1994-10-11 Micron Technology, Inc. Lower power CMOS buffer amplifier for use in integrated circuit substrate bias generators
US6094086A (en) * 1997-05-12 2000-07-25 Industrial Technology Research Institute High drive CMOS output buffer with fast and slow speed controls
CN1496002A (en) * 2002-07-15 2004-05-12 株式会社瑞萨科技 Semiconductor device with complementary metal oxide semiconductor drive circuit
CN102449908A (en) * 2009-05-28 2012-05-09 高通股份有限公司 Short-circuit protection for switched output stages
CN102545603A (en) * 2010-10-29 2012-07-04 三美电机株式会社 Switching power-supply unit
CN103780242A (en) * 2013-05-13 2014-05-07 威盛电子股份有限公司 Driving circuit
CN104348341A (en) * 2013-08-02 2015-02-11 亚德诺半导体集团 Anti-ringing technique for switching power stage

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7969217B2 (en) * 2009-10-13 2011-06-28 Himax Technologies Limited Output buffer with slew-rate enhancement output stage
CN107112988B (en) * 2014-11-07 2018-05-04 贝能思科技有限公司 Switch driver with prevention cross-conduction circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355028A (en) * 1992-10-23 1994-10-11 Micron Technology, Inc. Lower power CMOS buffer amplifier for use in integrated circuit substrate bias generators
US6094086A (en) * 1997-05-12 2000-07-25 Industrial Technology Research Institute High drive CMOS output buffer with fast and slow speed controls
CN1496002A (en) * 2002-07-15 2004-05-12 株式会社瑞萨科技 Semiconductor device with complementary metal oxide semiconductor drive circuit
CN102449908A (en) * 2009-05-28 2012-05-09 高通股份有限公司 Short-circuit protection for switched output stages
CN102545603A (en) * 2010-10-29 2012-07-04 三美电机株式会社 Switching power-supply unit
CN103780242A (en) * 2013-05-13 2014-05-07 威盛电子股份有限公司 Driving circuit
CN104348341A (en) * 2013-08-02 2015-02-11 亚德诺半导体集团 Anti-ringing technique for switching power stage

Also Published As

Publication number Publication date
CN108736863A (en) 2018-11-02

Similar Documents

Publication Publication Date Title
CN108736863B (en) Output driving circuit
EP1102402A1 (en) Level adjustment circuit and data output circuit thereof
CN110663182B (en) Circuit with parallel voltage threshold architecture supporting wide voltage supply range
US7317333B1 (en) Large loading split I/O driver with negligible crowbar
US7511555B2 (en) Level conversion circuit and input-output device using same
US20120001672A1 (en) Apparatuses and methods for a voltage level shifting
US20070164789A1 (en) High Speed Level Shift Circuit with Reduced Skew and Method for Level Shifting
US8441279B2 (en) Scan flip-flop circuits and scan test circuits including the same
JP3953492B2 (en) Output buffer circuit
WO2005107073A1 (en) Break before make predriver and level-shifter
US9780790B2 (en) High speed level shifter circuit
JP3935925B2 (en) Output buffer circuit
JPH035692B2 (en)
JP2003032098A (en) Output buffer circuit
JP5160320B2 (en) Switching drive circuit
KR20040002722A (en) Level shifter, semiconductor integrated circuit and information processing system
JP3794347B2 (en) Differential output buffer, differential input buffer, semiconductor integrated circuit, and circuit board
US20060071695A1 (en) Signal driving circuits including inverters
JP4386918B2 (en) Level shift circuit and semiconductor integrated circuit having the same
US9112486B2 (en) Asymmetric propagation delays in level shifters and related circuits
CN110521124B (en) Output circuit
JP2002353802A (en) Cmos output circuit
US5495182A (en) Fast-fully restoring polarity control circuit
US6111433A (en) Differential output driver with monotonic output transitions
KR100530929B1 (en) Cmos output buffer circuit of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: 1568 Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201506

Patentee after: Shanghai Hehui optoelectronic Co.,Ltd.

Address before: 1568 Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201506

Patentee before: EVERDISPLAY OPTRONICS (SHANGHAI) Ltd.