JP3794347B2 - Differential output buffer, differential input buffer, semiconductor integrated circuit, and circuit board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a differential output buffer that transmits a set of positive and negative signals, a differential input buffer that receives the differential output buffer, a semiconductor integrated circuit including at least one of them, and a circuit board. The present invention relates to a differential output buffer for automatically adjusting to a reference voltage, a differential input buffer, a semiconductor integrated circuit including at least one of them, and a circuit board.
[0002]
[Prior art]
The portion excluding the dotted line block in FIG. 14 shows an example of transmission between LSIs such as computers in a positive / negative pair of differential formats. The differential input buffer 21 of the input-side LSI 200 operates by detecting a point (cross-point potential) where the voltages of a pair of positive and negative differential signals cross, but the signal simultaneously becomes a low level (or high level). When the potential difference between the signals falls below the limit that can be detected by the differential input buffer 21, the output signal malfunctions due to slight noise.
[0003]
This can also occur when the power supply on the output side LSI 100 side is OFF. That is, the intersecting points are shifted due to the characteristics of the transistors in the output buffer circuit, circuit configuration, power supply noise, and the like.
[0004]
[Problems to be solved by the invention]
Since it is unavoidable that the crossing points are shifted, when the signal received by the differential input buffer 21 is used in the internal logic, the timing for latching by the flip-flop (FF) is taken into consideration, or a time longer than a certain time is detected. It can be considered effective only in the case.
[0005]
However, if the signal received in the differential format is a control signal that itself triggers the circuit operation on the input side, like a strobe signal, the sampling timing at the FF cannot be adjusted, and the cross-point shift There is a problem that malfunction when the value becomes large becomes a direct functional failure.
[0006]
Further, as shown in FIG. 14, a circuit (HH detection circuit or LL detection circuit) that compares both the reference voltage Vref and a pair of positive and negative differential signals and detects that both are high or low is provided. It is also possible to suppress the output signal of the differential input buffer 21 during the malfunction period (suppression by # disable).
[0007]
However, there is a problem that the HH or LL detection circuit itself causes a malfunction when the timing design becomes strict due to the improvement of the operating frequency and the deviation of the cross point becomes large.
[0008]
Further, in the signal line connected to the bus, when both the positive and negative signals become High, there is a demand to have a meaning indicating that the bus is not used and to use it for functional logic. Cannot be used due to the above malfunction.
[0009]
[Means for Solving the Problems]
A first differential output buffer according to the present invention is a differential output buffer including a positive side output buffer and a negative side output buffer that outputs a signal having a polarity opposite to the positive side output buffer, the positive side output buffer and the negative side output buffer. Each of the buffers has an output stage in which two transistors whose on / off control levels are reversed to each other are connected in a totem pole connection, a variable delay circuit that can change the delay time in response to an external increase / decrease instruction, and a fixed delay with a fixed delay time The positive side output buffer receives a positive output of a signal to be transmitted, inputs the positive output to the variable delay circuit and the fixed delay circuit, and outputs the variable delay circuit output of one transistor of the output stage. On / off control is performed, and on / off control of the other transistor of the output stage is performed with a fixed delay circuit output, Negative side output buffer receives a negative output of the signal to be transmitted, and performs on-off control of the transistors of the positive-side output buffer as well as an output stage.
[0010]
The second differential output buffer of the present invention is the first differential output buffer, wherein in the positive side output buffer and the negative side output buffer, the totem pole output of the output stage is used as an internal output. A transistor that is controlled to be turned on / off by the above-described method is provided, and this transistor is used as an output transistor of each buffer.
[0011]
A third differential output buffer according to the present invention is the first or second differential output buffer, wherein the fixed delay circuit is not separately provided in the positive side output buffer and the negative side output buffer. The output from a predetermined gate in the middle of the delay gate row of the variable delay circuit is used as a fixed delay output, and this controls the on / off of the other transistor in the output stage.
[0012]
A fourth differential output buffer according to the present invention is a differential output buffer including a positive side output buffer and a negative side output buffer that outputs a signal having a polarity opposite to that of the positive side output buffer. Each of the buffers includes a circuit that creates a differential output of rising and falling of an input signal, a variable delay circuit that can change a delay time in response to an increase / decrease instruction from the outside, a fixed delay circuit that has a constant delay time, A state memory element that can be set and reset; and an output stage in which two transistors whose ON / OFF control levels are reversed to each other are connected to tompole. The positive side output buffer receives a positive output of a signal to be transmitted, and a differentiation circuit One output is input to the variable delay circuit and the other output is input to the fixed delay circuit. The state memory element is set and reset by the output of the variable delay circuit, and both transistors of the output stage are switched by the output of the state memory element. The negative output buffer receives a negative output of a signal to be transmitted. In the same manner as the positive side output buffer, both transistors in the output stage are switched.
[0013]
A fifth differential output buffer according to the present invention is a differential output buffer including a positive side output buffer and a negative side output buffer that outputs a signal having a polarity opposite to the positive side output buffer, the positive side output buffer and the negative side output buffer. Each of the buffers includes a circuit that creates a differential output of rising and falling of an input signal, a variable delay circuit that can change a delay time in response to an increase / decrease instruction from the outside, a fixed delay circuit that has a constant delay time, The positive-side output buffer has a positive output of a signal to be transmitted, one output of the differentiation circuit is a variable delay circuit, and the other output is a fixed delay circuit. The state memory element is set and reset with the fixed delay circuit output and the variable delay circuit output, and the state memory element Performs a switching operation of the output transistors with a force, the negative-side output buffer, the negative output of the signal to be transmitted is input, and performs the switching operation of the positive-side output buffer as well as the output transistor.
[0014]
A sixth differential output buffer of the present invention is any one of the first to fifth differential output buffers, wherein the variable delay circuits of the positive side output buffer and the negative side output buffer have a plurality of gates. A cascade connection of gates, a counter that increases or decreases a value according to an external increase / decrease instruction, and a selector that selects an output corresponding to the counter value among the gate outputs of the gate array To do.
[0015]
A first differential input buffer block according to the present invention includes a first differential input buffer for inputting a differential signal composed of a positive side signal and a negative side signal, and a positive side signal of the differential signal from the outside. A second differential input buffer that receives a supplied reference voltage as an input; a third differential input buffer that receives a negative side signal of the differential signal and the reference voltage; and the second difference. When the dynamic input buffer output and the third differential input buffer output are switched in the direction of a predetermined level among the high / low levels, the switching timing of the second differential input buffer output and the third If there is a time difference in the switching timing of the differential input buffer output, depending on the context, the output source of the signal on the side that switches in the direction of the predetermined level among the differential signals, A phase comparison means for instructing so as to delay or early the switching timing of the order is a direction, characterized in that it has.
[0016]
The second differential input buffer block according to the present invention includes a first differential input buffer for inputting a differential signal composed of a positive side signal and a negative side signal, and a positive side signal of the differential signal from the outside. A second differential input buffer that receives a supplied reference voltage as an input; a third differential input buffer that receives a negative signal of the differential signal and the reference voltage; and the first difference. When it is detected that the second differential input buffer output is switched in advance when the dynamic input buffer output is switched in one potential direction, the positive side signal output source corresponds to the one potential direction. Instructs a delay in switching start timing, and detects that the third differential input buffer output is switched in advance when the first differential input buffer output is switched to the other potential. If that is characterized by having a phase comparing means for indicating the delay of switching timing corresponding to the one potential direction output source of the negative side signal.
[0017]
A third differential input buffer block according to the present invention includes a first differential input buffer for inputting a differential signal composed of a positive side signal and a negative side signal, and a positive side signal of the differential signal from the outside. A second differential input buffer that receives a supplied reference voltage as an input; a third differential input buffer that receives a negative signal of the differential signal and the reference voltage; and the first difference. When the switching of the second differential input buffer output or the switching of the third differential input buffer output preceding the switching of the dynamic input buffer output in the direction of one potential is detected, the positive side signal The output source is instructed to delay or accelerate the switching timing corresponding to the one potential direction, and the first differential input buffer output is preceded when the output is switched to the other potential. When the switching of the third differential input buffer output or the switching of the second differential input buffer output is detected, the switching timing delay corresponding to the one potential direction is output to the negative side signal output source. Or a phase comparison means for instructing an early stage.
[0018]
The semiconductor integrated circuit according to the present invention is characterized in that any one of the first to sixth differential output buffers and any one of the first to third differential input buffer blocks are integrated on a semiconductor substrate. To do.
[0019]
The first circuit board of the present invention includes an integrated circuit including any one of the first to sixth differential output buffers and another integrated circuit including any one of the first to third differential input buffer blocks. A circuit and a reference voltage circuit, and outputs each of the positive side output buffer and the negative side output buffer of the integrated circuit as differential signals to the differential input buffer block of the other integrated circuit. The instruction regarding the switching start timing from the differential input buffer block is a delay time control instruction to the differential output buffer.
[0020]
A second circuit board of the present invention includes a first integrated circuit including any one of the second, third, fifth, and sixth differential output buffers, and any one of the first to third differences. 2nd to Nth integrated circuits including a dynamic input buffer block and a reference voltage circuit are mounted, and outputs of the positive side output buffer and the negative side output buffer from the first integrated circuit are supplied to the second to second output circuits, respectively. The differential signal to the N integrated circuit is used, and the instruction regarding the switching start timing of one of the second to Nth integrated circuits is the delay time control instruction to the first integrated circuit. And
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Next, a first embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 5, an example in which the strobe signal is balanced and transmitted between the integrated circuits 1 and 2 will be described.
[0022]
Referring to FIG. 1, differential output buffer 10 has two output buffers 11P and 11N having the same configuration, and outputs two signals of strobe (P) and strobe (N), respectively. Here, P and N mean Positive and Negative, respectively.
[0023]
The input terminal of the output buffer 11N receives a signal obtained by inverting the input signal strobe to the output buffer 11P by the inverter 16, and the two buffers operate in a complementary manner.
[0024]
The output stage of the output buffer 11P is composed of a P-channel transistor 112 and an N-channel transistor 113 that are totem-pole connected, and a variable delay gate 114 and a fixed delay gate 115 are provided in front of this output stage. The fixed delay gate 115 is configured so that the output delay value of the rising waveform can be made negative relative to the falling side by setting the center of the delay time of the variable delay gate.
[0025]
The differential input buffer block 20 includes a differential input buffer 21 having the strobes (P) and (N) as inputs, a differential input buffer 22 having the strobe (P) and the external reference voltage (Vref) 31 as inputs, A differential input buffer 23 to which a strobe (N) and an external reference voltage (Vref) 31 are input and a phase comparator 28 are included.
[0026]
The phase comparator 28 compares the phase of the output of the differential input buffer 21 (P-N signal) with the output of the differential input buffer 22 (P-Vref signal) and the output of the differential input buffer 23 (N-Vref signal). The delay value of the variable delay gate 114 of the output buffers 11P and 11N is automatically adjusted by the comparison result signal.
[0027]
FIG. 2 is a block diagram showing a configuration example of the variable delay gate 114. The variable delay gate 114 is a buffer gate according to the values of a plurality of (for example, eight) buffer gates 1141-1 to 1141-8 and a binary counter 1142 cascaded with a binary counter 1142 of several bits (for example, three bits). It includes a selector 1143 that selects one of the outputs 1141-1 to 1141-8.
[0028]
The binary counter 1142 is reset by an initial clear signal and is incremented if the control data (up instruction) is High at the rising edge of the clock. When the counter value is 0, the buffer gate 1141-1 is selected, and when the counter value is 7, the buffer gate 1141-8 is selected.
[0029]
Although not shown in detail, the fixed delay gate 115 is composed of four buffer gates. Further, as shown in FIG. 3, the fixed output may be drawn from the delay gate near the center of the variable delay gate without providing the fixed delay gate 115 separately.
[0030]
FIG. 4 is a block diagram showing a configuration example of the phase comparator 28. The flip-flops (hereinafter abbreviated as FF) 281 and 285, in which data is set at the rising edge of the timing input, have a delay corresponding to their operation time. Buffers 282 and 286 and inverters 283 and 284 are included.
[0031]
Next, the operation of this embodiment will be described with reference to the drawings. In the present invention, the differential input buffer block 20 side compares the phase difference between the PN signal and the P-Vref signal, and the phase difference between the PN signal and the N-Vref signal, so that the differential output buffer 10 The difference between the cross-point potential of the output strobe (P) and strobe (N) signals and the Vref potential is detected.
[0032]
Next, based on the detected information, the delay times of the variable delay gates 114 of the output buffers 11P and 11N are adjusted, the rising timings of the strobe (P) and the strobe (N) are changed, and finally the PN signal waveform. The cross-point potential is adjusted to the Vref potential.
[0033]
A detailed description will be given along the time chart of FIG. 6 and with reference to FIGS. The differential input buffer 21 receives the strobe (P) and the strobe (N), performs a switching operation at the cross point, and outputs a signal PN. On the other hand, the differential input buffer 22 operates by a cross-point potential between the strobe (P) and Vref, and outputs a P-Vref signal. Similarly, the differential input buffer 23 outputs an N-Vref signal from the strobe (N) and Vref.
[0034]
The phase comparator 28 uses the FF 281 to capture the P-Vref signal value at the rising edge of the PN signal, and as a result, compares the phase between the two signals. That is, when the strobe (P) rises and the cross point between the strobe (P) and the strobe (N) (hereinafter simply referred to as the strobe cross point) is higher than Vref, the P-Vref signal is higher than the PN signal rise. Detection is performed when the rising timing is advanced and FF 281 becomes H.
[0035]
Similarly, the N-Vref signal value is captured by the FF 285 when the PN signal falls (when the strobe (N) rises), and as a result, the phase between the two signals is compared. That is, when the cross point of the strobe is higher than Vref when the PN signal falls, the timing of the rise of the N-Vref signal is earlier than the fall of the PN signal, and the FF 285 becomes H. .
[0036]
As shown in FIG. 6, when the rising operation time (time required for rising) of the strobe (P) is shorter than the falling operation time of the stove (N) but the operation start timing is not later, the cross-point potential is higher than Vref. Get higher. Then, after the P-VREF signal rises, the PN signal rises, and then the N-VREF signal falls.
[0037]
Therefore, the FF 281 is set to High (hereinafter abbreviated as H) at the rise timing of the PN signal, and the control data (P) becomes H, and is input to the variable delay gate 114 of the output buffer 11P in synchronization with the control clock (P). Is done.
[0038]
Conversely, when the cross point of the strobe is lower than Vref, as shown in FIG. 7, the rise of the P-Vref signal comes after the rise of the PN signal, and the FF 281 is set to Low (hereinafter abbreviated as L) to control data. (P) becomes L and is similarly input to the variable delay gate 114.
[0039]
Turning to FIG. 2, if the control data (P) is H at the rising edge of the control clock, the binary counter 1142 of the variable delay gate 114 increments the count value. The counter value is output as a selection signal and input to the selector 1143. When the value of the binary counter 1142 increases by one, the selector 1143 changes so as to select a signal whose data output delay time is one step later.
[0040]
Therefore, when the strobe cross point is higher than Vref, the variable delay gate 114 changes by one step toward the later side, and the rising timing of the output buffer 11P shifts in the later direction, resulting in a lower strobe cross point potential. Adjusted to
[0041]
Returning to the time chart of FIG. 6, at the fall of the strobe (P) signal, when the cross-point potential is higher than the Vref potential, the rise of the N-Vref signal precedes the fall of the PN signal. The FF 285 of the phase comparator 28 in FIG. 4 catches this and is set to H, and the control data (N) becomes H.
[0042]
The variable delay gate 114 of the output buffer 11N receives the control clock (N) and the control data (N) which has become H, increments the internal counter, and the rising timing of the output buffer 11N is shifted in the slow direction. When falling, the cross-point potential of the strobe is adjusted to be lower.
[0043]
In this embodiment, the initial setting of the differential output buffer 10 (reset when the integrated circuit 1 is turned on, etc.) sets the strobe (P), (N) rising timing (ON timing of the transistor 112) to the strobe (N), (P ), The binary counter increment operation is repeated several times, and finally all the cross-point potentials are brought close to the Vref potential. Thereafter, the increment is not performed and the state is maintained. .
[0044]
Next, a second example of the present embodiment will be described with reference to the drawings. FIG. 8 is a block diagram showing the overall configuration of this embodiment. 1 differs from the configuration of FIG. 1 in that the phase comparator 29 sends control data (U) and control data (D) to the differential output buffers 12P and 12N, respectively. Here, U and D mean counting up and down.
[0045]
Further, as shown in FIG. 9, the delay gate 114B has an integrated configuration example in which the fixed output is drawn from the variable delay gate. The binary counter 1142B has UP and DOWN inputs, and increments if the control data (U) is H at the rising edge of the control clock input, and decrements if the control data (D) is H.
[0046]
In the initial clear, “3” corresponding to the fixed output is preset. However, in the manufacturing process of the integrated circuit 1 including the differential output buffer 10A, etc., if the trend of the ON operation time of the transistors 112 and 113 is constant and known, the cross-point potential is close to Vref with respect to the center value “3”. Do not deny presetting pre-corrected values.
[0047]
FIG. 10 is a block diagram showing a detailed configuration of the phase comparator 29. The phase comparator 29 includes RS flip-flops 291, FF292, and 293, AND-OR circuits 294, 295, and 296, inverters 297 and 298, and delay buffers 2991 to 2994.
[0048]
The FF 291 is an FF that receives the PN signal and converts it to FF or latch. The AND-OR circuit 294 is a circuit that creates an internal clock pulse that becomes H for a predetermined time (corresponding to the sum of the operation time of the FF 291 and the delay time of the buffer 2991 or the buffer 2992) at the rise or fall of the PN signal.
[0049]
The FF 292 is an FF that instructs to increment the binary counter 1142B, and is an FF that combines the FF 281 and the FF 282 in terms of control functions. The FF 293 is an FF that instructs decrement similarly when set to Low.
[0050]
The AND-OR circuit 295 selects the P-Vref signal as the data input of the FF 291 when the buffer 2992 is H, that is, from the time before the rise of the PN signal to the predetermined time after the rise, and the buffer 2991 is at the H level. This is a selector that selects the N-Vref signal as the data input of the FF 292 during a period of time, that is, until a predetermined time after the PN signal falls.
[0051]
The AND-OR circuit 296 is a selector that selects the N-Vref signal as the data input of the FF 293 when the buffer 2992 is H, and selects the P-Vref signal as the data input of the FF 291 when the buffer 2991 is H.
[0052]
Next, the operation of the present embodiment will be described with respect to differences from the first embodiment. Referring to FIG. 8, when the strobe rises after the initial setting, in output buffer 12P, N channel transistor 113 is turned off and P channel transistor 112 is turned on. In the output buffer 12N, the P-channel transistor 112 is turned off and the N-channel transistor 113 is turned on.
[0053]
The strobe (P) signal and the strobe (N) signal are transmitted to operate the differential input buffers 21, 22, and 23. The PN signal and the P-Vref signal rise, and the N-Vref signal falls. At this time, as shown in FIG. 6, if the cross-point potential at the differential input buffer 21 is higher than the Vref potential, the P-Vref signal rises, the PN signal rises, and the N-Vref signal falls. In addition, a time difference according to the potential difference is obtained.
[0054]
Referring to FIG. 10, in the phase comparator 29, before the internal clock pulse from the AND-OR circuit 294 becomes H, in the AND-OR circuits 295 and 296, the P-Vref signal which has risen, and the N-Vref which is still in the H state, respectively. The signal is selected, FF292 is set to H at the rising edge of the internal clock, and FF293 is also kept at H. The sum of the operation times of the buffers 2993 and 2994 is set to be slightly larger than the sum of the operation times of the AND-OR circuit 294 and the FF 292. After the control data (U) becomes H and the control data (D) becomes L. The control clock (P) becomes H.
[0055]
Referring to FIG. 9, the delay gate 114B of the output buffer 12P has a control data (U) of H at the rising edge of the control clock (P), so the binary counter 1142B is incremented to “4” and the control timing of the P-channel transistor 112 is reached. Delay one step.
[0056]
If the cross-point potential when the strobe (P) signal falls is also higher than Vref, the N-Vref signal rises, the PN signal falls, and the P-Vref signal falls. In the phase comparator 29, the N-Vref signal and the P-Vref signal are selected as the inputs of the FFs 292 and 293, respectively, become H at the rising edge of the internal clock, and only the control data (U) is set to H and then the control clock (N ). Then, the binary counter 1142B of the delay gate 114B of the output buffer 12N is incremented to “4”, and the control timing of the P-channel transistor 112 is delayed by one step.
[0057]
When the adjustment operation is performed several times, the cross-point potential becomes close to Vref, the time from the rise of the P-Vref signal to the rise of the PN signal, and the time from the rise of the N-Vref signal to the fall of the PN signal. Becomes extremely small. Therefore, in FF292, the setup time of the data input with respect to the rising edge of the internal clock is not satisfied and is not set to H. Therefore, both the control data (U) and the control data (D) remain L, and the value of the binary counter 1142B is also maintained.
[0058]
Next, if the cross-point potential is lower than the Vref potential in the differential input buffer 21 when the strobe (P) signal rises and the strobe (N) signal falls after the initial setting, N The -Vref signal falls, the PN signal rises, and the P-Vref signal rises in this order. In the phase comparator 29 of FIG. 10, the P-Vref signal and the N-Vref signal are selected as the inputs of the FFs 292 and 293, and are set to L, respectively. Therefore, after setting the control data (U) and (D) to L and H, the control clock (P) is started. As a result, the binary counter 1142B of the delay gate 114B of the output buffer 12P is decremented to “2”.
[0059]
If the cross-point potential at the next strobe (N) signal rise is also lower than the Vref potential, the P-Vref signal falls, the PN signal falls, and the N-Vref signal rises in this order as shown in FIG. . The FFs 292 and 293 of the phase comparator 29 are supplied with the N-Vref signal that is still in the L state and the P-Vref signal that has previously become L. Accordingly, both FFs 292 and 293 are set to L, and the binary counter 1142B of the output buffer 12N is decremented at the rising edge of the control clock (N).
[0060]
Also in this case, the cross-point potential becomes close to Vref, and the time from the fall of the N-Vref signal to the rise of the PN signal, and the time from the fall of the P-Vref signal to the fall of the PN signal become extremely short. Accordingly, the setup time of the data input with respect to the rising edge of the internal clock is not satisfied in the FF 293 and the Low is not set, and the binary counter 1142B is also maintained thereafter.
[0061]
Next, a second embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 11, the difference from the first embodiment is that the strobe (P) output and strobe (N) output of the differential output buffer 10B are of the open drain type.
[0062]
The open drain output buffer 13P provides an inverter 116 and a transistor 117 behind the output of the output buffer 11P, and outputs the drain of the transistor 117. The open drain output buffer 13N has the same configuration as the open drain output buffer 13P. Since the P-channel transistor 112 and the N-channel transistor 113 are internally driven, the driving capability may be reduced.
[0063]
Termination resistors 33 and 34 for obtaining an output voltage are connected to the strobe (P) signal and the strobe (N) signal. The receiving side is the differential input buffer block 20 described above.
[0064]
Although not shown, there is an example in which a plurality of differential input buffer blocks 20 are driven. In this case, the adjustment signal (control clock (P), control data (P), control clock (N), control data (N)) to the differential output buffer 10B is received on the receiving differential signal waveform. May be returned from one of the differential input buffer blocks 20 representing the above.
[0065]
Next, a third embodiment of the present invention will be described with reference to the drawings. In this embodiment, each of the two output buffers shown in FIG. 1 is configured as shown in FIG. That is, without changing the gate signals of the P-channel transistor 112 and the N-channel transistor 113, the operation time from the rise of IN (strobe or #strobe) to the fall of the gate signal (output on instruction) can be adjusted. The operation time from the fall of IN to the rise of the gate signal (output off instruction) is fixed (the median value of the operation time).
[0066]
The output buffer 14P creates rising and falling derivatives of the IN signal.
A delay gate (fixed) 119 and an exclusive OR gate 120, AND gates 121 and 122, a variable delay gate 114, a fixed delay gate 115, an RS flip-flop 118, an output stage P-channel transistor 112 and an N-channel transistor 113. The
[0067]
The operation of the output buffer 14P will be described with reference to the time chart of FIG. The exclusive OR signal of the IN signal and its delayed signal (IN ′) becomes the rising and falling differential signal (E) of the IN signal. This signal is gated by IN, and the rising differential signal (A) of IN is output, and the signal gated by IN ′ becomes the falling differential signal (B) of IN.
[0068]
Therefore, when the IN signal rises, the reset pulse to the RS-FF 118 is turned on after a time depending on the delay value of the variable delay gate 114 (the set pulse remains off), and the output (Q) of the RS-FF 118 becomes L and the N channel. The transistor 113 is turned off, the P-channel transistor 112 is turned on, and the output rises.
[0069]
When the IN signal falls, the set pulse to the RS-FF 118 is turned on after a fixed time (the reset pulse remains off), the RS-FF 118 output (Q) becomes H, the P-channel transistor 112 is turned off, and the N-channel transistor 113 Turns on and the output falls.
[0070]
By configuring the output buffers 14P and 14N in this way, it is possible to avoid an increase in the through current that flows instantaneously during the switching operation of the output buffer output stage.
[0071]
Next, FIG. 12B is an example of an open drain output buffer 15P that avoids the increase in the through current, in which the output stage of the output buffer is an open drain transistor 117, and the others are the same as the output buffer 14P. . The operation is similar to this.
[0072]
If a plurality of outputs from the output buffer are not supplied, a transistor in which a drain or a collector is connected to VDD or VCC through a resistor or the like instead of the open drain transistor 117 may be used.
[0073]
Although FIG. 5 shows transmission from the integrated circuit 1 including the differential output buffer to the integrated circuit 2 including the differential input buffer block, the receiving side may be a plurality of integrated circuits. Alternatively, an IC in which a differential output buffer and one or more differential input buffer blocks are integrated on a single integrated circuit substrate may be used.
[0074]
In the examples of the first and second embodiments, the delay gate connected to the P-channel transistor 112 at the output stage of the output buffer is made variable. However, the delay gate on the N-channel transistor 113 side is made variable in the same manner. (The phase difference of the strobe (P) signal and the strobe (N) signal is detected by the phase comparator of the differential input buffer block, and the falling timing is detected in the positive side output buffer and the negative side output buffer. Can be realized by instructing delay / early
[0075]
In the first, second, and third embodiments, the feedback coefficient needs to be optimal so that oscillation does not occur due to the adjustment. For this purpose, the adjustment step of the variable delay gate 114 is made sufficiently small. In addition to the method, there is a method in which a frequency dividing circuit is inserted in the middle of the control clocks (P) and (N) so that the variable delay gate 114 is adjusted only once every n times.
Further, if Vref is varied, the cross point can be set to an optimum value.
[0076]
【The invention's effect】
As described above, according to the present invention, the deviation from the reference potential of the cross-point potential of the differential signal caused by LSI manufacturing variation, circuit configuration, and noise is automatically corrected. Has the effect of avoiding.
[0077]
Further, according to the third embodiment of the present invention, it is possible to automatically correct the deviation of the cross-point potential of the differential signal from the reference potential without increasing the through current during the switching operation of the output buffer output stage.
[0078]
Further, if the reference potential setting supplied to the differential signal receiving side can be adjusted, a wider range of circuit malfunctions can be avoided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall circuit configuration of a first embodiment of the present invention.
2 is a block diagram showing a configuration example of a variable delay gate 114 in FIG.
3 is a block diagram showing a configuration when the variable delay gate 114 and the fixed delay gate 115 of FIG. 1 are combined into a variable delay gate 114A with a fixed delay output.
4 is a block diagram showing a configuration example of a phase comparator 28 in FIG.
FIG. 5 is a diagram showing an overall hardware configuration of the first embodiment of the present invention.
FIG. 6 is a time chart showing the operation and timing of the first embodiment of the present invention when the strobe cross point is higher than Vref.
FIG. 7 is a time chart showing timing when the strobe cross point is lower than Vref in the first embodiment of the present invention;
FIG. 8 is a block diagram showing an overall configuration of a second example of the first embodiment of the present invention.
9 is a block diagram showing the configuration of the delay gate 114B of FIG.
10 is a block diagram showing a detailed configuration of the phase comparator 29 in FIG. 8. FIG.
FIG. 11 is a block diagram showing the overall circuit configuration of a second embodiment of the present invention.
12A is a block diagram showing a configuration of an output buffer 14P according to a third embodiment of the present invention, and FIG. 12B is a block diagram showing a configuration of an open drain output buffer 15P.
FIG. 13 is a time chart showing the operation of the output buffer 14P according to the third embodiment of the present invention.
FIG. 14 is a diagram including an example of transmission between a conventional LSI in a differential format of a positive / negative set.
[Explanation of symbols]
1, 2 Integrated circuit
10, 10A, 10B Differential output buffer
112 P-channel transistor
113 N-channel transistor
114 Variable delay gate
1141-1 to 1141-8 buffer gate
1142, 1142B binary counter
1143 selector
114B delay gate
115 fixed delay gate
116 Inverter
117 Open drain transistor
118 RS flip-flop
119 Delay gate (fixed)
11P, 11N output buffer
120 exclusive OR gate
121 AND gate
12P, 12N output buffer
13P, 13N open drain output buffer
14P output buffer
15P open drain output buffer
16 Inverter
20 Differential input buffer block
21 Differential input buffer
22 Differential input buffer
23 Differential input buffer
28, 29 Phase comparator
31 Reference voltage circuit
33, 34 Termination resistor

Claims (12)

A differential output buffer including a positive side output buffer and a negative side output buffer that outputs a signal having a polarity opposite to the positive side output buffer,
Each of the positive side output buffer and the negative side output buffer includes an output stage in which two transistors whose on / off control levels are reversed to each other are connected to a totem pole, and a variable delay circuit capable of changing a delay time in response to an increase / decrease instruction from the outside. And a fixed delay circuit having a constant delay time,
The positive-side output buffer receives a positive output of a signal to be transmitted, inputs this to the variable delay circuit and the fixed delay circuit, and performs on / off control of one transistor of the output stage with the variable delay circuit output, and is fixed Perform on / off control of the other transistor of the output stage at the delay circuit output,
The negative output buffer receives a negative output of a signal to be transmitted, and performs on / off control of a transistor in an output stage in the same manner as the positive output buffer. In the positive side output buffer and the negative side output buffer, a totem pole output of the output stage is used as an internal output, and a transistor that is on / off controlled by this is provided, and this transistor is used as an output transistor of each buffer. The differential output buffer according to claim 1. In the positive-side output buffer and the negative-side output buffer, instead of providing the fixed delay circuit separately, an output from a predetermined gate in the middle of the delay gate row of the variable delay circuit is set as a fixed delay output, thereby 3. The differential output buffer according to claim 1, wherein on / off of the other transistor of the output stage is controlled. A differential output buffer including a positive side output buffer and a negative side output buffer that outputs a signal having a polarity opposite to the positive side output buffer,
Each of the positive side output buffer and the negative side output buffer includes a circuit for generating a differential output of rising and falling of an input signal, a variable delay circuit capable of changing a delay time in response to an increase / decrease instruction from the outside, and a delay A fixed delay circuit having a constant time; a state memory element that can be set and reset; and an output stage in which two transistors whose on / off control levels are reversed to each other are connected in a totem pole connection. Positive output is input, one output of the differentiation circuit is input to the variable delay circuit, the other output is input to the fixed delay circuit, the state memory element is set and reset by the fixed delay circuit output and the variable delay circuit output, and the state Switch operation of both transistors of the output stage at the output of the storage element,
The differential output buffer, wherein a negative output of a signal to be transmitted is input to the negative side output buffer, and the switching operation of both transistors in the output stage is performed similarly to the positive side output buffer. A differential output buffer including a positive side output buffer and a negative side output buffer that outputs a signal having a polarity opposite to the positive side output buffer,
Each of the positive side output buffer and the negative side output buffer includes a circuit for generating a differential output of rising and falling of an input signal, a variable delay circuit capable of changing a delay time in response to an increase / decrease instruction from the outside, and a delay It has a fixed delay circuit with a constant time, a state memory element that can be set and reset, and an output transistor,
The positive output buffer receives a positive output of a signal to be transmitted, inputs one output of a differentiation circuit to a variable delay circuit, and inputs the other output to a fixed delay circuit, and is in a state of a fixed delay circuit output and a variable delay circuit output. The memory element is set, reset, and the output transistor is switched by the output of the state memory element. The negative output buffer receives the negative output of the signal to be transmitted, and the output transistor switches in the same way as the positive output buffer. A differential output buffer characterized by performing an operation. The variable delay circuit of the positive side output buffer and the negative side output buffer includes a gate row in which a plurality of gates are cascade-connected, a counter that increases or decreases a value by an increase / decrease instruction from the outside, and each gate output of the gate row The differential output buffer according to claim 1, further comprising: a selector that selects an output according to the counter value. A first differential input buffer for inputting a differential signal composed of a positive side signal and a negative side signal;
A second differential input buffer having a positive signal of the differential signal and a reference voltage supplied from the outside as inputs;
A third differential input buffer having the negative signal of the differential signal and the reference voltage as inputs;
Switching timing of the second differential input buffer output when the second differential input buffer output and the third differential input buffer output are switched in a predetermined level direction of high / low levels. If there is a time difference between the switching timings of the output of the third differential input buffer and the output of the signal on the side of switching to the predetermined level direction of the differential signal, depending on the context, the output source of the signal A differential input buffer block comprising: phase comparison means for instructing to delay or accelerate the switching timing in a predetermined direction. A first differential input buffer for inputting a differential signal composed of a positive side signal and a negative side signal;
A second differential input buffer having a positive signal of the differential signal and a reference voltage supplied from the outside as inputs;
A third differential input buffer having the negative signal of the differential signal and the reference voltage as inputs;
When it is detected that the second differential input buffer output is switched in advance when the first differential input buffer output is switched in the direction of one potential, the one of the positive side signals is output to the first differential input buffer output. Instructing a delay of the switching start timing corresponding to the potential direction, and detecting that the third differential input buffer output is switched first when the first differential input buffer output is switched to the other potential. Phase comparison means for instructing the output source of the negative side signal to delay the switching timing corresponding to the one potential direction,
A differential input buffer block comprising: A first differential input buffer for inputting a differential signal composed of a positive side signal and a negative side signal;
A second differential input buffer having a positive signal of the differential signal and a reference voltage supplied from the outside as inputs;
A third differential input buffer having the negative signal of the differential signal and the reference voltage as inputs;
When the switching of the second differential input buffer output or the switching of the third differential input buffer output preceding the switching of the first differential input buffer output in the direction of one potential is detected, Instructing the output source of the positive side signal to delay or speed up the switching timing corresponding to the one potential direction, the first differential input buffer output precedes when the output of the first differential input buffer is switched to the other potential. When the switching of the differential input buffer output of 3 or the switching of the second differential input buffer output is detected, a delay of switching timing corresponding to the one potential direction or an early stage is output to the negative side signal output source. Phase comparison means for instructing
A differential input buffer block comprising: 9. A semiconductor integrated circuit comprising the differential output buffer according to claim 1 and the differential input buffer block according to claim 7, 8 or 9 integrated on a semiconductor substrate. An integrated circuit including the differential output buffer according to any one of claims 1 to 6, another integrated circuit including the differential input buffer block according to claim 7, 8, or 9, and a reference voltage circuit are mounted. And
Each output of the positive side output buffer and the negative side output buffer of the integrated circuit is used as a differential signal to the differential input buffer block of the other integrated circuit, and the switching start timing from the differential input buffer block of the other integrated circuit is related to A circuit board characterized in that the instruction is a delay time control instruction to a differential output buffer. A first integrated circuit including the differential output buffer according to claim 2, 3, 5, or 6, and a second to Nth integrated circuit including the differential input buffer block according to claim 7, 8, or 9. A circuit and a reference voltage circuit, and outputs each of the positive side output buffer and the negative side output buffer from the first integrated circuit as differential signals to the second to Nth integrated circuits, and 2. A circuit board characterized in that an instruction relating to a switching start timing of one of the 2nd to Nth integrated circuits is a delay time control instruction to the first integrated circuit.

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