JP2021077926A - Semiconductor device and operation method for the same - Google Patents

Abstract

To suppress the influence from a process, temperature, and voltage about a waveform characteristic output from a differential output circuit.SOLUTION: A semiconductor device includes a first output circuit that outputs a first signal included in a differential output signal, a first circuit that controls the output waveform of the first output circuit, a second output circuit that outputs a second signal included in the differential output signal, a second circuit that controls the output waveform of the second output circuit, a first comparator that outputs a first status signal expressing whether the first signal is in a predetermined voltage range, a second comparator that outputs a second status signal expressing whether the second signal is in the predetermined voltage range, and an adjustment control circuit that receives the first status signal and the second status signal. The adjustment control circuit controls the first and second circuits on the basis of the first status signal and the second status signal.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device and its operation method, and relates to a semiconductor device having a built-in differential output such as a USB (Universal Serial Bus) driver and its operation method.

In personal computers and the like, the USB interface, which is an interface standard capable of connecting various peripheral devices such as a keyboard, mouse, or printer with a common connector, has become widespread. For this reason, some semiconductor devices such as microcomputers and SoCs (System on Chips) incorporated in electronic devices are provided with a differential output driver.

The USB interface requires a USB transceiver that transmits and receives data at high speed, and the USB transceiver is composed of a differential driver, a differential receiver, and the like.

To support different transfer rates, USB differential drivers include the USB Full Speed driver and the Low Speed driver. These USB differential drivers are equipped with differential output terminals DP (D +) and DM (D-), but with respect to the differential output terminals DP and DM, the cross voltage point, signal rise time and fall time (slew rate). Waveform characteristics such as rate) and slew rate ratio matching are standardized. The standards for these waveform characteristics are very strict, and every time the manufacturing process of a semiconductor device changes, it is necessary to adjust the design of the differential driver so as to satisfy the standards for the waveform characteristics.

Specifically, since the differential driver is an analog circuit and the waveform transition is performed by the reference current and the feedback capacitance, the waveform characteristics of the differential signal output by the differential driver depend on the process, temperature, and voltage. There is a problem of variation. Further, there is a problem that the element size of the reference current circuit becomes large in order to suppress the variation in the waveform characteristics, and the design difficulty becomes high.

Patent Document 1 discloses a technique including a threshold compensation transistor in addition to a basic differential driver circuit configuration. According to Patent Document 1, it is possible to suppress variations in the crossover voltage and variations in the slew rate.

Japanese Unexamined Patent Publication No. 2003-309460

However, the differential driver according to Patent Document 1 has a problem that it is not possible to suppress variations in constant current and variations in feedback capacitance. There is also a problem that it is not possible to suppress variations including the influence of temperature and voltage dependence.

An object of the embodiment is to suppress the influence of the process, temperature, and voltage on the waveform characteristics output by the differential output circuit. Other issues and novel features will become apparent from the description herein and the description in the drawings.

The semiconductor device according to the embodiment is differential between a first output circuit that outputs a first signal included in the differential output signal, a first circuit that controls the output waveform of the first output circuit, and the like. Whether the second output circuit that outputs the second signal included in the output signal, the second circuit that controls the output waveform of the second output circuit, and the first signal are in a predetermined voltage range. A first comparator that outputs a first status signal indicating whether or not, and a second comparator that outputs a second status signal indicating whether or not the second signal is in the predetermined voltage range. , The adjustment control circuit for receiving the first status signal and the second status signal is provided, and the adjustment control circuit has the first and second status signals based on the first status signal and the second status signal. Control the circuit of.

The method of operating the semiconductor device according to another embodiment includes the first and second output circuits, the first and second circuits, the first and second comparators, and the first and second counters. A method of operating the semiconductor device provided, the step of outputting the first signal included in the differential output signal, the step of controlling the output waveform of the first output circuit by the first circuit, and the differential. The first signal is predetermined by the step of outputting the second signal included in the output signal, the step of controlling the output waveform of the second output circuit by the second circuit, and the first comparator. A step of outputting a first status signal indicating whether or not it is in the voltage range, and a second status signal indicating whether or not the second signal is in a predetermined voltage range are generated by the second comparator. The output step, the step of counting based on the first status signal by the first counter, the step of counting based on the second status signal by the second counter, and the first and second steps. It has a step of controlling the first and second circuits based on the count value of the counter of.

According to one embodiment, the influence of the process, temperature, and voltage on the waveform characteristics output by the differential output driver can be suppressed.

FIG. 1 is a block diagram showing a configuration example of the semiconductor device according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of the differential output circuit according to the first embodiment. FIG. 3 is a block diagram showing a configuration example of the counting unit according to the first embodiment. FIG. 4 is a diagram showing an example of the output waveform of the output driver according to the first embodiment. FIG. 5 is a block diagram showing a configuration example of the driver circuit according to the first embodiment. FIG. 6 is a flowchart showing an operation flow of the differential output circuit according to the first embodiment. FIG. 7 is a block diagram showing a configuration example of the differential output circuit according to the second embodiment. FIG. 8 is a block diagram showing a configuration example of the counting unit according to the second embodiment. FIG. 9 is a block diagram showing a configuration example of the delay adjustment circuit according to the second embodiment. FIG. 10 is a timing chart showing an operation example of the delay adjustment circuit according to the second embodiment. FIG. 11 is a block diagram showing a configuration example of the output driver according to the second embodiment. FIG. 12 is a diagram showing an example of the output waveform of the output driver according to the second embodiment. FIG. 13 is a flowchart showing an operation flow of the differential output circuit according to the second embodiment. FIG. 14 is a block diagram showing a configuration example of the differential output circuit according to the third embodiment. FIG. 15 is a timing chart showing an example of the differential output signal output by the differential output circuit according to the third embodiment. FIG. 16 is a flowchart showing an operation flow of the differential output circuit according to the third embodiment. FIG. 17 is a block diagram showing a configuration example of the differential output circuit according to the fourth embodiment. FIG. 18 is a timing chart showing an example of the differential output signal output by the differential output circuit according to the fourth embodiment.

In order to clarify the explanation, the following description and drawings have been omitted or simplified as appropriate. Further, in each drawing, the same elements are designated by the same reference numerals, and duplicate explanations are omitted as necessary.

[Embodiment 1]
FIG. 1 is a block diagram showing a configuration example of the semiconductor device 1 according to the first embodiment. FIG. 1 shows a peripheral device 9 that communicates with the host computer 90 by a USB interface. The peripheral device 9 includes a semiconductor device 1. As shown in FIG. 1, the semiconductor device 1 includes a CPU (Central Processing Unit) 2, a ROM (Read Only Memory) 3, a RAM (Random Access Memory) 4, a logic circuit 5, a USB transceiver 6, and the like. A differential output circuit 7 is provided.

The CPU 2 reads the program stored in the ROM 3 and performs various operations. The ROM 3 is a storage device for storing a program executed by the CPU 2. The RAM 4 is, for example, a storage device for storing the result of the calculation executed by the CPU 2. The logic circuit 5 includes various processing circuits such as an interrupt controller. The USB transceiver 6 is an interface for connecting the host computer 90 and the peripheral device 9 via a common connector. The USB transceiver 6 includes a differential output circuit 7. The differential output circuit 7 outputs a differential output signal from the differential output terminals DP and DM of the semiconductor device 1.

FIG. 2 is a block diagram showing a configuration example of the differential output circuit 7 according to the first embodiment. The differential output circuit 7 includes a driver circuit 11, a driver circuit 12, a driver control circuit 13, a reference current generation circuit 14, comparators 20 and 21, and an adjustment control circuit 30.

The driver circuit 11 and the driver circuit 12 are driver circuits for outputting signals to the differential output terminals DP and DM, respectively. The driver circuit 11 drives the differential output terminal DP. The driver circuit 12 drives the differential output terminal DM.

The driver control circuit 13 is a control circuit that receives a data signal and an enable signal from the USB transceiver 6 and generates signals PEN_DP, NEN_DP, PEN_DM, and NEN_DM for controlling the driver circuits 11 and 12.

The reference current generation circuit 14 is a circuit that generates a reference current for adjusting the output waveforms of the driver circuit 11 and the driver circuit 12.

The comparator (first comparator) 20 is a voltage comparison circuit that compares the voltage of the differential output signal output to the differential output terminal DP with the reference voltage and outputs the status signal (first status signal) DP_COMP. is there. In other words, the comparator 20 is a circuit that outputs a status signal indicating whether or not the differential output signal output to the differential output terminal DP is within a predetermined voltage range. Similarly, the comparator (second comparator) 21 compares the voltage of the differential output signal output to the differential output terminal DM with the reference voltage, and outputs the status signal (second status signal) DM_COMP. It is a comparison circuit. In other words, the comparator 21 is a circuit that outputs a status signal indicating whether or not the differential output signal output to the differential output terminal DM is within a predetermined voltage range.

More specifically, in the comparator 20, when the voltage of the differential output terminal DP is equal to or higher than the reference voltage VREF1 and lower than or equal to VREF2, the status signal DP_COMP is, for example, High Level (hereinafter, also referred to as “H level”). Output a signal. On the other hand, when the voltage of the differential output terminal DP is smaller than the reference voltage VREF1 or larger than VREF2, a signal of, for example, Low Level (hereinafter, also referred to as “L level”) is output as the status signal DP_COMP. Similarly, the comparator 21 outputs, for example, H as the status signal DM_COMP when the voltage of the differential output terminal DM is the reference voltage VREF1 or more and VREF2 or less. On the other hand, when the voltage of the differential output terminal DM is smaller than the reference voltage VREF1 or larger than VREF2, for example, L is output as the status signal DM_COMP.

Hereinafter, the period during which the comparator 20 outputs the H level as the status signal DP_COMP and the period during which the comparator 21 outputs the H level as the status signal DM_COMP are referred to as slew rate times.

The adjustment control circuit 30 includes a counting unit 31 and a control circuit 34. The adjustment control circuit 30 is a control circuit for generating control signals SLEW_DP and SLEW_DM for adjusting the slew rate of the driver circuit 11 and the driver circuit 12 from the slew rate time monitored by the comparator 20 and the comparator 21. The control signals SLEW_DP and SLEW_DM for adjusting the slew rate are signals for controlling the constant current circuit provided in the driver circuit 11 and the driver circuit 12 in order to change the slew rate, respectively. The adjustment control circuit 30 outputs the control signals SLEW_DP and SLEW_DM based on the count values of the counter 32 and the counter 33.

The counting unit 31 includes a counter (first counter) 32 and a counter (second counter) 33. The counter 32 is a circuit for counting the time when the status signal DP_COMP output by the comparator 20 is at the H level and converting the slew rate time into a digital value. Similarly, the counter 33 is a circuit for counting the time when the status signal DM_COMP output by the comparator 21 is at the H level and converting the slew rate time into a digital value.

The control circuit 34 generates control signals SLEW_DP and SLEW_DM for adjusting the slew rate based on the count value (first count value) indicated by the counter 32 and the count value (second count value) indicated by the counter 33. It is a circuit to do. The control circuit 34 includes a threshold value setting register (not shown) that stores a threshold value that is acceptable as a value indicated by the counter 32 and the counter 33.

FIG. 3 is a block diagram showing a configuration example of the counting unit according to the first embodiment. The counting unit 31 includes ring oscillators (ROSC) 313 and 314, and counters 32 and 33.

The ring oscillators 313 and 314 are clock generation circuits that generate clocks supplied to the counters 32 and 33.

The counter 32 is a circuit that performs a counting operation based on the clock generated by the ring oscillator 313 and the status signal DP_COMP. For example, the ring oscillator 313 generates a clock while the status signal DP_COMP is at H level. The counter 32 counts up with the clock generated by the ring oscillator 313. Further, the counter 33 is a circuit that performs a counting operation based on the clock generated by the ring oscillator 314 and the status signal DM_COMP. For example, the ring oscillator 314 generates a clock during the period when the status signal DM_COMP is at H level. The counter 33 counts up with the clock generated by the ring oscillator 314. The configuration of the counting unit 31 is not limited to this. For example, the counters 32 and 33 may be configured to perform a count-up operation during the period when DP_COMP and DM_COMP are H levels, respectively, based on the clock generated from the common clock generation circuit.

FIG. 4 is a diagram showing an example of the waveform of the differential output signal output by the differential output circuit 7 according to the first embodiment. The comparator 20 can detect the point where the voltage of the differential output terminal DP intersects the reference voltages VREF1 and VREF2. FIG. 4 shows an example in which VREF1 is a voltage of 10% of the power supply voltage VDD and VREF2 is a voltage of 90% of the power supply voltage VDD, but the values of VREF1 and VREF2 are not limited to this. The values of VREF1 and VREF2 can be arbitrarily determined within the range to be adjusted according to the standard or the like. As shown in FIG. 4, the status signal DP_COMP becomes H level in the section where the voltage of the differential output terminal DP is VREF1 or more and VREF2 or less. Similarly, the DM_COMP signal becomes H level in the section where the voltage of the DM terminal is VREF1 or more and VREF2 or less.

FIG. 5 is a circuit diagram showing a configuration example of the driver circuit 11 according to the first embodiment. Although the configuration example of the driver circuit 11 is shown in the figure, the configuration of the driver circuit 12 is the same. The driver circuit 11 includes MP1 and MP2 which are P-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) for driving an external terminal PAD, MN1 and MN2 which are N-type MOSFETs, feedback capacitance elements C1 and C2, and resistors. It includes R1 and a resistor R2, a CMOS inverter INVP, a CMOS inverter INVN, a constant current circuit 110, and a constant current circuit 111. The configuration of the driver circuits 11 and 12 is not limited to the configuration example of FIG. 5, and for example, the resistors R1 and R2 may be replaced with wiring. Since the resistor R1 is inserted for protection against ESD (Electro-Static Discharge), the driver circuits 11 and 12 may be provided with simple wiring instead of the resistor R1. Further, since the resistor R2 is inserted for capacity adjustment of the N-type MOSFET MN2, the driver circuits 11 and 12 may be provided with simple wiring instead of the resistor R2. If the resistor R2 is replaced by wiring, the transistor size of the MN2 is adjusted. In the following, a configuration example of the driver circuits 11 and 12 will be described with reference to FIG. 5 in which the driver circuits 11 and 12 include resistors R1 and R2.

The PAD of FIG. 5 is the differential output terminal DP or DM of FIG.

MP1 and MN1 are MOSFETs that drive the external terminal PAD. As shown in FIG. 5, the MP2, the feedback capacitance element C1, the feedback capacitance element C2, the resistor R2, and the MN2 are connected in series. The source of MP2 is connected to the VCSQ and the drain is connected to the feedback capacitance element C1. The other end of the feedback capacitance element C1 is connected to the feedback capacitance element C2. The other end of the feedback capacitance element C2 is connected to the resistor R2. The other end of the resistor R2 is connected to the drain of the MN2. The source of MN2 is connected to VSSQ. The connection node of the feedback capacitance element C1 and the feedback capacitance element C2 is connected to the resistor R1, and the other end of the resistor R1 is connected to the external terminal PAD, the drain of the MP1 and the drain of the MN1.

The feedback capacitive element C1 is a capacitive element for controlling the speed at which MP1 which is a P-type MOSFET is turned ON or OFF. The driver circuit 11 includes a first capacitive element as the feedback capacitive element C1. Further, the driver circuit 12 includes a third capacitance element as the feedback capacitance element C1. Similarly, the feedback capacitive element C2 is a capacitive element for controlling the speed at which the N-type MOSFET MN1 is turned ON or OFF. The driver circuit 11 includes a second capacitive element as the feedback capacitive element C2. Further, the driver circuit 12 includes a fourth capacitance element as the feedback capacitance element C2.

The CMOS inverter INVP includes MP3 which is a P-type MOSFET and MN3 which is an N-type MOSFET. The output of the CMOS inverter INVP is connected to the drain of the MP2, the feedback capacitance element C1, and the gate of the MP1. Further, the CMOS inverter INVN includes MP4 which is a P-type MOSFET and MN4 which is an N-type MOSFET. The output of the CMOS inverter INVN is connected to the feedback capacitance element C2, the resistor R2, and the gate of the MN1.

The constant current circuit 110 is a constant current circuit having a current mirror configuration. A plurality of P-type MOSFETs 113 are provided on the mirror side of the constant current circuit 110. The driver circuit 11 controls the number of P-type MOSFETs to be turned on among the plurality of P-type MOSFETs 113 based on the control signal SLEW_DP, and adjusts the amount of current flowing through the constant current circuit 110. As a result, the driver circuit 11 can control the charge / discharge time of the feedback capacitance element C2 by the constant current circuit 110.

The constant current circuit 111 is a constant current circuit having a current mirror configuration. A plurality of N-type MOSFETs 114 are provided on the mirror side of the constant current circuit 111. The driver circuit 11 controls the number of N-type MOSFETs to be turned on among the plurality of N-type MOSFETs 114 based on the control signal SLEW_DM, and adjusts the amount of current flowing through the constant current circuit 111. As a result, the driver circuit 11 can control the charge / discharge time of the feedback capacitance element C1 by the constant current circuit 111.

The driver circuit (first driver circuit) 11 includes a first constant current circuit as the constant current circuit 110. Further, the driver circuit (first driver circuit) 11 includes a second constant current circuit as the constant current circuit 111. Similarly, the driver circuit (second driver circuit) 12 includes a third constant current circuit as the constant current circuit 110. Further, the driver circuit (second driver circuit) 12 includes a fourth constant current circuit as the constant current circuit 111.

The driver circuit 11 controls the ratio of the current mirrors based on SLEW_DP and SLEW_DM to adjust the reference current. As a result, the time required for charging and discharging the feedback capacitance elements C1 and C2 changes. Therefore, the differential output circuit 7 can adjust the slew rate of the driver circuit 11 and the driver circuit 12 and the cross point of the differential output. In other words, the driver circuit 11 and the driver circuit 12 can control the slew rates of the differential output terminals DP and DM via the time constants of the reference current and the feedback capacitance.

The principle of adjusting the slew rate will be further described with reference to FIG. To adjust the rising side of the slew rate of the driver circuit 11 and the driver circuit 12, the current mirror ratio of the constant current circuit 111 is changed. As a result, the discharge time of the feedback capacitance element C1 changes, so that the rise time Tr can be adjusted. More specifically, when the number of transistors to be turned on is increased for the plurality of N-type MOSFETs 114, the amount of current flowing through the plurality of N-type MOSFETs 114 driven by the constant current circuit 111 increases. Therefore, the feedback capacitance element C1 is discharged more quickly. Therefore, MP1 which is a P-type MOSFET also turns on more quickly. Therefore, the voltage of the PAD changes to VCSQ more quickly. As a result, the signal waveform output by the driver circuit 11 rises more steeply. On the other hand, when the number of transistors to be turned on is reduced for the plurality of N-type MOSFETs 114, the amount of current flowing through the plurality of N-type MOSFETs 114 driven by the constant current circuit 111 is reduced. Therefore, the feedback capacitance element C1 is discharged more slowly, and the time until the P-type MOSFET MP1 is turned on is also delayed. Therefore, since the voltage of the PAD changes to the VCSQ more slowly, the signal waveform output by the driver circuit 11 rises more slowly.

Next, in order to adjust the falling side of the slew rate of the driver circuit 11 and the driver circuit 12, the current mirror ratio of the constant current circuit 110 is changed. As a result, the charging time of the feedback capacitance element C2 changes, so that the fall-down time Tf can be adjusted. More specifically, when the number of transistors to be turned on is increased for the plurality of P-type MOSFETs 113, the amount of current flowing through the plurality of P-type MOSFETs 113 driven by the constant current circuit 110 increases. Therefore, the feedback capacitance element C2 is charged more quickly. Therefore, the MN1 which is an N-type MOSFET also turns on more quickly. Therefore, the voltage of the PAD changes to VSSQ more quickly. As a result, the signal waveform output by the driver circuit 11 falls sharper. On the other hand, when the number of transistors to be turned on is reduced for the plurality of P-type MOSFETs 113, the amount of current flowing through the plurality of P-type MOSFETs 113 driven by the constant current circuit 110 is reduced. Therefore, the feedback capacitance element C2 is charged more slowly. Therefore, the time until the MN1 which is an N-type MOSFET is turned on is also delayed. Therefore, the voltage of the PAD changes to VSSQ more slowly. As a result, the signal waveforms output by the driver circuit 11 and the driver circuit 12 fall more slowly.

(motion)
FIG. 6 is a flowchart showing an operation flow of the differential output circuit 7 according to the first embodiment. As described above, the control circuit 34 includes a threshold value setting register that stores a threshold value that is acceptable as a value indicated by the counter 32 and the counter 33. Prior to the operation of the differential output circuit 7, for example, the CPU 2 executes an initialization routine to set a threshold value allowed as a difference between the counter 32 and the counter 33 in the threshold value setting register.

When the differential output circuit 7 starts operating, the differential output circuit 7 transmits a differential output signal from the differential output terminals DP and DM (step S101). When the transmission of the differential output signal by the differential output circuit 7 is started, the comparator 20 compares the voltage of the signal output to the differential output terminal DP with the reference voltages VREF1 and VREF2, and outputs the status signal DP_COMP. To do. Similarly, the comparator 21 compares the voltage of the signal output to the differential output terminal DM with the reference voltages VREF1 and VREF2, and outputs the status signal DM_COMP. The counter 32 executes a slew rate count for monitoring the slew rate of the DP terminal based on the status signal DP_COMP (step S102). Similarly, the counter 33 executes a slew rate count for monitoring the slew rate of the DM terminal based on the status signal DM_COMP (step S102).

Subsequently, the control circuit 34 determines whether or not the values of the counter 32 and the counter 33 are within the predetermined threshold values. When the value of either the counter 32 or the counter 33 is not within the threshold value (step S103: NO), does the control circuit 34 adjust the slew rate of the driver circuit 11 by the control signal SLEW_DP for slew rate adjustment? , The slew rate of the driver circuit 12 is adjusted by the control signal SLEW_DM (step S104). More specifically, when the value of the counter 32 or the counter 33 is smaller than the predetermined threshold value, it indicates that the slew rate is small and the signal waveform is steeper. Therefore, adjust so that the rising or falling edges of the waveform are blunted. On the other hand, when the value of the counter 32 or the counter 33 is larger than the predetermined threshold value, it indicates that the slew rate is large and the signal waveform changes slowly. Therefore, the signal is adjusted to change more steeply. The control circuit 34 adjusts the slew rate for both the differential output terminals DP and DM.

In step S103, when the values of the counter 32 and the counter 33 are both within the threshold value (step S103: YES), the control circuit 34 compares the value of the counter 32 with the value of the counter 33 (step S105). Hereinafter, the value indicated by the counter 32 is referred to as CNTDP. Similarly, the value indicated by the counter 33 is called CNTDN. When CNTDP and CNTDM are equal (step S105: YES), the differential output circuit 7 ends the slew rate adjustment of the differential output signal. On the other hand, when the CNTDP and the CNTDM do not match (step S105: NO), the control circuit 34 determines whether or not the CNTDP is smaller than the CNTDM (step S106). When the CNTDP is smaller than the CNTDM (step S106: YES), the control circuit 34 adjusts the slew rate of the differential output terminal DP to be blunted by the control signal SLEW_DP (step S107). On the other hand, when the CNTDP is CNTDM or more (step S106: NO), the control circuit 34 adjusts the slew rate of the differential output terminal DM by the control signal SLEW_DM (step S108).

The driver circuits 11 and 12 control the slew rate with a reference current amount. That is, when the reference current amount is large, the slew rate is adjusted to be steeper, and when the reference current amount is small, the slew rate is adjusted to be gradual. For example, the control signals SLEW_DP and SLEW_DM for slew rate adjustment are determined based on a prepared table for associating the counter value with the fluctuation amount of the slew rate and the values of CNTDP and CNTDM.

Adjusting the difference between the slew rate of the differential output terminal DP and the slew rate of the differential output terminal DM is more advantageous in terms of power consumption if the slew rate is adjusted in a direction that makes the slew rate dull, and EMI (ElectroMagnetic Interference). ) Is also superior due to its low noise. However, whether the slew rate is adjusted by blunting or the slew rate is adjusted by steepness may change depending on factors such as the interface standard.

(effect)
The differential output circuit 7 according to the first embodiment includes driver circuits 11 and 12 including constant current circuits 110 and 111 for controlling the slew rate of the output circuit 112, comparators 20 and 21, and a control circuit 34. To be equipped. The control circuit 34 adjusts the amount of current driven by the constant current circuits of the driver circuits 11 and 12 based on the status signals COMP_DP and COMP_DM output by the comparators 20 and 21, and outputs them to the differential output terminals DP and DM. Adjust the through rate of the signal waveform. Therefore, it is possible to prevent the electrical characteristics of the differential output signal from fluctuating due to manufacturing variations, voltage, or temperature. Further, in the semiconductor device 1 according to the first embodiment, the adjustment control circuit 30 automatically adjusts the through rate of the differential output signals output from the differential output terminals DP and DM, so that the differential output signal The design of the driver circuit becomes easy, and the chip area can be reduced by reducing the element size.

[Modified Example of Embodiment 1]
In the semiconductor device 1 according to the first embodiment, after the semiconductor device 1 is started, the control circuit 34 generates control signals SLEW_DP and SLEW_DM based on the values of the counters 32 and 33, thereby passing through the differential output signal. I was adjusting the rate. However, the slew rate can be adjusted with a tester at the time of the shipment test of the semiconductor device 1 to determine the optimum SLEW_DP and SLEW_DM. Therefore, the semiconductor device 1 may be shipped after fixing the values of the control signals SLEW_DP and SLEW_DM to the values determined at the time of the shipping test. For example, by writing a signal value to a non-volatile memory (not shown) built in the semiconductor device 1, the values of SLEW_DP and SLEW_DM can be fixed to the values determined before shipment. However, in the semiconductor device 1 according to the modified example of the first embodiment, only the slew rate fluctuation related to the influence of the process can be adjusted at the time of the test. Apart from this, it is also possible to use the automatic adjustment function of the slew rate by the adjustment control circuit 30 every time the semiconductor device 1 operates. In this case, the fluctuation of the electrical characteristics according to the voltage or temperature can also be adjusted by the adjustment control circuit 30.

(effect)
According to the semiconductor device 1 according to the modified example of the first embodiment, the values of the control signals SLEW_DP and SLEW_DM output by the adjustment control circuit 30 are fixed to the values determined before shipment. Therefore, it is not necessary to adjust the slew rate fluctuation related to the influence of the process each time the differential output circuit 7 starts operating. Therefore, according to the modification of the first embodiment, the electrical characteristics of the differential output signal can be more easily satisfied than that of the first embodiment.

[Embodiment 2]
Next, the second embodiment will be described. FIG. 7 is a block diagram showing a configuration example of the differential output circuit 7A according to the second embodiment. The differential output circuit 7A according to the second embodiment includes delay adjusting circuits 22 and 23 as compared with the differential output circuit 7 according to the first embodiment, and the comparator 20A and the comparator 20A instead of the comparators 20 and 21. The point that 21A is provided, the point that the adjustment control circuit 30A is provided instead of the adjustment control circuit 30, and the point that the driver circuits 11A and 12A are provided instead of the driver circuits 11 and 12 are different. Since the other configurations and operations are the same as those of the semiconductor device 1 described in the first embodiment, the same configurations are designated by the same reference numerals, and duplicate description will be omitted.

The differential output circuit 7 according to the first embodiment adjusts the slew rate, but the differential output circuit 7A according to the second embodiment adjusts the cross point.

The comparator 20A is a voltage comparison circuit that outputs an H level as a status signal DP_COMP when the voltage of the differential output terminal DP is equal to or higher than the reference voltage VREF3. Similarly, the comparator 21A is a voltage comparison circuit that outputs an H level as a status signal DM_COMP when the voltage of the differential output terminal DM is equal to or higher than the reference voltage VREF3.

The adjustment control circuit 30A includes a counting unit 31A and a control circuit 34A. The adjustment control circuit 30A adjusts the delay times of the delay adjustment circuits 22 and 23 based on the delay time difference detected as the difference between the count value of the counter 32 and the count value of the counter 33. That is, the adjustment control circuit 30A adjusts the delay times of the delay adjustment circuits 22 and 23 by the control signals DELAY_DP and DELAY_DM. In other words, the adjustment control circuit 30A has a delay time difference between the rising edge of the output waveform of the driver circuit 11 and the falling edge of the output waveform of the driver circuit 12, or the falling edge of the output waveform of the driver circuit 11 and the falling edge of the driver circuit 12. The delay time difference from the rising edge of the output waveform is detected based on the respective count values output by the counter 32 and the counter 33.

The counter 32 is a circuit that detects that the DP_COMP signal is at the H level and performs a counting operation. Similarly, the counter 33 is a circuit that detects that the DM_COMP signal is at the H level and performs a counting operation. The details of the configuration of the counter unit 31A will be described later with reference to FIG.

The control circuit 34A is a circuit for generating control signals DELAY_DP and DELAY_DM for adjusting the delay times of the delay adjustment circuits 22 and 23 based on the values indicated by the counter 32 and the counter 33. The control circuit 34A includes a register (not shown) for storing in advance an acceptable threshold value as a difference between the counters 32 and 33. The control circuit 34A can be configured as, for example, a CPU or a decoder. When the control circuit 34A is configured as a decoder, the values of the counter 32 and the counter 33 are decoded to generate the control signals DELAY_DP and DELAY_DM. When the control circuit 34A is composed of a CPU (for example, CPU 2), the CPU calculates values to be output to the control signals DELAY_DP and DELAY_DM based on the count values of the counter 32 and the counter 33. The CPU writes a predetermined value to a register (not shown) for outputting DELAY_DP and DELAY_DM based on the calculated value to be output.

The delay adjustment circuit (first delay control circuit) 22 is a circuit for changing the delay amount of the data line based on the control signal DELAY_DP. Similarly, the delay adjustment circuit (second delay control circuit) 23 is a circuit for changing the delay amount of the data line based on the control signal DELAY_DM. In this way, the adjustment control circuit 30A can adjust the delay amount of the data output to the differential output terminals DP and DM by controlling the control signals DELAY_DP and DELAY_DM. Details of the delay adjusting circuits 22 and 23 will be described later with reference to FIGS. 9 and 10.

FIG. 8 is a block diagram showing a configuration example of the counting unit 31A according to the second embodiment. The counting unit 31A includes an XOR circuit 310, AND circuits 311 and 312, ring oscillators (ROSC) 313 and 314, and counters 32 and 33. The XOR circuit 310 is a circuit that takes an XOR of DP_COMP and DM_COMP. The output signal of the XOR circuit 310 is input to the AND circuits 311 and 312. The AND circuit 311 has a function of propagating the output of the XOR circuit 310 to the ring oscillator 313 only when the DP_COMP signal is at the H level. Further, the AND circuit 312 has a function of propagating the output of the XOR circuit 310 to the ring oscillator 314 only when the DM_COMP signal is at the H level. The clock signal DP_CN output by the ring oscillator 313 is input to the counter 32. The clock signal DM_CN output by the ring oscillator 314 is input to the counter 33.

The timing chart at the lower left of FIG. 8 shows the waveform when the DP rises and the DM falls. If the change on the DP side is fast, a clock pulse is output to DP_CN from the rise of DP to the fall of DM. On the other hand, no clock pulse is output to the clock signal DM_CN. The timing chart at the lower right of FIG. 8 shows the waveform when the DP falls and the DM rises. If the DP changes quickly, no clock pulse is output to the clock signal DP_CN. On the other hand, a clock pulse is output to the clock signal DM_CN from the fall of DP to the rise of DM.

FIG. 8 shows a configuration example in which the counting unit 31A includes the ring oscillators 313 and 314, but the configuration example of the counting unit 31A is not limited to this. The counting unit 31 may receive a reference clock from the outside. In this case, the counters 32 and 33 can be configured to count only the delay times of DP and DM with reference to the reference clock.

Next, the details of the delay adjustment circuits 22 and 23 will be described with reference to FIGS. 9 and 10. FIG. 9 is a block diagram showing a configuration example of the delay adjustment circuit 22 according to the second embodiment. FIG. 10 is a timing chart of the internal signal of the delay adjustment circuit 22. The delay adjustment circuit 23 is also configured as shown in FIG. 9, and thus the description thereof will be omitted. The delay adjustment circuit 22 includes a RISE delay adjustment circuit 220 and a FALL delay adjustment circuit 230. The RISE delay adjustment circuit 220 receives the signal PEN_IN and outputs the signal PEN_OUT. PEN_IN and PEN_OUT are control signals for controlling ON or OFF of MP1 which is a P-type MOSFET of the output circuit 112. The RISE delay adjustment circuit 220 adjusts the timing at which MP1 is turned on and the DP is started by adjusting the timing at which PEN_OUT rises. On the other hand, the FALL delay adjustment circuit 230 receives the signal NEN_IN and outputs the signal NEN_OUT. NEN_IN and NEN_OUT are control signals for controlling ON or OFF of the NMOS transistor MN1 of the output circuit 112. The FALL delay adjustment circuit 230 adjusts the timing at which MN1 is turned on and the DP is lowered by adjusting the timing at which NEN_OUT rises.

With reference to FIG. 9, the RISE delay adjustment circuit 220 includes a plurality of delay elements 221s, a multiplexer (MUX) 222, and an AND circuit 223. The RISE delay adjustment circuit 220 generates a plurality of signals having different propagation delays from the input signal PEN_IN. The signal 224 is a signal generated by buffering the signal PEN_IN. The signal group 225 is a plurality of signals having different propagation delay values by propagating the delay elements 221 having different delay values or different stages. The signal group 225 having different propagation delays is input to the multiplexer (MUX) 222, and the signal 226 having a desired delay value is selected based on the control signal DELAY_DP and input to the B terminal of the AND circuit 223. A signal 224 is input to the A terminal of the AND circuit 223. The output signal PEN_OUT of the delay adjustment circuit 22 is generated by AND circuit 223 by ANDing the signal 224 with the signal 226 having a desired delay value. As a result, the RISE delay adjustment circuit 220 can output a signal to PEN_OUT whose rising edge is delayed by a desired value with respect to the signal PEN_IN. FIG. 10 shows how the rising edge of PEN_OUT is delayed. The RISE delay adjustment circuit 220 propagates the falling side of PEN_IN to PEN_OUT without delay by the AND circuit 223. FIG. 10 shows how the falling edge of PEN_OUT is output without delay. The reason why the falling side of PEN_IN is not delayed is to prevent a through current from flowing through MP1 and MN1 due to a delay in the OFF control of MP1. FIG. 10 shows that the epitaxial transistor MP1 is turned on while PEN_OUT is at the H level.

With reference to FIG. 9 again, the FALL delay adjusting circuit 230 includes a plurality of delay elements 231, a multiplexer (MUX) 232, and an OR circuit 233. The FALL delay adjustment circuit 230 generates a plurality of signals having different propagation delays from the input signal NEN_IN. The signal 234 is a signal generated by buffering the signal NEN_IN. The signal group 235 is a plurality of signals having different propagation delay values by propagating the delay elements 231 having different delay values or different stages. The signal group 235 is input to the multiplexer (MUX) 232, and the signal 236 having a desired delay value is selected based on the control signal DELAY_DM and input to the D terminal of the OR circuit 233. A signal 234 is input to the C terminal of the OR circuit 233. The output signal NEN_OUT of the FALL delay adjustment circuit 230 is generated by ORing the signal 234 and the signal 236 having a desired delay value by the OR circuit 233. As a result, the FALL delay adjustment circuit 230 can output a signal to NEN_OUT in which the fall of the signal is delayed by a desired value with respect to the signal NEN_IN. FIG. 10 shows how the falling edge of NEN_OUT is delayed. The FALL delay adjustment circuit 230 propagates the rising side of NEN_IN to NEN_OUT without delay by the OR circuit 233. FIG. 10 shows how the rising edge of NEN_OUT is output without delay. The reason why the rising side of NEN_IN is not delayed is to prevent a through current from flowing through MP1 and MN1 due to a delay in the OFF control of MN1. FIG. 10 shows that the NMOS transistor MN1 is turned off while NEN_OUT is at the H level.

In FIG. 9, the RISE delay adjustment circuit 220 and the FALL delay adjustment circuit 230 have a plurality of delay elements 221 and 231, respectively, but the configuration of the delay adjustment circuit 22 is not limited to this.

FIG. 11 is a block diagram showing a configuration example of the driver circuit 11A according to the second embodiment. Unlike the driver circuit 11 according to the first embodiment, the driver circuit 11A receives a signal PEN_OUT output by the delay adjustment circuit 22 instead of PEN_DP as an input of the inverter circuit composed of MP3 and MN3. Further, the driver circuit 11A receives the signal NEN_OUT output by the delay adjustment circuit 22 instead of NEN_DP as an input of the inverter circuit composed of MP4 and MN4. The driver circuit 11A can adjust the change timing of the output circuit 112 by PEN_OUT and NEN_OUT.

(motion)
FIG. 12 is a timing chart showing an example of the waveform of the differential output signal output by the differential output circuit 7A according to the second embodiment. FIG. 12 shows the waveforms of the differential output signals output from the differential output terminals DP and DM, and the waveforms of the status signals DP_COMP and DM_COMP output by the comparators 20 and 21. The comparators 20A and 21A monitor the point where the DP and DM voltages cross the reference voltage VREF3. Here, the value of the reference voltage VREF3 is, for example, 1/2 of the power supply voltage VDD, but it can be arbitrarily determined within a range to be adjusted according to a standard or the like. In FIG. 12, DP changes from L level to H level, and DM changes from H level to L level.

When the voltage of DP changes from L level to H level, the comparator 20A outputs H level to DP_COMP when it becomes VDD / 2 or more. The comparator 21A outputs the H level to DM_COMP when the voltage of DM changes from H to L and becomes VDD / 2 or less. The counters 32 and 33 count the delay time difference between the rising edge of the DP and the falling edge of the DM, or the delay time difference between the falling edge of the DP and the rising edge of the DM, based on DP_COMP and DM_COMP. The control circuit generates control signals DELAY_DP and DELAY_DM for delay adjustment based on the count values indicated by the counters 32 and 33, and adjusts the signal delays of the differential output terminals DP and DM.

With reference to FIG. 12, the waveform shown by the broken line is the waveform of the DP after the delay obtained by delaying the output waveform of the DP in this way. The solid DM waveform and the dashed DP waveform intersect at VDD / 2. That is, the cross point of the differential output signal is adjusted to VDD / 2.

FIG. 13 is a flowchart showing a crosspoint adjustment flow by the control circuit 34A. First, the differential output circuit 7A transmits a differential output signal (step S201). Subsequently, the counters 32 and 33 count the time difference between the cross points of the differential output terminals DP and DM (step S202). The control circuit 34A according to the second embodiment includes a register (not shown) for storing in advance an acceptable threshold value as a difference between the counters 32 and 33. The control circuit 34A refers to the values indicated by the counters 32 and 33 and determines whether or not the time difference between the DP and DM cross points is equal to or less than a predetermined threshold value (step S203). When the time difference between the cross points of DP and DM is larger than the threshold value (step S203: NO), the control circuit 34A adjusts the delays of the delay adjustment circuits 22 and 23 by DELAY_DP and DELAY_DM, so that either the DP side or the DM side It is determined whether the change timing is earlier (step S204). When the time when the DP intersects the reference voltage VREF3 is earlier than the time when the DM intersects the reference voltage VREF3 (step S204: YES), a delay is inserted on the DP side by the control signal DELAY_DP for delay adjustment on the DP side (step). S205). After adjusting the delay on the DP side, the control by the control circuit 34A shifts to the process of step S202 in order to determine whether or not the time difference between the cross points of DP and DM is improved below the threshold value. On the other hand, when the time when the DM intersects the reference voltage VREF3 is earlier than the time when the DP intersects the reference voltage VREF3 (step S204: NO), a delay is inserted on the DM side by the control signal DELAY_DM for delay adjustment (step S206). .. After adjusting the delay on the DM side, the control by the control circuit 34A shifts to the process of step S202 in order to determine whether or not the time difference between the DP and DM cross points is improved below the threshold value.

(effect)
The differential output circuit 7A according to the second embodiment includes the comparators 20A and 21A instead of the comparators 20 and 21 as compared with the differential output circuit 7 according to the first embodiment. Further, the differential output circuit 7A according to the second embodiment includes delay adjusting circuits 22 and 23. Therefore, the delay adjustment circuits 22 and 23 can delay the timing at which the driver circuits 11A and 12A output the differential output signal. Therefore, the differential output circuit 7A can adjust the cross point between DP and DM. As a result, it becomes easy to suppress the influence of fluctuations in the process, voltage, and temperature on the electrical characteristics defined by the standard such as USB, and to output a differential output signal satisfying the standard.

Also in the second embodiment, as in the modification of the first embodiment, the DELAY_DP and the DELAY_DM can be fixed based on the result of testing the semiconductor device with a tester at the time of shipment. In this case, the values of DELAY_DP and DELAY_DM can be stored in, for example, a non-volatile memory (not shown) built in the semiconductor device.

Further, although the delay adjustment circuits 22 and 23 have been described as being outside the driver circuits 11A and 12A in FIG. 7, the configuration of the differential output circuit 7A is not limited to this. The delay adjustment circuits 22 and 23 may be configured to be included in the driver circuits 11A and 12A, respectively.

Further, as the control circuit 34A according to the second embodiment, for example, a CPU can be used. Further, the control circuit 34A may be a dedicated decoder.

[Embodiment 3]
Next, the third embodiment will be described. FIG. 14 is a block diagram showing a configuration example of the differential output circuit 7B according to the third embodiment. The differential output circuit 7B according to the third embodiment includes delay adjusting circuits 22 and 23 as compared with the differential output circuit 7 according to the first embodiment, and the comparator 20B is replaced with the comparators 20 and 21. And 21B are provided, the counting unit 31B is provided instead of the counting unit 31, and the control circuit 34B outputs the DELAY_DP and DELAY_DM in addition to the control signals SLEW_DP and SLEW_DM. Since the other configurations and operations are the same as those of the semiconductor device 1 described in the first embodiment, the same configurations are designated by the same reference numerals, and duplicate description will be omitted.

The differential output circuit 7B according to the third embodiment has both a slew rate adjustment function of the differential output circuit 7 according to the first embodiment and a cross point adjustment function of the differential output circuit 7A according to the second embodiment. It has an adjustment function.

The delay adjustment circuits 22 and 23 are the same delay adjustment circuits as the differential output circuit 7A described in the second embodiment.

The comparator 20B is a voltage comparison circuit that compares the magnitude relationship between the voltage of the differential output terminal DP and the three reference voltages VREF1, VREF2, and VREF3. Similarly, the comparator 21B is a voltage comparison circuit that compares the magnitude relationship between the voltage of the differential output terminal DM and the three reference voltages VREF1, VREF2, and VREF3.

The adjustment control circuit 30B includes a counting unit 31B and a control circuit 34B. The adjustment control circuit 30B outputs control signals SLEW_DP and SLEW_DM to the driver circuits 11 and 12, respectively, based on the count value of the counter 32 and the count value of the counter 33. Further, the adjustment control circuit 30B outputs control signals DELAY_DP and DELAY_DM to the delay adjustment circuits 22 and 23, respectively, based on the count value of the counter 32 and the count value of the counter 33.

The counting unit 31B has both functions of the counting unit 31 according to the first embodiment and the counting unit 31A according to the second embodiment. The counting unit 31B is in the step of controlling by the control signals SLEW_DP and SLEW_DM as in the first embodiment, or in the step of controlling by the DELAY_DP and DELAY_DM as in the second embodiment, respectively. Performs a counting operation suitable for.

The control circuit 34B transmits the control signals SLEW_DP and SLEW_DM to the driver circuits 11 and 12, and also transmits the control signals DELAY_DP and DELAY_DM to the delay adjustment circuits 22 and 23.

(motion)
FIG. 15 is a timing chart of the differential output signal output by the differential output circuit 7B. The differential output circuit 7B according to the third embodiment first adjusts Tr / Tf, that is, the slew rate, as shown in FIG. 15A. Subsequently, the differential output circuit 7B adjusts the cross point using the delay adjustment circuit as shown in FIG. 15 (b).

FIG. 16 is a flowchart showing an operation flow of the differential output circuit 7B according to the third embodiment. Steps S101 to S108 are the same as FIG. 6 which is a flowchart of the first embodiment, and thus the description thereof will be omitted. When CNTDP and CNTDM match in step S105 (step S105: YES), the counter 32 and the counter 33 are switched to the operation mode for counting the time difference of the cross points (step S202). Since the operations from steps S202 to S206 are the same as those in FIG. 13 which is the flowchart according to the second embodiment, the description thereof will be omitted. When the cross point time difference is equal to or less than the threshold value (step S203: YES), the differential output signal adjustment operation by the differential output circuit 7B ends. As described above, in the third embodiment, after adjusting the slew rate, the cross point is adjusted. This is because changing the slew rate also changes the cross point, so it is better to adjust the slew rate first, determine the slew rate, and then adjust the delay difference of the cross point for better adjustment efficiency.

(effect)
The differential output circuit 7B according to the third embodiment further includes delay adjusting circuits 22 and 23 with respect to the differential output circuit 7 of the first embodiment. Further, the comparator 20B can compare the voltage of the differential output terminal DP with the voltage of the reference voltages VREF1, VREF2, and VREF3. Similarly, the comparator 21B can compare the voltage of the differential output terminal DM with the voltages of the reference voltages VREF1, VREF2, and VREF3. The adjustment control circuit 30B generates control signals SLEW_DP and SLEW_DM for adjusting the slew rate and control signals DELAY_DP and DELAY_DM for adjusting the cross point. Therefore, the differential output circuit 7B can perform both slew rate adjustment and cross point adjustment. Therefore, even when the slew rate and crosspoint electrical characteristics are standardized with respect to the differential output signal output by the differential output circuit 7B, the differential output circuit 7B is affected by the process, voltage, and temperature. A differential output signal that can be removed to satisfy the standard can be easily output.

[Embodiment 4]
Next, the fourth embodiment will be described. The differential output circuit 7C according to the fourth embodiment realizes the cross point adjustment by adjusting the slew rate.

(Constitution)
FIG. 17 is a block diagram showing a configuration example of the differential output circuit 7C according to the fourth embodiment. The differential output circuit 7C according to the fourth embodiment is different from the differential output circuit 7 according to the first embodiment in that the comparators 20C and 21C are provided instead of the comparators 20 and 21. Since the other configurations and operations are the same as those of the differential output circuit 7 described in the first embodiment, the same configurations are designated by the same reference numerals, and duplicate description will be omitted.

The comparator 20C is a voltage comparison circuit that compares the voltage of the differential output terminal DP with the reference voltage VREF3. When the voltage of the differential output terminal DP changes from the L level to the H level, the comparator 20C outputs the H level as a DP_COMP signal when the reference voltage is VREF3 or higher. Further, when the voltage of DP changes from H level to L level, the comparator 20C outputs H level as DP_COMP signal when the reference voltage is VREF3 or less.

Similarly, the comparator 21C is a voltage comparison circuit that compares the voltage of the differential output terminal DM with the reference voltage VREF3. When the voltage of the differential output terminal DM changes from the L level to the H level, the comparator 21C outputs the H level as a DM_COMP signal when the reference voltage is VREF3 or higher. Further, when the voltage of DM changes from H level to L level, the comparator 21C outputs H level as a DM_COMP signal when the reference voltage is VREF3 or less.

The adjustment control circuit 30C is a circuit that outputs control signals SLEW_DP and SLEW_DM for controlling the slew rate of the driver circuits 11 and 12 based on the values indicated by the counters 32 or 33. The driver circuit 11 adjusts the reference current by controlling the ratio of the current mirrors of the constant current circuits 110 and 111 based on SLEW_DP. Since the reference currents of the constant current circuits 110 and 111 are adjusted, the time required for charging and discharging the feedback capacitance elements C1 and C2 changes. As a result, the slew rate of the differential output signal output to the differential output terminal DP is adjusted. Similarly, the driver circuit 12 adjusts the reference current by controlling the ratio of the current mirrors of the constant current circuits 110 and 111 based on SLEW_DM. Since the reference currents of the constant current circuits 110 and 111 are adjusted, the time required for charging and discharging the feedback capacitance elements C1 and C2 changes. As a result, the slew rate of the differential output signal output to the differential output terminal DM is adjusted. The adjustment control circuit 30C adjusts the cross point of both signals by adjusting the slew rate of the signals output to the differential output terminals DP and DM.

(motion)
In the adjustment control circuit 30C, the time difference between when either one of the differential output terminals DP or DM reaches VDD / 2 first and when the other of DP or DM reaches VDD / 2 is the counter 32 or the counter. It is counted at 33. In other words, in the adjustment control circuit 30C, the time difference between the activation of one of the status signals DP_COMP or DM_COMP and the activation of the other is counted by the counter 32 or the counter 33. More specifically, when the differential output terminal DP reaches VDD / 2 before the differential output terminal DM, the counter 32 performs a counting operation. On the other hand, when the differential output terminal DM reaches VDD / 2 before the differential output terminal DP, the counter 33 performs a counting operation.

FIG. 18 is a timing chart of the differential output signal output by the differential output circuit 7C according to the fourth embodiment. In the example shown in FIG. 18, at the time T1 when the waveform of the differential output terminal DP changes from L level to H level and reaches VDD / 2, the waveform of the differential output terminal DM changes from H level to L level. It is earlier than the time T2 when it reaches VDD / 2 when it changes. Therefore, the waveform of the DP before adjustment shown by the solid line and the waveform of the DM before adjustment shown by the solid line cross at a voltage higher than VDD / 2. The counter 32 performs a counting operation from the time T1 to the time T2. The control circuit 34C generates a SLEW_DP signal in order to adjust the slew rate of the differential output terminal DP based on the value indicated by the counter 32. The driver circuit 11 adjusts the slew rate of the differential output terminal DP so as to change from the L level to the H level more slowly based on the control signal SLEW_DP. As a result, as shown in FIG. 18, the rising waveform of the differential output terminal DP changes as shown by the broken line. As a result, the differential output circuit 7C can adjust the cross point of the differential output terminals DP and DM to VDD / 2.

(effect)
The differential output circuit 7C according to the fourth embodiment includes the comparators 20C and 21C instead of the comparators 20 and 21 as compared with the differential output circuit 7 according to the first embodiment. Therefore, the comparators 20C and 21C can adjust the cross point of the differential output signal based on one reference voltage VREF3 and without providing a delay control circuit. As a result, the differential output circuit 7C can easily output a differential output signal that satisfies the electrical characteristics defined by the standard or the like by removing the influence of the process, voltage, and temperature.

Although the invention made by the present invention has been specifically described above based on the embodiments, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

1 Semiconductor device 2 CPU
3 ROM
4 RAM
5 Logic circuit 6 USB transceiver 7, 7A, 7B, 7C Differential output circuit 9 Peripheral equipment 11, 12 Driver circuit 13 Driver control circuit 14 Reference current generation circuit 20, 20A, 20B, 20C Comparator 21, 21A, 21B, 21C Comparator 22,23 Delay adjustment circuit 30, 30A, 30B, 30C Adjustment control circuit 31, 31A, 31B, 31C Count unit 32, 33 Counter 34, 34A, 34B, 34C Control circuit 90 Host computer 91 Semiconductor device 92 USB transceiver 110, 110A Constant current circuit 111, 111A Constant current circuit 112 Output circuit 220 RISE delay adjustment circuit 230 FALL delay adjustment circuit 221, 231 Delay element 222, 232 multiplexer (MUX)
223 AND circuit 233 OR circuit 224, 234 signal 225, 235 signal group 226, 236 signal 310 XOR circuit 311, 312 AND circuit 313, 314 Ring oscillator (ROSC)
C1, C2 feedback capacitance element DELAY_DP, DELAY_DM control signal DP_CN, DM_CN clock signal DP, DM differential output terminal DP_COMP, DM_COMP status signal MN1, MN2, MN3, MN4 N-type MOSFET
MP1, MP2, MP3, MP4 P-type MOSFET
PEN_IN, NEN_IN signal PEN_OUT, NEN_OUT signal PEN_DP, NEN_DP, PEN_DM, NEN_DM control signal SLEW_DP, SLEW_DM control signal VCS, VCSQ, VDD Power supply voltage VREF1, VREF2, VREF3 Reference voltage VSS

Claims (16)

A first output circuit that outputs the first signal included in the differential output signal, and
The first circuit that controls the output waveform of the first output circuit and
A second output circuit that outputs a second signal included in the differential output signal, and a second output circuit.
A second circuit that controls the output waveform of the second output circuit, and
A first comparator that outputs a first status signal indicating whether or not the first signal is in a predetermined voltage range, and a first comparator.
A second comparator that outputs a second status signal indicating whether or not the second signal is in the predetermined voltage range, and
An adjustment control circuit for receiving the first status signal and the second status signal is provided.
The adjustment control circuit controls the first circuit and the second circuit based on the first status signal and the second status signal.
Semiconductor device. The adjustment control circuit
A first counter that counts based on the first status signal, and
A second counter that counts based on the second status signal is provided.
The adjustment control circuit controls the first circuit and the second circuit based on the count values of the first counter and the second counter.
The semiconductor device according to claim 1. The first circuit includes a first constant current circuit and a second constant current circuit for controlling the output waveform of the first output circuit.
The second circuit includes a third constant current circuit and a fourth constant current circuit for controlling the output waveform of the second output circuit.
The adjustment control circuit controls the amount of current in the first to fourth constant current circuits based on the first count value indicated by the first counter and the second count value indicated by the second counter. To do,
The semiconductor device according to claim 2. The first circuit further comprises a first capacitive element and a second capacitive element connected to the first output circuit.
The second circuit further comprises a third capacitive element and a fourth capacitive element connected to the second output circuit.
The first capacitive element is connected to the first constant current circuit and is connected to the first constant current circuit.
The second capacitive element is connected to the second constant current circuit and is connected to the second constant current circuit.
The third capacitive element is connected to the third constant current circuit.
The semiconductor device according to claim 3, wherein the fourth capacitive element is connected to the fourth constant current circuit. When the first count value is larger than the second count value, the adjustment control circuit controls to increase the currents of the first constant current circuit and the second constant current circuit.
The semiconductor device according to claim 3. When the first count value is larger than the second count value, the adjustment control circuit controls to reduce the currents of the third constant current circuit and the fourth constant current circuit.
The semiconductor device according to claim 3. The first reference voltage and the second reference voltage, which are predetermined based on the power supply voltage supplied to the first output circuit and the second output circuit, are the first comparator and the second comparator. Entered in
The predetermined voltage range is equal to or higher than the first reference voltage and equal to or lower than the second reference voltage.
The semiconductor device according to claim 1. The adjustment control circuit further includes a clock generation circuit.
The first counter and the second counter count based on the clock supplied by the clock generation circuit.
The semiconductor device according to claim 2. The first circuit is a first delay adjusting circuit for adjusting a delay amount of data input to the first output circuit.
The second circuit is a second delay adjusting circuit for adjusting the delay amount of the data input to the second output circuit.
The adjustment control circuit controls the delay amount of the first delay adjustment circuit and the delay amount of the second delay adjustment circuit based on the first status signal and the second status signal.
The semiconductor device according to claim 1. A reference voltage predetermined based on the power supply voltage supplied to the first output circuit and the second output circuit is input to the first comparator and the second comparator.
The predetermined voltage range is equal to or higher than the reference voltage.
The semiconductor device according to claim 1. A first delay adjustment circuit for adjusting the amount of delay of data input to the first circuit, and
A second delay adjusting circuit for adjusting the delay amount of data input to the second circuit is further provided.
The first circuit includes a first constant current circuit and a second constant current circuit for controlling the output waveform of the first output circuit.
The second circuit includes a third constant current circuit and a fourth constant current circuit for controlling the output waveform of the second output circuit.
The adjustment control circuit is based on the first count value indicated by the first counter and the second count value indicated by the second counter, and the current amount of the first to fourth constant current circuits, said. Controlling the delay amount of the first delay adjustment circuit and the delay amount of the second delay adjustment circuit.
The semiconductor device according to claim 2. A reference voltage predetermined based on the power supply voltage supplied to the first output circuit and the second output circuit is input to the first comparator and the second comparator.
The predetermined voltage range is
When the first signal changes from the first level to the second level, it is equal to or higher than the reference voltage.
When the first signal changes from the second level to the first level, it is equal to or less than the reference voltage.
Based on the time difference between the first status signal and the second status signal being activated, the first counter or the second counter counts.
The adjustment control circuit controls the first circuit or the second circuit based on the count value of the first counter or the second counter.
The semiconductor device according to claim 2. A method of operating a semiconductor device including first and second output circuits, first and second circuits, first and second comparators, and first and second counters. The operation method is
The step of outputting the first signal included in the differential output signal and
A step of controlling the output waveform of the first output circuit by the first circuit, and
The step of outputting the second signal included in the differential output signal, and
A step of controlling the output waveform of the second output circuit by the second circuit, and
A step of outputting a first status signal indicating whether or not the first signal is in a predetermined voltage range by the first comparator, and a step of outputting the first status signal.
A step of outputting a second status signal indicating whether or not the second signal is in a predetermined voltage range by the second comparator, and a step of outputting the second status signal.
A step of counting based on the first status signal by the first counter, and
A step of counting based on the second status signal by the second counter, and
It has a step of controlling the first circuit and the second circuit based on the count values of the first counter and the second counter.
How to operate a semiconductor device. The first circuit includes first and second constant current circuits.
The second circuit includes third and fourth constant current circuits.
The step of controlling the output waveform of the first output circuit further includes a step of controlling the output waveform of the first output circuit by the first and second constant current circuits.
The step of controlling the output waveform of the second output circuit further includes a step of controlling the output waveform of the second output circuit by the third and fourth constant current circuits.
The step of controlling the first circuit further includes a step of controlling the amount of current flowing through the first and second constant current circuits based on the count values of the first counter and the second counter. ,
The step of controlling the second circuit further includes a step of controlling the amount of current flowing through the third and fourth constant current circuits based on the count values of the first counter and the second counter. ,
The method of operating the semiconductor device according to claim 13. The first circuit includes a first delay adjusting circuit for adjusting a delay amount of data input to the first output circuit.
The second circuit includes a second delay adjusting circuit for adjusting a delay amount of data input to the second output circuit.
The step of controlling the first circuit further includes a step of controlling the delay amount of the first delay adjusting circuit based on the count values of the first counter and the second counter.
The step of controlling the second circuit further includes a step of controlling the delay amount of the second delay adjusting circuit based on the count values of the first counter and the second counter.
The method of operating the semiconductor device according to claim 13. The first circuit includes first and second constant current circuits.
The second circuit includes third and fourth constant current circuits.
The semiconductor device is
A first delay adjustment circuit for adjusting the amount of delay of data input to the first circuit, and
A second delay adjusting circuit for adjusting the delay amount of data input to the second circuit is further provided.
The step of controlling the output waveform of the first output circuit further includes a step of controlling the output waveform of the first output circuit by the first and second constant current circuits.
The step of controlling the output waveform of the second output circuit further includes a step of controlling the output waveform of the second output circuit by the third and fourth constant current circuits.
The step of controlling the first circuit further includes a step of controlling the amount of current flowing through the first and second constant current circuits based on the count values of the first counter and the second counter. ,
The step of controlling the second circuit further includes a step of controlling the amount of current flowing through the third and fourth constant current circuits based on the count values of the first counter and the second counter. ,
A step of controlling the delay amount of the first delay adjustment circuit based on the count values of the first counter and the second counter, and
A step of controlling the delay amount of the second delay adjusting circuit based on the count values of the first counter and the second counter is further included.
The method of operating the semiconductor device according to claim 13.

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