JP5809550B2 - CR oscillation circuit and semiconductor integrated device - Google Patents

Description

  The present invention relates to a CR oscillation circuit and a semiconductor integrated device in which the CR oscillation circuit is formed.

  As an oscillation circuit for generating a clock pulse in a digital circuit, a CR oscillation circuit that generates a sine wave by feedback-connecting a CR circuit composed of a capacitor and a resistor to three inverters connected in series Is known (see, for example, FIG. 1 of Patent Document 1). In such a CR oscillation circuit, the oscillation signal sent from the inverter 12 is fed back to the input terminal of the inverter 11 via the capacitor 15. Therefore, due to the transient phenomenon of the capacitor accompanying the oscillation signal, the so-called overshoot and undershoot in which the voltage suddenly exceeding the power supply voltage and the voltage lower than the ground potential are applied to the input terminal of the inverter 11 occur. There was a possibility that the life of 11 would be reduced.

  Therefore, in order to suppress such overshoot and undershoot, this CR oscillation circuit is provided with a second capacitor 16 at the input terminal of the inverter 11.

  However, since the capacitor 16 having a larger element area than the inverter must be newly provided, there has been a problem that the overall scale of the CR oscillation circuit becomes large.

Japanese Patent Laid-Open No. 07-131301

  An object of the present invention is to provide a CR oscillation circuit and a semiconductor integrated device that are small in size and capable of high-density mounting without causing a reduction in lifetime.

A CR oscillation circuit according to the present invention includes an inverter train including m (m is an integer of 3 or more) inverters connected in series in order from upstream to downstream, and (2n) th from the upstream in the inverter train. The signal sent from the inverter connected to the second (n is an integer of 1 or more) is supplied to the first connected inverter from the upstream in the inverter train via a capacitor, and the inverter train a CR oscillating circuit having a CR circuit for supplying to said first first inverter from the upstream first (2n + 1) a signal sent from the connected inverter th through the resistor, the m Each of the inverters excluding the first inverter when the level of the input signal is lower than a predetermined logic threshold value While outputting the high level signal, the predetermined logic is higher than the threshold value and outputs a low level signal, the first numbered inverter, the level of the signal supplied from the CR circuit is the predetermined logic threshold When a transition is made from a state lower than the lower first logic threshold to a state higher than the first logic threshold, a low level signal is supplied to the inverter of the next stage, while the level of the signal supplied from the CR circuit When a transition is made from a state higher than the second logic threshold value higher than the predetermined logic threshold value to a state lower than the second logic threshold value, a high level signal is supplied to the next-stage inverter.

The semiconductor integrated device according to the present invention includes an inverter train composed of m (m is an integer of 3 or more) inverters connected in series in order from upstream to downstream, and (2n) th from the upstream in the inverter train. The signal sent from the inverter connected to the second (n is an integer equal to or greater than 1) is supplied to the first connected inverter from the upstream of the inverter train via a capacitor, and the inverter train A CR circuit that supplies a signal sent from the (2n + 1) -th connected inverter from the upstream to the first inverter through a resistor, with an oscillation output terminal for outputting a signal transmitted from the first inverter in the inverter train as an oscillation signal, the m Each of the inverters except the first inverter outputs a high level signal when the level of the input signal is lower than a predetermined logic threshold value, and when the level is higher than the predetermined logic threshold value, When the low-level signal is output and the level of the signal supplied from the CR circuit transits from a state lower than the first logic threshold lower than the predetermined logic threshold to a higher state While a low level signal is supplied to the inverter of the next stage, the level of the signal supplied from the CR circuit is lower than the second logic threshold after exceeding the second logic threshold higher than the predetermined logic threshold. When the transition is made, a high level signal is supplied to the inverter of the next stage.

  In the present invention, a signal sent from the (2n + 1) -th connected inverter in an inverter train in which a plurality of inverters are connected in series, and a signal sent from the (2n) -th inverter, respectively. The following inverter is used as the first inverter in generating the oscillation signal by feeding back to the first inverter through a resistor and a capacitor. That is, when the level of the signal supplied from the resistor and capacitor as described above transitions from a state lower than the first logic threshold to a high state, the first inverter sends a low level signal to the next stage inverter. Supply. In addition, the first inverter temporarily exceeds the second logic threshold value, which is higher than the first logic threshold value, after which the level of the signal supplied from these resistors and capacitors is lower than the second logic threshold value. When the transition is made, a high level signal is supplied to the inverter of the next stage.

  According to such a configuration, since the peak potential of undershoot and overshoot generated on the input terminal of the first inverter can be reduced, it is possible to suppress a reduction in the element life of the first inverter. Become. Furthermore, since a capacitor for suppressing the amount of undershoot and overshoot is not required, the scale of the apparatus can be reduced.

1 is a circuit diagram showing a CR oscillation circuit according to the present invention formed in a semiconductor chip 10; FIG. It is a time chart which shows operation | movement of the inverters 1-3. It is a time chart which shows the internal operation | movement of CR oscillation circuit. It is a circuit diagram which shows another example of CR oscillation circuit. It is a circuit diagram which shows an example of the inverters 11 and 12. FIG. 6 is a circuit diagram showing a modification of the CR oscillation circuit formed in the semiconductor chip 10. FIG.

In the present invention, a signal sent from the (2n + 1) -th connected inverter (3) in an inverter train formed by connecting a plurality of inverters (1 to 3) in series is passed through a resistor (5). By supplying to the first inverter (1) and supplying the signal sent from the (2n) th inverter (2) to the first inverter (1) via the capacitor (4), oscillation It is a CR oscillation circuit that generates a signal. At this time, when the first inverter (1) transitions from a state where the level of the signal supplied from the resistor (5) and the capacitor (4) is lower than the first logic threshold (TH _L ) to a higher state. Supplies a low level (GND) signal to the next inverter. Further, the first inverter (1) has a level of a signal supplied from the resistor (5) and the capacitor (4) exceeding a second logic threshold (TH _H ) higher than the first logic threshold (TH _L ). After that, when the state transitions to a state lower than the second logic threshold value, a high level (Vdd) signal is supplied to the next stage inverter.

  FIG. 1 is a circuit diagram showing an example of a CR oscillation circuit formed in a semiconductor chip 10 as a semiconductor integrated device.

  As shown in FIG. 1, the CR oscillation circuit according to the present invention includes inverters 1 to 3, a capacitor 4 and a resistor 5.

  As shown in FIG. 1, a capacitor 4 is connected between the input terminal of the inverter 1 and the output terminal of the inverter 2 in the inverter train in which three inverters 1 to 3 are connected in series. A resistor 5 is connected between the output terminals of the inverter 3. That is, as shown in FIG. 1, the output terminal of the inverter 1 is connected to the input terminal of the inverter 2 via the line L1, and the output terminal of the inverter 2 is connected to the input terminal of the inverter 3 and the capacitor 4 via the line L2. It is connected to one end. The output terminal of the inverter 3 is connected to one end of the resistor 5 and the oscillation output terminal PD via the line L3, and the other end of each of the capacitor 4 and the resistor 5 is connected to the input terminal of the inverter 1 via the line L0. Has been. As described above, in the CR oscillation circuit shown in FIG. 1, the signal generated by the CR circuit including the capacitor 4 and the resistor 5 connected to the output terminals of the inverters 2 and 3, respectively, is transferred to the inverter 1 via the line L0. To the input terminal.

Inverter 1, a first logic threshold TH _L, and based on the two thresholds comprised of high second logic threshold TH _H than the first logical threshold TH _L, performs level inversion of the input signal. That is, the inverter 1 has a high level corresponding to the logic level 1, that is, the power supply potential when the level of the input signal IN supplied to its input terminal is lower than the first logic threshold value TH _L as shown in FIG. An inverted signal having Vdd is output. At this time, as shown in FIG. 2, when the level of the input signal IN from lower than the first logical threshold TH _L, remained in a state higher than the first logical threshold TH _L, the inverter 1 Outputs a low level corresponding to the logic level 0, that is, an inverted signal having the ground potential GND. Thereafter, as shown in FIG. 2, when the level of the input signal IN is temporarily lowered after exceeding the second logical threshold TH _H, it was in a state of below again second logical threshold TH _H, the inverter 1 outputs an inverted signal having the ground potential GND corresponding to the logic level 0.

In short, among the inverters 1 to 3 connected in series, the inverter 1 connected first from the upstream side in the signal flow direction has the first logic threshold value TH _L as the rising logic threshold value. Based on this, a time point at which the input signal transitions from the logic level 0 to 1 is detected, and at this time, a signal obtained by inverting the logic level of the input signal, that is, an inverted signal from the logic level 1 to 0 is output. The inverter 1, a second logic threshold TH _H as falling logic threshold, detects when the input signal transitions to the state 0 and a logic level 1, this time, by inverting the logic level of the input signal Therefore, an inverted signal that transitions from a logic level 0 to a 1 state is output. Note that the first logical threshold value TH _L is smaller than the logical threshold value TH _M of the inverters 2 and 3 as described below. Further, the second logic threshold value TH _H is larger than the logic threshold value TH _M of the inverters 2 and 3.

The inverters 2 and 3 are supplied to their input terminals based on a third logic threshold value TH _M that is higher than the first logic threshold value TH _L and lower than the second logic threshold value TH _H as shown in FIG. The level of the input signal is inverted. That is, when the level of the input signal IN as shown in FIG. 2 supplied to the input terminals of the inverters 2 and 3 is lower than the third logic threshold value TH _M , the inverters 2 and 3 have a high level corresponding to the logic level 1; That is, an inversion signal having the power supply potential Vdd is output. On the other hand, if the level of the input signal IN is higher than the third logical threshold TH _M, the inverter 2 and 3, as shown in FIG. 2, the low-level corresponding to a logic level 0, i.e. inversion having the ground potential GND Output a signal.

  Hereinafter, the operation of the CR oscillation circuit shown in FIG. 1 will be described with reference to FIG.

First, at time t0 immediately after power-on, the potentials of the lines L0 and L2 are in the ground potential GND state corresponding to the logic level 0, that is, the low level state, and the potentials of the lines L1 and L3 correspond to the logic level 1. The power supply potential Vdd is in a high level state. Since the power supply potential Vdd is applied to the line L3 by turning on the power, the capacitor 4 is charged via the resistor 5. As a result, the potential on the line L0 gradually rises with time as shown in FIG. Thereafter, when the potential on the line L0 exceeds the logic threshold value TH _L of the inverter 1 at the time t1, the inverter 1 supplies an inverted signal indicating the logic level 0 to the inverter 2 via the line L1. When an inverted signal indicating a logic level 0 is supplied from the inverter 1, the inverter 2 outputs an inverted signal indicating the logic level 1 obtained by inverting the logic level via the line L2 as shown in FIG. 4 is supplied. Thereby, the inverter 3 supplies the ground potential GND corresponding to the logic level 0 to the resistor 5 via the line L3.

As shown in FIG. 3, when the potential of the line L2 transitions from the ground potential GND state to the power supply potential Vdd state at the time t1, the potential on the line L0 increases sharply due to the transient phenomenon of the capacitor 4. At this time, the potential on the line L0, exceeds the logic threshold TH _H of the inverter 1, leading to to a power supply potential Vdd, and or slightly smaller becomes potential than the power supply potential Vdd. After that, as described above, when an inverted signal of logic level 0 is sent on the line L3 by the inverter 3, the ground potential GND is applied to the line L0 via the resistor 5, so that the capacitor 4 is discharged. . As a result, the potential on the line L0 gradually decreases with time as shown in FIG. Thereafter, at time t2, the potential on the line L0 is below the logical threshold TH _H of the inverter 1, the inverter 1 is supplied to the inverter 2 through the line L1 of the inversion signal indicating a logic level 1. At this time, the inverter 2 supplies an inverted signal indicating a logic level 0 obtained by inverting the logic level to the inverter 3 and the capacitor 4 via the line L2. As a result, the inverter 3 supplies the power supply potential Vdd corresponding to the logic level 1 to the resistor 5 through the line L3 as shown in FIG.

As shown in FIG. 3, when the potential of the line L2 transitions from the power supply potential Vdd state to the ground potential GND state at time t2, the potential on the line L0 sharply decreases due to the transient phenomenon of the capacitor 4. At this time, the potential on the line L0 falls below the logic threshold value TH _L of the inverter 1 and reaches the ground potential GND or a potential slightly higher than the ground potential GND. Thereafter, as described above, when an inverted signal of logic level 1 is sent on the line L3 by the inverter 3, the power supply potential Vdd is applied to the line L0 via the resistor 5, so that the capacitor 4 is charged. . As a result, the potential on the line L0 gradually increases with time as shown in FIG.

  The CR oscillation circuit shown in FIG. 1 generates an oscillation signal having a period T as shown in FIG. 3 by periodically repeating the operations at the time points t0 to t2 as described above. The CR oscillation circuit is connected to the line L3 and the oscillation output terminal PD. Output via.

  Here, in this CR oscillation circuit, among the inverters 1 to 3 connected in series, the following two thresholds are set as the inverter 1 that is the input target of the signal generated by the CR circuit (4, 5). Use what you have.

That is, the inverter 1 employs a logic threshold TH _L that is lower than the logic threshold TH _M of the inverters 2 and 3 for detecting that the input signal has transitioned from the logic level 0 to 1, and the logic level 1 to 0 As the logic threshold value TH _H for detecting the transition to, a value higher than the logic threshold value TH _M of the inverters 2 and 3 is adopted. That is, in the inverter 1, in contrast to the Schmitt trigger type inverter, the logic threshold value (TH _L ) is lower than the logic threshold value (TH _H ).

According to the inverter 1, in the period (t0 to t1) in which the potential on the line L0 gradually increases from the ground potential GND state, the time point t1 of the logic threshold value TH _L lower than the logic threshold value TH _M of the inverters 2 and 3 Thus, a signal that transitions from the logic level 1 to the state 0 is supplied to the inverter 2 in the next stage. As a result, the inverter 2 supplies the power supply potential Vdd corresponding to the logic level 1 to the capacitor 4, so that a steep potential increase due to a transient phenomenon of the capacitor 4, so-called overshoot occurs on the line L 0. However, as shown in FIG. 3, since the potential rises from a potential (TH _L ) state lower than the logical threshold value TH _M of the inverters 2 and 3, overshoot occurs from a potential state equal to the logical threshold value TH _M. The peak potential of overshoot is lower than that of.

Further, according to the inverter 1, in the interval (t1 to t2) in which the potential on the line L0 is decreased gradually, from a logic level 0 in the logic threshold TH is higher than the _M logical threshold TH when the _H t2 of the inverter 2 and 3 A signal transitioning to the state 1 is supplied to the inverter 2 in the next stage. As a result, the inverter 2 supplies the ground potential GND corresponding to the logic level 0 to the capacitor 4, so that a steep potential drop due to a transient phenomenon of the capacitor 4, a so-called undershoot occurs on the line L 0. However, as shown in FIG. 3, since the potential drops from a potential (TH _H ) state higher than the logical threshold TH _M of the inverters 2 and 3, undershoot occurs from a potential state equal to the logical threshold TH _M. The peak potential of overshoot is lower than that of.

  Therefore, according to the CR oscillation circuit, even if undershoot and overshoot occur on the line L0, the peak potential can be lowered. Therefore, it is possible to suppress a decrease in element lifetime due to the potential applied to the input terminal of the inverter 1 exceeding the range of the power supply potential Vdd to the ground potential GND due to such undershoot and overshoot. . Furthermore, according to the CR oscillation circuit according to the present invention, a capacitor for suppressing the amount of undershoot and overshoot is not required, so that the scale of the device can be reduced.

  FIG. 4 is a circuit diagram showing another embodiment of the CR oscillation circuit according to the present invention.

  4 is the same as that shown in FIG. 1 except that the inverter 1a is used instead of the inverter 1.

  In FIG. 4, the inverter 1 a includes two inverters 21 and 22 and a selector 23.

The inverter 21 as the first inverter has a logic level 1 when the level of the input signal IN supplied to its input terminal is lower than the first logic threshold TH _L as shown in FIG. supplying a first inverted signal _{V H} indicating a level 0 to the selector 23. The inverter 22 as the second inverter has a logic level 1 when the level of the input signal IN supplied to its input terminal is lower than the second logic threshold value TH _H as shown in FIG. A second inverted signal _VL indicating level 0 is supplied to the selector 23. The inverters 21 and 22 are each composed of a p-channel MOS (Metal Oxide Semiconductor) type transistor Q1 and an n-channel MOS type transistor Q2 as shown in FIG. At this time, the logic threshold values TH _L and TH _H are obtained by individually setting the gate widths or gate lengths of the transistors Q1 and Q2 in the inverter 21 and the inverter 22, respectively. The selector 23 supplies the first inverted signal V _H supplied from the inverter 21 and the inverter 22 when the inverted signal sent out on the line L2 by the inverter 2 is a low level signal indicating the logic level 0. The first inverted signal V _H is selected from the second inverted signals V _L thus generated, and is supplied to the inverter 2 at the next stage via the line L1. On the other hand, when the inverted signal sent from the inverter 2 is a high level signal indicating the logic level 1, the selector 23 selects the second inverted signal _VL supplied from the inverter 22 and outputs it to the line. It supplies to the inverter 2 of the next stage via L1.

  4 also performs the same operation as the CR oscillation circuit having the configuration shown in FIG. 1, that is, the oscillation operation shown in FIG.

  In addition, FIG. 1 or FIG. 4 shows a configuration when the present invention is applied to a CR oscillation circuit including an inverter train in which three inverters 1 to 3 are connected in series. The number of is not limited to three, and may be four or more.

  In short, the present invention can be similarly applied to a CR oscillation circuit including an inverter train including m (m is an integer of 3 or more) inverters connected in series in order from upstream to downstream along the signal flow. At this time, as the CR oscillation circuit, the signal sent from the (2n) th inverter (n is an integer of 1 or more) from the upstream in the inverter train is passed through the capacitor and the first from the upstream in the inverter train. The signal sent from the (2n + 1) th inverter connected from the upstream is only required to be supplied to the first inverter via the resistor.

  In the above embodiment, all elements (inverters 1 to 3, capacitor 4 and resistor 5) constituting the CR oscillation circuit are formed on one semiconductor chip 10. The CR oscillation circuit may be constructed in such a manner that these are not provided in the semiconductor chip 10 but are externally connected to the semiconductor chip 10.

For example, as shown in FIG. 6A, an external terminal PD ₁ for omitting the capacitor 4 and the resistor 5 from the semiconductor chip 10 shown in FIG. An external terminal PD ₂ for connecting the other end of the capacitor 4 to the output terminal of the inverter 2 by external connection, and an external terminal PD ₃ for connecting the other end of the resistor 5 to the output terminal of the inverter 3 by external connection. Are provided. That, is connected to the first external terminal PD ₁ which is connected to an input terminal of the first inverter 1 in the inverter train as mentioned above, the output terminal of the inverter 2 connected to the (2n) th and a second external terminal PD ₂ has, is of providing a first (2n + 1) 3 which is connected to the output terminal of the inverter 3 connected to the second external terminal PD _3, the semiconductor chip 10.

Further, as shown in FIG. 6B, only the capacitor 4 is omitted from the semiconductor chip 10 shown in FIG. 1, and the external terminal PD for connecting the capacitor 4 to the input terminal of the inverter 1 and the output terminal of the inverter 2 by external connection. ₁ and PD ₂ may be provided. That, is connected to the first external terminal PD ₁ which is connected to an input terminal of the first inverter 1 in the inverter train as mentioned above, the output terminal of the inverter 2 connected to the (2n) th The second external terminal PD ₂ is provided on the semiconductor chip 10.

6C, only the resistor 5 is omitted from the semiconductor chip 10 shown in FIG. 1, and the external terminal for connecting the resistor 5 to the input terminal of the inverter 1 and the output terminal of the inverter 3 by external connection. PD ₁ and PD ₂ may be provided. In other words, the first external terminal PD ₁ connected to the input terminal of the first inverter 1 in the inverter train as described above and the output terminal of the inverter 3 connected to the (2n + 1) th are connected. The second external terminal PD ₂ is provided on the semiconductor chip 10.

  In the above embodiment, the inverters 1 to 3 are used as the inverting elements constituting the CR oscillation circuit, but a NAND gate or a NOR gate may be used instead of these inverters.

1-3 Inverter 4 Capacitor 5 Resistance

Claims (7)

An inverter train composed of m (m is an integer of 3 or more) inverters connected in series in order from upstream to downstream, and (2n) th (n is an integer of 1 or more) from the upstream in the inverter train The signal sent from the inverter connected to the inverter is supplied to the inverter connected first from the upstream in the inverter train via the capacitor, and (2n + 1) th from the upstream in the inverter train. A CR oscillation circuit having a CR circuit for supplying a signal sent from a connected inverter to the first inverter through a resistor,
Of the m inverters, each of the inverters other than the first inverter outputs a high-level signal when the level of the input signal is lower than a predetermined logic threshold, while the inverter exceeds the predetermined logic threshold. When it is high, it outputs a low level signal,
The first inverter is low when the level of the signal supplied from the CR circuit transitions from a state lower than the first logic threshold lower than the predetermined logic threshold to a state higher than the first logic threshold. While the level signal is supplied to the inverter of the next stage, the level of the signal supplied from the CR circuit is changed from a state higher than the second logic threshold higher than the predetermined logic threshold to a state lower than the second logic threshold. A CR oscillation circuit characterized in that a high-level signal is supplied to the next-stage inverter when a transition is made. The first inverter generates a high level signal when the level of the signal supplied from the CR circuit is lower than the first logic threshold value, and generates a low level signal when the level is high. A first inverter;
A second inverter that generates a high level signal when the level of the signal supplied from the CR circuit is lower than the second logic threshold, and generates a low level signal when the level is higher;
A selector that selects a signal sent from one of the first and second inverters according to the level of the signal sent from the (2n) -th inverter and supplies the selected signal to the next-stage inverter; CR oscillation circuit according to claim 1, wherein a. The selector selects the signal sent from the first inverter when the signal sent from the (2n) th inverter is at the low level, and supplies it to the next-stage inverter, When the signal sent from the (2n) th inverter is at the high level, the signal sent from the second inverter is selected and supplied to the next-stage inverter. Item 3. The CR oscillation circuit according to Item 2 . An inverter train composed of m (m is an integer of 3 or more) inverters connected in series in order from upstream to downstream, and (2n) th (n is an integer of 1 or more) from the upstream in the inverter train The signal sent from the inverter connected to the inverter is supplied to the inverter connected first from the upstream in the inverter train via the capacitor, and (2n + 1) th from the upstream in the inverter train. A CR circuit for supplying a signal sent from an inverter connected to the first inverter via a resistor,
An oscillation output terminal for outputting a signal sent from one inverter in the inverter train as an oscillation signal;
Of the m inverters, each of the inverters other than the first inverter outputs a high-level signal when the level of the input signal is lower than a predetermined logic threshold, while the inverter exceeds the predetermined logic threshold. When it is high, it outputs a low level signal,
The first inverter outputs a low level signal in the next stage when the level of the signal supplied from the CR circuit transitions from a state lower than the first logic threshold lower than the predetermined logic threshold to a higher state. While the signal is supplied to the inverter, the level of the signal supplied from the CR circuit exceeds the second logic threshold value higher than the predetermined logic threshold value, and then transitions to a state lower than the second logic threshold value. A semiconductor integrated device, wherein a signal is supplied to the inverter of the next stage . (The m 3 or more integer) m pieces which are connected in series in this order toward the upstream to downstream a semiconductor integrated device inverter train consisting of inverters are made form,
A first external terminal connected to the input terminal of the inverter connected first from the upstream in the inverter train;
A second external terminal connected to the output terminal of the inverter connected to the (2n) th (n is an integer of 1 or more) from the upstream in the inverter train ;
A third external terminal connected to the output terminal of the inverter connected to the (2n + 1) th from the upstream in the inverter train,
Of the m inverters, each of the inverters other than the first inverter outputs a high-level signal when the level of the input signal is lower than a predetermined logic threshold, while the inverter exceeds the predetermined logic threshold. When it is high, it outputs a low level signal,
The first inverter supplies a low-level signal to the next-stage inverter when the level on the input terminal transitions from a state lower than the first logic threshold lower than the predetermined logic threshold to a higher state. On the other hand, when the level on the input terminal exceeds the second logic threshold value higher than the predetermined logic threshold value and then transitions to a state lower than the second logic threshold value, a high level signal is sent to the next stage inverter. A semiconductor integrated device. A semiconductor integrated device in which an inverter train including m (m is an integer of 3 or more) inverters connected in series in order from upstream to downstream is formed,
The output terminal of the inverter connected to the (2n + 1) th (n is an integer equal to or greater than 1) from the upstream in the inverter train, and the input terminal of the inverter connected first from the upstream in the inverter train A resistor connected between ,
A first external terminal connected to an input terminal of the first numbered inverter,
And a second external terminal connected to an output terminal of the inverter from the upstream is connected to the (2n) th in the inverter train,
Of the m inverters, each of the inverters other than the first inverter outputs a high-level signal when the level of the input signal is lower than a predetermined logic threshold, while the inverter exceeds the predetermined logic threshold. When it is high, it outputs a low level signal,
The first inverter supplies a low-level signal to the next-stage inverter when the level on the input terminal transitions from a state lower than the first logic threshold lower than the predetermined logic threshold to a higher state. On the other hand, when the level on the input terminal exceeds the second logic threshold value higher than the predetermined logic threshold value and then transitions to a state lower than the second logic threshold value, a high level signal is sent to the next stage inverter. A semiconductor integrated device. A semiconductor integrated device in which an inverter train including m (m is an integer of 3 or more) inverters connected in series in order from upstream to downstream is formed,
The output terminal of the inverter connected to the (2 n) th (n is an integer equal to or greater than 1) from the upstream in the inverter train, and the input of the inverter connected first from the upstream in the inverter train A capacitor connected between the terminals;
A first external terminal connected to an input terminal of the first inverter;
A second external terminal connected to the output terminal of the inverter connected to the (2n + 1 ) th from the upstream in the inverter train,
Of the m inverters, each of the inverters other than the first inverter outputs a high-level signal when the level of the input signal is lower than a predetermined logic threshold, while the inverter exceeds the predetermined logic threshold. When it is high, it outputs a low level signal,
The first inverter supplies a low-level signal to the next-stage inverter when the level on the input terminal transitions from a state lower than the first logic threshold lower than the predetermined logic threshold to a higher state. On the other hand, when the level on the input terminal exceeds the second logic threshold value higher than the predetermined logic threshold value and then transitions to a state lower than the second logic threshold value, a high level signal is sent to the next stage inverter. A semiconductor integrated device .

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