JP3511753B2 - Ring oscillator and oscillation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverting amplifier circuit, a ring oscillator using a capacitance element and a resistance element, and an oscillation method.

[0002]

BACKGROUND ART AND PROBLEM TO BE SOLVED BY THE INVENTION FIG.
11 shows an example of a conventional ring oscillator, and FIG. 12 shows potential waveform diagrams of the nodes 600 and 601 of FIG. The capacitor 609 (capacitance element) is connected to the node 603-resistor 610.
(Resistive element) -charged and discharged through the path of the capacitor 609. Then, the potential V600 of the node 600 changes to the inverter 604.
When the threshold voltage Vt of the (inverting amplifier circuit) is reached, the potential at the output end of the inverter 604 is inverted. By repeating the above operation, the oscillation waveform shown in FIG. 12 is obtained.

Here, the P-side power supply potential is VDD, the N-side power supply potential is VSS (ground potential), and the first-stage inverter 604.
Vt, the capacitance value of the capacitor 609 is C, and the resistance value of the resistor 610 is R. Then, the potential of the node 600 after t time when the capacitor 609 is discharged is V600 = (Vt + VDD) × e ^A (1) [where A = −t / CR], and the potential of the node 600 during charging is , V600 = VDD− (2VDD−Vt) × e ^A (2)

Therefore, when the time from when the output of the inverter 604 is inverted to when the capacitor 609 is discharged and V600 drops to Vt is t3, t3 = CR × ln {(VDD + Vt) / Vt}. On the other hand, when the time from when the output of the inverter 604 is inverted to when the capacitor 609 is charged and V600 rises to Vt is t4, t4 = CR × ln {(2VDD−Vt) / (VDD−V
t)}. The oscillation frequency fosc of the ring oscillator is t3
And is the reciprocal of the sum of t4, fosc = 1 / (t3 + t4) = 1 / (− CR × lnB) (3) [B = Vt × (VDD−Vt) / {(VDD + Vt) ×
(2VDD-Vt)}].

Here, the threshold voltage Vt of the inverter is
The threshold voltage and the current amplification factor of Pch-Tr (P-type field effect transistor) are Vtp and βp, respectively, and Nch-
When the threshold voltage and the current amplification factor of Tr (N-type field effect transistor) are Vtn and βn, respectively, they are generally expressed by the following equation.

Vt = {Vtn + D × (VDD− | Vtp |)} / (1 + D) (4) [D = (βp / βn) ^0.5 ] However, the above expression (4) is satisfied in the inverter. Threshold values Vtp and Vt of the Pch-Tr and Nch-Tr that compose
This is a case where the following formula is established between n and the power supply potential VDD.

VDD ≧ | Vtp | + Vtn (5) From the above equation (4), if βp = βn and | Vtp | = Vtn, then Vt = VDD / 2. This Vt = VDD / 2
Is substituted into the above equation (3), the oscillation frequency becomes fosc = 1 / (2.2 × CR) (6). That is, the value of the oscillation frequency is the capacitance 609 and the resistance 61.
It is determined by the time constant of 0.

Next, the influence of variations in Vtp and Vtn on the oscillation frequency of the ring oscillator will be described. Vtp and Vtn vary due to manufacturing variations in the semiconductor manufacturing process. When the power supply potential VDD = 1.5 V and the relationship of βp = βn is maintained, Vtp = −
It is assumed that the threshold voltage varies in the range of (0.5 ± 0.2) V and Vtn = 0.5 ± 0.2V.

First, Vt is calculated by the above equation (4), and the obtained Vt is substituted into the above equation (3). | Vtp | = Vtn
In this case, even if | Vtp | and Vtn fluctuate within the range of 0.5 ± 0.2V, Vt = VDD / 2, and therefore the frequency does not fluctuate as shown in the above equation (6). On the other hand, Vtp
= -0.7V and Vtn = 0.3V, Vt = 0.5
5V, and Vt = 0.95V when Vtp = -0.3V and Vtn = 0.7V. Therefore, in these cases, | Vtp | = Vtn and Vt = VDD / 2 = 0.7
Vt fluctuates compared to the case of 5 V, and a frequency variation of about 3% occurs as calculated by the above equation (3). The influence of variations in Vtp and Vtn on this frequency tends to increase as the power supply potential decreases. For example, when the power supply potential VDD = 1.0V, the following is obtained. That is, Vt = 0.3 (Vtp = -0.7V, Vtn = 0.3)
Alternatively, Vt = 0.7V (Vtp = -0.3V, Vtn
= 0.7), Vt = VDD / 2 = 0.5V (|
Compared with the case of Vtp | = Vtn = 0.5V, there is a frequency variation of about 7% as calculated by the above equation (3). As described above, the variation in the frequency due to the variation in the threshold voltages Vtp and Vtn is about several percent.

Now, let us consider the case where the power supply potential further decreases or the Vtp and Vtn relatively rise in the conventional ring oscillator shown in FIG. Here, the conditional expressions for the ON and OFF states of the Pch-Tr and Nch-Tr are as shown in the following expressions (7) to (10).
That is, when Vin ≦ VDD− | Vtp | (7), the Pch-Tr is turned on, and when Vin> VDD− | Vtp | (8), the Pch-Tr is turned off. . Further, when Vin ≧ Vtn (9), the Nch-Tr is turned on, and when Vin <Vtn (10), the Nch-Tr is turned off.

Therefore, when VDD <| Vtp | + Vtn (11) holds, when the input potential Vin of the inverter is near the intermediate potential of the power source potential, Pch-Tr and N
It can be seen that both ch-Tr are turned off. That is,
The power supply potential drops, and the above equation (5) does not hold.
When 1) comes to hold, Pch-Tr and Nch
There may occur a case where both Tr are turned off.

For example, now, VDD = 1.0V, Vtp =
When −0.7V and Vtn = 0.7V, the range of the input potential Vin of the inverter 604 is 0.3V <Vin <
When the voltage is 0.7 V, both Pch-Tr and Nch-Tr are turned off. That is, even if the potential of the input (node 600) of the inverter 604 is near VDD / 2, the potential of the output (node 601) of the inverter is not inverted. Therefore, the oscillation frequency of the ring oscillator is
It will be different from the value shown in.

In FIG. 13, VDD = 1.0 V and Vtp =-
The potential waveform diagram of the nodes 600 and 601 in case of 0.7V and Vtn = 0.7V is shown. The oscillation frequency of the ring oscillator when the above equation (11) is satisfied is obtained using this potential waveform diagram and the like.

When the potential of the node 600 is 0V, the potential of the node 603 is 1V. Therefore, the capacitor 609 is charged in the path of the node 603-resistor 610-capacitor 609. As a result, the potential of the node 600 rises according to the following equation (12).

V600 = VDD × (1−e ^A ) ... (12) [where A = −t / CR] The potential (Vin) of the node 600 is VDD− | Vtp | =
When it reaches 0.3 V (A in FIG. 13), the above equation (7),
From (8), the Pch-Tr 607 changes from the on state to the off state, but the Nch-Tr 608 is still in the off state according to the above equation (10). During this period, since the electric charge is held in the drain capacitance of the inverter 604 and the gate capacitance of the inverter 605, the output potential of the inverter 604 is maintained at 1V. Therefore, the potentials of the node 602 and the node 603 are maintained at 0V and 1V, respectively.

When the potential of the node 600 further increases and the potential of the node 600 reaches Vtn = 0.7V (see FIG. 13).
B) and Nch-Tr 608 are turned on by the above equation (9), the potential of the node 601 is inverted from 1V to 0V (C in FIG. 13). Accordingly, the potential of the node 602 is inverted from 0V to 1V, and the potential of the node 603 is inverted from 1V to 0V.

At this time, the potential of the node 602 connected to one end of the capacitor 609 rises from 0V to 1V.
The potential of the node 600 connected to the other end of 09 rises by 1V due to capacitive coupling. As a result, the potential of the node 600 becomes Vtn + VDD = 1.7V (D in FIG. 13).

At this time, since the potential of the node 603 is 0 V, the charge of the capacitor 609 is discharged through the route of the capacitor 609-the resistor 610-node 603, and the potential of the node 600 is Vt.
It decreases from n + VDD = 1.7V according to the following equation (13).

V600 = (Vtn + VDD) × e ^A (13) When the potential of the node 600 further decreases and reaches Vtn = 0.7V (E in FIG. 13), the Nch-Tr 608 is expressed by the above equation (9). , (10) changes from the on state to the off state. However, the Pch-Tr 607 is still in the off state. During this period, the drain capacitance of the inverter 604 and the inverter 6
Since electric charge is held in the gate capacitance of 05, the potential of the node 601 is maintained at 0V, and the potentials of the node 602 and the node 603 are also maintained at 1V and 0V, respectively.

The potential of the node 600 is further reduced and VDD
When − | Vtp | = 0.3V is reached (F in FIG. 13), P
Since the ch-Tr 607 is turned on by the above formula (7), the potential of the node 601 is inverted from 0V to 1V (see FIG.
3G), and accordingly, the potential of the node 602 changes from 1V to 0.
At V, the potential of the node 603 is inverted from 0V to 1V.

Then, the potential of the node 602 changes from 1V to 0V.
Therefore, the potential of the node 600 decreases by 1V due to the capacitive coupling by the capacitor 609, and (VDD− | V
tp |) -VDD =-| Vtp | = -0.7V (H in FIG. 13).

At this time, since the potential of the node 603 is 1 V, the capacitor 609 is charged through the path of the node 603-resistor 610-capacitor 609. As a result, the potential of node 600 rises according to the following equation.

V600 = VDD− (VDD + | Vtp |) × e ^A (14) Until the potential of the node 600 reaches 0.7 V (I in FIG. 13), the potentials of the nodes 601, 602 and 603 are 1 each
It is maintained at V, 0V and 1V.

Thereafter, the operation according to the above equations (13) and (14) is repeated.

After the output of the inverter 604 is inverted,
The electric charge of the capacitor 609 is discharged and the potential of the node 600 is VD.
D- | Vtp | = Time until falling to 0.3V is t5
Then, t5 = CR × ln {(VDD + Vtn) / (VDD− |
Vtp |)}. Also, after the output of the inverter 604 is inverted,
The capacitor 609 is charged and the potential of the node 600 is Vt.
Assuming that the time required to increase to n = 0.7V is t6, t6 = CR × ln {(VDD + | Vtp |) / (VDD
-Vtn)}. The frequency fosc ′ of the signal output from the ring oscillator in FIG. 11 is represented by the reciprocal of the sum of t5 and t6, so fosc ′ = 1 / (t5 + t6) = 1 / (− CR × lnE) (15) ) [E = F × G] [F = (VDD−Vtn) / (VDD + | Vtp |)] [G = (VDD− | Vtp |) / (VDD + Vtn)].

In the above equation (15), VDD = 1.0V, Vtp
= −0.7V, Vtn = 0.7V are substituted, the frequency fosc ′ is fosc ′ = 1 / (3.469 × CR) (16). There is a 37% difference between the frequency of equation (16) above and the frequency of equation (6) above. As described above, in the conventional ring oscillator, under the condition of VDD <| Vtp | + Vtn, the oscillation frequencies have the threshold voltages Vtp and Vt.
However, there is a problem in that it fluctuates due to the influence of the manufacturing variation of n.

The present invention has been made to solve the above problems, and its purpose is to prevent the influence of manufacturing variations in the threshold voltage of transistors even when the power supply potential is lowered. It is an object of the present invention to provide a ring oscillator and an oscillating method that are hard to receive and can obtain a stable oscillation frequency with little variation.

[0028]

In order to solve the above-mentioned problems, the present invention provides an inverting amplifier circuit including a P-type field effect transistor and an N-type field effect transistor, and an inverting signal output from the inverting amplifier circuit. A ring oscillator comprising: a capacitive element for returning to an input of an inverting amplifier circuit; and a resistance element for returning a non-inverted signal of an output of the inverting amplifier circuit to an input of the inverting amplifier circuit. When both the field-effect transistor and the N-type field-effect transistor are in the off state, a setting means for setting the output of the inverting amplifier circuit to either the P-side power supply potential or the N-side power supply potential is included. To do.

For example, when the power supply potential decreases, both the P-type and N-type field effect transistors may be turned off depending on the input potential of the inverting amplifier circuit. In such a case, the following situation occurs unless the setting means of the present invention is provided. That is, when the input potential of the inverting amplifier circuit falls, the output of the inverting amplifier circuit is not inverted until the P-type field effect transistor is turned on, and when the input potential rises, the N-type field effect transistor is The output of the inverting amplifier circuit is not inverted until it is turned on. Therefore, it takes a lot of time until the output of the inverting amplifier circuit is inverted, and as a result, the oscillation frequency fluctuates greatly.

On the other hand, in the present invention, the above situation can be effectively prevented by providing the setting means. For example, if the setting means for setting the N-side power supply potential is provided, the output of the inverting amplifier circuit can be inverted when the P-type field effect transistor is turned off when the input potential of the inverting amplifier circuit rises. Further, if the setting means for setting the P-side power supply potential is provided, the output of the inverting amplification circuit can be inverted when the N-type field effect transistor is turned off when the input potential of the inverting amplification circuit falls. Therefore, the time until the output of the inverting amplifier circuit is inverted can be shortened as compared with the case where the setting means is not provided, and as a result, the fluctuation of the oscillation frequency can be effectively prevented. That is, according to the present invention, it is possible to supply a signal having a stable oscillation frequency even with a low power supply potential.

In this case, the setting means is preferably a connecting means provided between the output of the inverting amplifier circuit and the P-side power supply potential or the N-side power supply potential and having a given impedance. Further, it is more desirable that this connecting means is a resistance element. With such a configuration, the problems of the conventional example can be solved with a simple configuration.
For example, if the connecting means is formed of a diffused resistor, a polyresistor or the like, the connecting means can be formed of the same components as other circuit components, and an increase in the number of manufacturing steps can be prevented.

Further, the setting means determines the potential of the input of the inverting amplifier circuit when both the P-type field effect transistor and the N-type field effect transistor are turned off, and the output of the determination means. Based on the above, switch means for connecting or disconnecting the output of the inverting amplifier circuit and the P-side power supply potential or the N-side power supply potential may be included.

When the setting means is composed of a resistance element or the like, it is necessary to consider the balance between the resistance value of this resistance element and the capability of the transistor included in the inverting amplifier circuit. On the other hand, if the above-mentioned discrimination means is provided,
It is possible to effectively prevent the frequency fluctuation due to the blunting of the output waveform of the inverting amplifier circuit without considering such a situation.

The present invention also relates to an inverting amplifier circuit, a capacitive element for feeding back the inverted signal of the output of the inverting amplifier circuit to the input of the inverting amplifier circuit, and a normal signal of the output of the inverting amplifier circuit. A ring oscillator including a resistance element for returning to an input of an inverting amplifier circuit, wherein the inverting amplifier circuit is provided between one of a P-side power source potential and an N-side power source potential and an output of the inverting amplifier circuit. A P-type field effect transistor or an N-type field effect transistor provided, and a connecting means provided between the other power supply potential different from the one and the output of the inverting amplifier circuit and having a given impedance. Is characterized by.

For example, when the connecting means is provided between the N-side power supply potential and the output of the inverting amplifier circuit, when the input potential of the inverting amplifier circuit rises, the time when the P-type field effect transistor is turned off. The output of the inverting amplifier circuit can be inverted with. In addition, if the connection means is provided between the P-side power supply potential and the output of the inverting amplifier circuit, when the input potential of the inverting amplifier circuit falls, it is inverted when the N-type field effect transistor is turned off. The output of the amplifier circuit can be inverted. As a result, fluctuations in the oscillation frequency can be effectively prevented, and a signal with a stable oscillation frequency can be supplied even with a low power supply potential.

Further, according to the present invention, an inverting amplifier circuit, a capacitive element for feeding back the inverted signal of the output of the inverting amplifier circuit to the input of the inverting amplifier circuit, and a normal signal of the output of the inverting amplifier circuit are provided. A ring oscillator including a resistance element for feeding back to an input of an inverting amplifier circuit, the input potential at which the output of the inverting amplifier circuit is inverted when the input of the inverting amplifier circuit falls, and the inverting amplifier circuit. And a potential of the input at which the output of the inverting amplifier circuit is inverted when the input of is input rises when the power source potential supplied to the inverting amplifier circuit decreases.

According to the present invention, the input potential at which the output of the inverting amplifier circuit is inverted is substantially the same at the fall and rise of the input potential when the power supply potential is reduced. Therefore, in the present invention, the problem that occurred in the conventional example does not occur when the power supply voltage drops, and a signal with a stable oscillation frequency can be supplied even with a low power supply potential.

In the present invention, it is desirable to include a constant voltage circuit for converting a given power supply potential into a constant voltage and supplying it as the power supply potential of the inverting amplifier circuit.

When the value of the power supply potential changes, the oscillation frequency may fluctuate. However, according to the present invention, the constant power supply potential is supplied to the inverting amplifier circuit or the like. It is possible to effectively prevent such a situation and reduce the power supply potential deviation of the oscillation frequency. Further, the present invention, when combined with a constant voltage circuit, has the following special effects. That is, according to the present invention, it is possible to provide a signal having a stable oscillation frequency even when the power supply potential applied to the inverting amplifier circuit becomes low. Therefore, when the constant voltage circuit is combined, the constant voltage output by the constant voltage circuit can be set to a lower value. This means that the range of the power supply potential within which the oscillation frequency falls within the given specifications can be set lower. Thereby, for example, when the power source potential of the constant voltage circuit is supplied by a battery or the like, a battery or the like which outputs a lower power source potential can be adopted. Further, even when the power supply potential of the battery or the like decreases with the lapse of use time, it is possible to supply a stable oscillation frequency for a longer time. According to the present invention, for example, the constant voltage value output from the constant voltage circuit can be set low up to a range of a value slightly higher than the maximum absolute value of the threshold voltage of the transistor included in the inverting amplifier circuit. . That is, in the configuration in which the constant voltage circuit is combined with the conventional example, since the inverting amplifier circuit includes P-type and N-type field effect transistors, the constant voltage value is set to the P-type and N-type in order to satisfy a given oscillation frequency. Cannot be less than the sum of the threshold voltages (absolute values) of the field effect transistors of the type. On the other hand, in the present invention, the constant voltage value can be set to be equal to or less than the sum of these threshold voltages.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION The best embodiment of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is an example of a circuit diagram of a first embodiment of a ring oscillator according to the present invention, and FIG. 2 is a potential waveform diagram of nodes 100 and 101. Note that FIG. 1 shows a ring oscillator of FIG. 11 which is a conventional example with a resistor 111 added, and other circuit configurations are the same as those of FIG.

Here, the input potential of the inverting amplifier circuit, for example, the inverter 104 is Vin, Pch-Tr 107 and N.
Set the threshold voltage of ch-Tr 108 to Vtp, Vtn, P
Side and N side power supply potentials are VDD and VSS (ground potential = 0
V). The conditional expressions relating to the on and off states of the Pch-Tr and Nch-Tr are expressed by Expressions (7) to (7) to
As described in (10), for Pch-Tr, Vin ≦
ON state when VDD− | Vtp |, Vin> VDD
-| Vtp | is in the off state, Nch-Tr is Vi
When n ≧ Vtn, it is turned on, and when Vin <Vtn, it is turned off. Therefore, VDD ≧ | Vtp | + Vtn
In the range of Pch-, regardless of the value of the input potential Vin.
At least one of Tr and Nch-Tr is turned on.

In the case of VDD ≧ | Vtp | + Vtn, the impedance of the resistor 111 added in the present invention is set larger than the impedance of the Pch-Tr 107 or Nch-Tr 108 in the ON state and can be ignored. To do. Then, VDD ≧ | Vtp | + Vt
In the range of n, the frequency of the ring oscillator can be described by the same formula as the conventional example. The operation of the ring oscillator will be briefly described. In the oscillation of the ring oscillator, the capacitor 109 is charged / discharged through the path of the node 103-the resistor 110-the capacitor 109, and the potential V100 of the node 100 reaches the threshold voltage Vt of the inverter 104. At this time, this is repeated by reversing the potential at the output end of the inverter 104. Here, the threshold voltage of the inverter 104 is Vt, the capacitance value of the capacitor 109 is C, and the resistance value of the resistor 110 is R. Then V10
The potential of 0 is V100 = (Vt + VDD) × e ^A when falling (discharging) and V100 = VDD− (2VDD−Vt) × e ^A when rising (charging). Therefore, the oscillation frequency fosc of the ring oscillator of FIG. 1 is determined by the time constant of the capacitor 109 and the resistor 110, and fosc = 1 / (− CR × lnB) [B = Vt × (VDD−Vt) / {(VDD + Vt) ×
(2VDD-Vt)}].

When the current amplification factors of Pch-Tr and Nch-Tr are βp and βn, respectively, the threshold voltage Vt of the inverter is expressed by the following equation.

Vt = {Vtn + D × (VDD- | Vtp
|)} / (1 + D) [D = (βp / βn) ^0.5 ] If βp = βn and | Vtp | = Vtn in the above equation, Vt
= VDD / 2, and the oscillation frequency fosc is fosc = 1 / (2.2 × CR). For example, when the resistance value of the resistor 110 is 346.8 K ohms and the capacitance value of the capacitor 109 is 40 PF, the frequency fosc = 1 / (2.2 × CR) = 32.77 kH
z, and the cycle is about 30.5 usec.

In the case of VDD <| Vtp | + Vtn In the case of VDD <| Vtp | + Vtn, the inverter 104
Depending on the value of the input potential Vin of Pch-Tr107
There is a case where both the Nch-Tr 108 and the Nch-Tr 108 are turned off. For example, VDD = 1.0V, Vtp = −0.7
Consider the case where V and Vtn = 0.7V. Initially, when the potential of the node 100 is 0V, the potential of the node 103 becomes 1V, so that the capacitor 109 is connected to the node 103-the resistor 1
It is charged by the path of 10-capacity 109. As a result, the potential of the node 100 becomes V100 = VDD × (1−e ^A ) ... (12) [where A = −t / CR] and gradually increases (J in FIG. 2). Here, in the present invention, the resistance value of the resistor 111 is a value that can be ignored as compared with the on-resistance of the Pch-Tr 107.

The potential of the node 100 is 0.3V to 0.7V
In the section that becomes, Pch-Tr107 and Nch
Both -Tr108 will be in an OFF state. In the present invention, a resistor 1 is provided between the node 101 and the N-side power supply potential (ground potential).
11 is connected. Therefore, the potential of the node 100 rises from 0 V to 0.3 V (K in FIG. 2), and Pch-
When Tr is turned off, the potential of the node 101 is discharged to the 0V side with a time constant determined by the resistor 111 and the load capacitance of the node 101, and is inverted from 1V to 0V (L in FIG. 2). The discharge time constant at this time is 700 K ohms for the resistance value of the resistor 111 and 0.5 PF for the load capacitance of the node 101.
Then, it becomes 350 nsec, which is about 1% of the period of the ring oscillator calculated above. This node 1
The potential of the node 102 changes from 0V to 1V according to the change of 01.
Then, the potential of the node 103 is inverted from 1V to 0V.

At this time, since the potential of the node 102 connected to one end of the capacitor 109 rises from 0V to 1V, the capacitance 1
Due to the capacitive coupling by 09, the potential of the node 100 connected to the other end of the capacitor 109 rises by 1 V, and (VDD−
| Vtp |) + VDD = 2VDD− | Vtp | = 1.3
V (M in FIG. 2). The potential of the node 103 is 0
Since it is V, the charge of the capacitor 109 is the capacitor 109-the resistor 1
10-Discharge on the path of the node 103, and the potential V100 of the node 100 decreases from 1.3V according to the following equation.

V100 = ((VDD− | Vtp |) + VDD) × e ^A = (2VDD− | Vtp |) × e ^A (17) When the potential of the node 100 decreases to 0.7 V, Nc
The h-Tr 108 changes from the on state to the off state, as is apparent from the above equations (9) and (10). However, Pch
-Tr107 is still off, and node 101 and N
Since the resistor 111 is connected to the side power supply potential, the potential of the output terminal 101 of the inverter 104 remains 0V. Therefore, the potentials of the nodes 102 and 103 remain 1V and 0V, respectively.

The potential of the node 100 is further reduced to 0.3 V
(N in FIG. 2), the Pch-Tr 107 changes from the off state to the on state as is clear from the above equations (7) and (8). If the impedance of the Pch-Tr 107 in the ON state is set sufficiently lower than that of the resistor 111,
The potential of the node 101 is inverted from 0V to 1V (O in FIG. 2). As a result, the potential of the node 102 changes from 1V to 0V.
Then, the potential of the node 103 is inverted from 0V to 1V.

At this time, since the potential of the node 102 connected to one end of the capacitor 109 is reduced from 1V to 0V, the potential of the node 100 connected to the other end of the capacitor 109 is 1V due to capacitive coupling by the capacitor 109. Decrease (VDD−
| Vtp |) -VDD =-| Vtp | = -0.7V (P in FIG. 2). Since the potential of the node 103 is 1 V, the capacitor 109 is charged through the path of the node 103-resistor 110-capacitor 109. As a result, the node 100
Potential rises according to the following equation (18).

V100 = VDD− (VDD + | Vtp |) × e ^A (18) Until the potential of the node 100 reaches 0.3 V (Q in FIG. 2), the potentials of the nodes 101, 102 and 103 are 1 each
It is maintained at V, 0V and 1V.

Thereafter, the operation according to the above equations (17) and (18) is repeated. Here, when the time from when the output of the inverter 104 is inverted to when the capacitance 109 is discharged and the potential of the node 100 drops to VDD− | Vtp | = 0.3V is t1, t1 = CR × ln {(2VDD -| Vtp |) / (VD
D- | Vtp |)}. Also, after the output of the inverter 104 is inverted,
Assuming that the time required for charging the capacitor 109 and raising the potential of the node 100 to 0.3 V is t2, t2 = CR × ln {(VDD + | Vtp |) / | Vtp
|}. Oscillation frequency of ring oscillator fosc ''
Is the reciprocal of the sum of t1 and t2, so fosc ″ = 1 / (t1 + t2) = 1 / (− CR × lnH) (19) [H = I × J] [I = | Vtp | / (VDD + | Vtp |)] [J = (VDD- | Vtp |) / (2VDD- | Vtp
|)].

In the above equation (19), VDD = 1.0V, Vtp
= −0.7V is substituted, the frequency fosc ″ is fosc ″ = 1 / (2.354 × CR) (20). This equation (20) is VDD <| Vtp | + Vt
This is an equation that holds when n. On the other hand, VDD ≧ | Vtp
In the range of | + Vtn, the frequency is fosc = 1 / (2.2 × CR) (6) as described above. Therefore, the shift of fosc ″ from the desired frequency fosc ″ is about 7%.

On the other hand, in the conventional example, VDD <| Vtp | +
In the range of Vtn, the frequency fos of the ring oscillator is
c ′ was fosc ′ = 1 / (3.469 × CR) (16), and the deviation of fosc ′ from fosc (the above formula (6)) was about 37%. Therefore, according to the present invention,
By connecting the resistor 111 between the N-side power supply potential and the node 101, the fluctuation of the frequency of the ring oscillator due to the fluctuation of Vtp and Vtn can be greatly reduced from 37% of the conventional example to 7%.

In the above, the N side power source potential (ground potential)
Although the example in which the resistor 111 is connected between the node 101 and the node 101 has been described, the same effect can be obtained by connecting the resistor 111 between the P-side power supply potential and the node 101 instead. FIG. 3 shows a potential waveform diagram of the nodes 100 and 101 in this case. Thus, in this embodiment, the P of the inverter 104 is
When both the ch-Tr 107 and the Nch-Tr 108 are in the off state, the node 101 is rapidly discharged or charged, so that the inverter at the next stage is quickly inverted.

FIG. 4 shows the cases of VDD ≧ | Vtp | + Vtn and VDD <| Vtp | + Vtn.
The fall time tf, the rise time tr, and the oscillation frequency f obtained in the conventional example and the present example are shown together. Figure 4
As is clear by comparing the S1 column and the S2 column, in the present embodiment, t is in the range of VDD <| Vtp | + Vtn.
Both f and tr are improved as compared with the conventional example, and therefore the frequency fluctuation is also greatly improved. The fact that the fall time (discharge time) tf is improved can be seen in a comparison between D of FIG. 13 and M of FIG.
This is because the potential of V100 at the time of starting discharge is smaller than that in the conventional example. In the conventional example, this is B in FIG.
As shown in C, V601 is inverted at V600 = 0.7V, whereas in the present embodiment, V101 is inverted at V100 = 0.3V as shown at K and L in FIG. On the other hand, the rise time (charging time) tr is improved, as is clear by comparing I in FIG. 13 and Q in FIG.
This is because the potential of 0 is 0.3V, which is smaller than 0.7V of the conventional example.

As is clear from the above consideration, the frequency variation is improved by this embodiment for the following reason.
That is, even when the power supply potential is lowered, the input potential (the threshold voltage of the inverter) at which the output of the inverter 104 is inverted is substantially the same when the input potential falls and when it rises. For example, in the conventional example, as shown in FIG. 13, the threshold voltage of the inverter at the time of falling and rising of the input is 0.3, respectively.
V and 0.7V, which are different. On the other hand, in the present embodiment, as shown in FIG. 2, the threshold voltage of the inverter is 0.3V (0.7V in the case of FIG. 3) at both the fall and rise of the input. ing. As a result, frequency fluctuations when the power supply potential drops can be greatly improved.

Setting of the resistance R, etc. Now, in this embodiment, the time constant determined by the resistance value of the resistance 111 and the load capacitance of the node 101 is used.
Promptly discharge the potential of 1 to the N side power source potential (= 0V),
Alternatively, it is preferable to quickly charge the P-side power supply potential (= VDD), and the time constant of discharging or charging at this time is preferably sufficiently smaller than the cycle of the ring oscillator. For this purpose, it is desirable to reduce the load capacitance of the node 101 and further reduce the impedance of the resistor 111 added in this embodiment. On the other hand, Pch-T
It is preferable to set the impedance of the resistor 111 added in this embodiment to be larger than the impedance of the r107 or the Nch-Tr 108 in the ON state.
As described above, the resistance value of the resistor 111 must be determined in consideration of the balance with the transistor capability of the inverter 104.

An example of the actual value of each parameter in this embodiment set in consideration of these points is shown below.

When the resistance value R of the resistor 110 is 346.8 K ohms and the capacity value C of the capacitor 109 is 40 PF, the frequency of the ring oscillator is fosc = 1 / (2.2 × C).
R) = 32.77 kHz, and the cycle is 30.5u
It will be about sec. The power supply potential is VDD = 1.0 V, and the variation range of the threshold voltage of Pch-Tr 107 and Nch-Tr 108 is Vtp =-(0.5 ± 0.2).
V, Vtn = 0.5 ± 0.2 V, Pch-Tr10
7 and Nch-Tr108 current amplification factors, βp =
80 μA / V ² and βn = 80 μA / V ² . Further, by setting the resistance value of the resistor 111 to 700 K ohms and the load capacitance of the node 101 to 0.5 PF, these resistance values,
The time constant determined by the capacitance value is set to 350 nsec and set to about 1% of the cycle of the ring oscillator. With the above settings, the fluctuation of the frequency of the ring oscillator
As mentioned above, the reduction was possible from 7% to about 7%.

Next, with reference to FIG. 5, the influence of the change in the resistance value of the resistor 111 on the oscillation frequency will be described. First, a case where the resistance value of the resistor 111 is too large will be described. For example, Pch-Tr107 and Nch-Tr108
Let us consider a case in which both are in the off state, and the charges charged in the load capacitance of the node 101 (the drain capacitance of the inverter 104, the gate capacitance of the inverter 105, etc.) are discharged through the resistor 111. In this case, if the time constant of this discharge is large, the potential waveform of the node 101 becomes dull as shown by 200 in FIG. The greater the resistance value of the resistor 111, the greater the degree of the dullness. Therefore node 10
The time until the potential of 1 reaches the threshold voltage of the inverter 105 is deviated, and the timing at which the output of the inverter 105 is inverted is delayed. This reduces the oscillation frequency. Specifically, when the load capacitance is 0.5 PF, the resistor 111 is formed of a diffused resistor and the center value of the resistor is 700 K ohms, when the resistance value increases to 5000 K ohms, the frequency becomes about 30.1 kHz, The frequency decreases by about 8%.

On the other hand, when the resistance value of the resistor 111 is reduced, it becomes as follows. That is, in this case, node 1
Even when the potential of 00 is close to the threshold voltage of Pch-Tr 107, P is compared with the impedance of the resistor 111.
Since the ch-Tr 107 has a high impedance, the node 101 does not invert. Then, only when the potential of the node 100 further decreases and the impedance of the Pch-Tr 107 becomes small until it becomes equal to the resistance 111,
The node 101 is inverted. As a result, as shown by 201 in FIG. 2, the potential waveform of the node 101 becomes dull (delayed). As a result, the time until the potential of the node 101 reaches the threshold voltage of the inverter 105 is deviated, and the oscillation frequency of the ring oscillator becomes small. In particular,
When the load capacitance is 0.5 PF, the resistor 111 is formed of a diffused resistor, and the center value of the resistor is 700 K ohms, when the resistance value is reduced to 100 K ohms, the frequency is 30.
The frequency becomes 2 kHz, and the frequency decreases by about 7%.

As described above, the resistance value of the resistor 111 must be determined in consideration of the balance with the transistor capability of the inverter 104. The same applies when a resistor or the like is connected between the P-side power supply potential and the node 101.

(Second Embodiment) FIG. 6 shows a circuit configuration example of a second embodiment of the present invention. In the first embodiment shown in FIG. 1, Pc
There is a need to set the impedance of the resistor 111 larger than the impedance of the h-Tr 107 or the Nch-Tr 108 in the ON state. The second embodiment is for eliminating the need for such setting. Therefore, in this embodiment, the Pch-Tr 107, Nc
There are provided means (monitor circuit) for determining the input potential of the inverter when both the h-Tr 108 are in the off state, and switch means, for example, Nch-Tr, which is on / off controlled by the output of the determination means.

The second embodiment will be specifically described below with reference to FIG. The monitor circuit 411 is a Pch-Tr40.
7 and Nch-Tr 408 are both off, N
Nch-Tr41 for the gate part of ch-Tr412
It outputs a signal for turning ON the No. 2 signal. Figure 7
A configuration example of this monitor circuit 411 is shown in FIG. Nch-
The Tr502 has substantially the same threshold voltage as the Nch-Tr 408 shown in FIG. 6, and the Pch-Tr 503 has the Pch-Tr 403.
-It has substantially the same threshold voltage as Tr407. Inverter 505 outputs the inverted potential of node 507 to node 510. NOR gate 506 has nodes 508, 5
When 10 is connected and both nodes 508 and 510 are at the VSS level (= 0V), the VDD level is output. The node 500 of FIG. 7 corresponds to the node 400 of FIG. 6 (input of the monitor circuit 411), and the node 509 of FIG. 7 corresponds to the node 413 of FIG. 6 (output of the monitor circuit 411). Nc
When the h-Tr 408 is in the off state, the Nch-Tr 502
Since the threshold voltage of is substantially the same as that of Nch-Tr 408, Nch-Tr 502 is also turned off. At this time, the node 507 is connected to the P-side power supply potential VDD via the resistor 501.
Connected to the node 507, the potential of the node 507 becomes VDD level. Similarly, when the Pch-Tr 407 is off, the threshold voltage of the Pch-Tr 503 is Pch-Tr 503.
Since it is substantially the same as 407, the Pch-Tr 503 is also turned off. At this time, since the node 508 is connected to the N-side power supply potential VSS via the resistor 504, the node 5
The potential of 08 becomes VSS level.

Therefore, Nch-Tr 408 and Pch-T
When both r407 are off, nodes 507 and 508
Potentials are VDD and VSS levels, respectively. The potential of the node 510 is inverted by the inverter 505 to V
Since it becomes the SS level, the output node 509 of the NOR gate 506, that is, the output node 413 of the monitor circuit 411.
Becomes VDD level. As a result, the Nch-Tr 412 is turned on, and the output node 401 of the inverter 404 is
Potential becomes VSS level.

With the above arrangement, in the second embodiment, the impedance of the Nch-Tr 412 that performs the same function as the resistance 111 can be made sufficiently smaller than the impedance of the resistance 111 in the first embodiment. . By this, Nch-Tr408 and Pch-Tr407
When both are in the off state, the discharge time constant of the node 401 determined by the impedance of the Nch-Tr 412 and the load capacitance of the node 401 can be reduced.

By thus generating the control signal by the monitor circuit 411 and short-circuiting the output of the inverter 404 to the power supply potential on the P side or the N side, the same effect as when the resistor is connected can be obtained. Moreover, in the first embodiment, it was necessary to consider the balance between the transistor capacity of the inverter 104 and the resistance value of the resistor 111, but in the second embodiment, this is not necessary, and the waveforms shown by 200 and 201 in FIG. It is possible to eliminate the frequency error due to the bluntness of.

(Third Embodiment) FIG. 8 shows a circuit configuration example of the third embodiment of the present invention. The difference from the first embodiment is the circuit configuration of the first-stage inverter 304. In the third embodiment, unlike the first embodiment shown in FIG. 1, the Nch-Tr10 is
The resistor 308 is provided instead of the resistor 8
Is omitted. With this configuration, even when the power supply potential is lowered, the input potential (the threshold voltage of the inverter 304) at which the output of the inverter 304 is inverted can be made substantially the same at the fall and rise of the input potential. The same effect as that of the first embodiment can be obtained.

Next, regarding the operation of the third embodiment, VDD =
A brief description will be given by taking the case of 1.0 V, Vtn = 0.7 V, and Vtp = −0.7 V as an example. The potential of node 300 is 0
When the voltage is V, the Pch-Tr 307 is in the ON state, and the potential of the node 301 becomes 1V, so that the potential of the node 303 also becomes 1V. Therefore, the capacity 309 is the node 303
-The resistor 310 and the capacitor 309 are charged in the path. As a result, the potential of the node 300 gradually rises according to the above equation (12).

When the potential of the node 300 becomes 0.3 V,
The Pch-Tr 307 is turned off. At this time, the resistance 3
If the impedance of 08 is set sufficiently lower than the impedance of the Pch-Tr 307 when it is off, the potential of the node 301 becomes equal to the resistance value of the resistor 308 and the node 30.
It is discharged to the 0V side with a time constant determined by the load capacity of 1.
Invert from 1V to 0V. This changes the potential of the node 302 from 0V to 1V and the potential of the node 303 from 1V to 0V.
Invert to V. Then, the potential of the node 300 rises by 1 V due to capacitive coupling by the capacitor 309, and (VDD−
| Vtp |) + VDD = 2VDD− | Vtp | = 1.3
It becomes V. Then, the electric charge of the capacitor 309 is discharged through the path of the capacitor 309-the resistor 310-the node 303, and the node 30
The zero potential decreases according to equation (17) above.

When the potential of the node 300 decreases and reaches 0.3 V, the Pch-Tr 307 changes from the off state to the on state. If the impedance of the Pch-Tr 307 in the ON state is set sufficiently lower than that of the resistor 308,
The potential of the node 301 is inverted from 0V to 1V. This changes the potential of the node 302 from 1V to 0V,
The potential of 3 is inverted from 0V to 1V. Then, capacity 30
Due to the capacitive coupling by 9, the potential of the node 300 decreases by 1 V, and (VDD− | Vtp |) −VDD = − | Vtp |
= -0.7V. Then, the electric charge of the capacitor 309 is charged through the path of the node 303-the resistor 310-the capacitor 309. As a result, the potential of the node 300 rises according to the above equation (18).

Until the potential of the node 300 reaches 0.3 V, the potentials of the nodes 301, 302 and 303 are 1 each.
It is maintained at V, 0V and 1V. After that, by repeating the above operation, a desired oscillation signal is obtained. The obtained oscillating frequency is similar to that of the above equation (19).

In the first embodiment described above, when the potential of the output of the first stage inverter is inverted from 1V to 0V, N
Although both the ch-Tr 108 and the resistor 111 are used, only the resistor 308 is used in the third embodiment. Therefore, especially when the power supply potential applied to the ring oscillator is sufficiently high, the first embodiment, which can quickly invert the potential of the node 101 from the power supply potential VDD to the ground potential VSS, is better than the third embodiment. It has an advantageous configuration.

In the third embodiment, the resistor 308 is used to invert the potential of the node 301 from 1V to 0V, but other than this, for example, a depletion type field effect transistor, a gate electrode and a drain region are connected. Various connecting means such as the field effect transistor described above can be used.

Further, in the third embodiment, the resistor serving as the connecting means is provided between the output of the inverter 304 and the N-side power supply potential VSS. On the contrary, the output of the inverter 304 and P
A connection means may be provided between the power supply potential VDD and the side power supply potential VDD.

(Fourth Embodiment) FIG. 9 shows a circuit configuration example of a fourth embodiment of the present invention. In the fourth embodiment, a constant voltage circuit 150 is added to the first embodiment. This constant voltage circuit 1
Reference numeral 50 is for making a given power supply potential VDD ′ a constant voltage and supplying this to the inverter 104 and the like as a power supply potential VDD.

The constant voltage circuit 150 includes a reference voltage generating circuit 152 for generating a reference voltage Vref, an operational amplifier (operational amplifier) 154, and a Pch which is a transistor for a driver.
-Tr156, resistors 158 and 1 having resistance values R1 and R2
Including 60. The reference voltage Vref is input from the reference voltage generation circuit 152 to the inverting input terminal of the operational amplifier 154. The constant voltage circuit 1 is connected to the non-inverting input terminal of the operational amplifier.
A potential obtained by dividing the output Vr (= VDD) of 50 by the resistors R1 and R2 is input. The operational amplifier 154 operates so as to equalize the potential of the inverting input terminal and the potential of the non-inverting input terminal. Therefore, Vr = {(R1 + R2) / R2} × V
The relational expression of ref is established. The gate voltage of the Pch-Tr 156 is controlled by the output of the operational amplifier 154, which allows the inverter 104 to have a constant power supply potential V.
r is supplied.

By thus providing the constant voltage circuit 150, it is possible to reduce the power supply potential deviation of the oscillation frequency of the ring oscillator. That is, the oscillation frequency of the ring oscillator is affected to a large extent by the fluctuation of the power supply potential to be supplied. When the power supply potential is high, the oscillation frequency is relatively high, and when the power supply potential is low, the oscillation frequency is low. According to the present embodiment, since the power supply potential VDD which has been made constant by the constant voltage circuit 150 is given to the inverter 104 and the like,
The power supply potential deviation of such an oscillation frequency can be made extremely small.

As described above, in the conventional ring oscillator shown in FIG. 11, the oscillation frequency fluctuates significantly when the power supply potential VDD becomes small and VDD≤Vtn + │Vtp│. Therefore, the power supply potential VDD is changed to Vt
It was practically impossible to make it to be n + | Vtp | or less. Then, the power supply potential VDD ′ given to the constant voltage circuit 150
Must be greater than VDD, so even if the constant voltage circuit 150 is added to the configuration of the conventional example,
This means that VDD 'cannot be set to Vtn + | Vtp | or less. For example, the manufacturing variations of Vtn and Vtp are Vtn = 0.5 ± 0.2V, Vtp = − (0.5 ±
Consider the case of 0.2) V. Then, considering the manufacturing variations of other elements and noise, etc.
As shown in 0 (A), for example, the power supply potential VDD ′ is 2.
The oscillation frequency deviation does not fall within the specifications when it becomes approximately 0 V or less.

On the other hand, in this embodiment, as described above, the oscillation frequency does not change so much even in the range of VDD ≦ Vtn + │Vtp│. Therefore, as shown in FIG. 10B, the oscillation frequency deviation can be kept within the specifications until the power supply potential VDD ′ becomes about 1.0 V, for example. That is, the lower limit voltage of the operating range of the ring oscillator can be made lower. More generally, when the conventional example is used, the constant voltage Vr output from the constant voltage circuit 150 cannot be set to about Vtn + | Vtp | or less. On the other hand, in this embodiment, Vtn + | V
tp | or less, and at least | Vtp | or Vt
The constant voltage Vr can be set in a range larger than n.

The ring oscillator is sometimes used in batteries, ICs driven by batteries (melody ICs, etc.), portable electronic devices, etc. In this case, the power supply potential V
DD 'is supplied by a battery or the like. According to this embodiment,
Even if the power supply potential VDD ′ becomes low, the oscillation frequency deviation can be kept within the specifications, so that the lower power supply potential V
It is possible to use a battery or the like that supplies DD '. Then, by lowering the power supply potential VDD ', power consumption can be reduced.

The power supply potential supplied from a battery or the like generally decreases with the lapse of usage time. Therefore,
For example, when a battery or the like having an output of 2.5 V in an unused state is used, in the conventional ring oscillator, the oscillation frequency fluctuates greatly when VDD ′ becomes, for example, about 2.0 V or less, and the ring oscillator becomes inoperable. Will end up. As a result, the battery drive time is very short. On the other hand, in this embodiment, V
Since the oscillation frequency deviation can be kept within the specifications until DD 'becomes about 1.0 V, the battery driving time can be lengthened.

In the fourth embodiment, the case where the constant voltage circuit 150 is combined with the first embodiment has been described, but the constant voltage circuit 150 may be combined with the second and third embodiments. Further, in the fourth embodiment, the P-side power supply potential VDD is supplied by the constant voltage circuit 150, but the N-side power supply potential VSS may be supplied by the constant voltage circuit 150.

The configuration of the constant voltage circuit 150 is not limited to that shown in FIG. However, according to the configuration shown in FIG. 9, the constant voltage can be supplied until VDD ′ and Vr (= VDD) become substantially equal. Therefore, the constant voltage circuit 150 configured as shown in FIG. 9 has an advantage that the range of the power supply potential VDD ′ in which the oscillation frequency deviation falls within the specifications can be widened.

The present invention is not limited to the above first to fourth embodiments, and various modifications can be made within the scope of the gist of the present invention.

For example, when both Nch-Tr and Pch-Tr are off, the output of the first-stage inverting amplifier circuit is set to P.
The method of setting the side or N-side power supply potential is not limited to that described in the first embodiment, and the present invention includes a range equivalent thereto. For example, the resistor 111 may be configured by a field effect transistor or the like instead of the diffused resistor or the like. Further, the method of using the discriminating means (monitor circuit) is not limited to that described in the second embodiment. For example, the switch means in the second embodiment may be constituted by a switch means such as a bipolar transistor instead of a field effect transistor, or a resistance element may be inserted in series with the switch means. In addition to the configurations described in the first to fourth embodiments, various configurations can be considered as a configuration for implementing the method of the present invention. As such a configuration, for example, when the power supply potential drops, the input potential at which the output of the inverting amplifier circuit is inverted is
Another configuration is conceivable in which the input potential is substantially the same when the input potential falls and when the input potential rises.

As a basic configuration of the ring oscillator,
The use of configurations other than those described in the first to fourth embodiments is also included in the equivalent scope of the present invention. For example, an element for controlling oscillation stop or the like may be provided in the inverting amplifier circuit.

In the above first to fourth embodiments, the case where the inverting amplifier circuit has three stages has been described. However, in the present invention, in general, the inverting amplifier circuits are connected in series in 2n + 1 stages (n ≧ 1),
The output of the 2m (0 <m ≦ n) th stage inverting amplifier circuit is fed back to the input of the first stage inverting amplifier circuit via the capacitive element, and 2k
It can also be applied to a ring oscillator having a configuration in which the output of the +1 (m ≦ k ≦ n) th stage inverting amplifier circuit is fed back to the input of the first stage inverting amplifier circuit via a resistance element. The present invention provides at least a capacitive element for feeding back the inverted signal of the output of the inverting amplifier circuit of the first stage to the input of the inverting amplifier circuit, and a normal signal of the output of the inverting amplifier circuit is fed back to the input of the inverting amplifier circuit. Any element including a resistance element for

[0091]

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration example of a ring oscillator according to a first embodiment of the present invention.

FIG. 2 is a potential waveform diagram at nodes 100 and 101.

FIG. 3 shows a node 10 when a resistor is connected to VDD side.
It is a potential waveform diagram in 0 and 101.

FIG. 4 is a diagram for comparing and explaining an oscillation frequency and the like of a conventional example and this example.

FIG. 5 is a diagram showing a relationship between an oscillation frequency of a ring oscillator and a resistance value.

FIG. 6 is a diagram showing a circuit configuration example of a ng oscillator according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration example of a monitor circuit.

FIG. 8 is a diagram showing a circuit configuration example of a ng oscillator according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a circuit configuration example of a ng oscillator according to a fourth embodiment of the present invention.

10A and 10B are diagrams showing a relationship between a power supply potential and an oscillation frequency.

FIG. 11 is a diagram showing a circuit configuration example of a conventional ring oscillator.

FIG. 12 is a potential waveform diagram at nodes 600 and 601.

FIG. 13 is a potential waveform diagram at nodes 600 and 601 in the case where the power supply potential is reduced and the like.

[Explanation of Codes] 107, 156, 307, 407, 503, 607
Pch-Tr 108, 308, 408, 502, 608
Nch-Tr 104-106, 304-306, 404-406, 5
05, 604-606 Inverters 110, 111, 158, 160, 308, 310, 4
10, 501, 504, 610 Resistors 109, 309, 409, 609
Capacity 411
Monitor circuit 150 Constant voltage circuit 152 Reference voltage generation circuit 154 Operational amplifier

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 3/354 H03K 3/03

Claims (11)

(57) [Claims] 1. An inverting amplifier circuit including a P-type field effect transistor and an N-type field effect transistor, a capacitive element for feeding back an inverted signal of an output of the inverting amplifier circuit to an input of the inverting amplifier circuit, and the inverting circuit. A ring oscillator including a resistance element for returning a normal signal of an output of an amplifier circuit to an input of the inverting amplifier circuit, wherein both the P-type field effect transistor and the N-type field effect transistor are in an off state. The ring oscillator, further comprising setting means for setting the output of the inverting amplifier circuit to either the P-side power supply potential or the N-side power supply potential. 2. The setting means according to claim 1, wherein the setting means outputs the output of the inverting amplifier circuit and the P-side power supply potential or the N-side power supply potential.
A ring oscillator, characterized in that it is a connecting means having a given impedance provided between a side power supply potential and the side power supply potential. 3. The ring oscillator according to claim 2, wherein the connecting means is a resistance element. 4. The determination means according to claim 1, wherein the setting means determines the potential of the input of the inverting amplifier circuit when both the P-type field effect transistor and the N-type field effect transistor are turned off. A ring oscillator comprising: a switch means for connecting or disconnecting the output of the inverting amplifier circuit and the P-side power supply potential or the N-side power supply potential based on the output of the determining means. 5. An inverting amplifier circuit, a capacitive element for feeding back the inverted signal of the output of the inverting amplifier circuit to the input of the inverting amplifier circuit, and a normal signal of the output of the inverting amplifier circuit. And a resistance element for feeding back to the input of the inverting amplifier circuit, wherein the inverting amplifier circuit is provided between one of the P-side power source potential and the N-side power source potential and the output of the inverting amplifier circuit. A P-type field-effect transistor or an N-type field-effect transistor; and a connecting means having a given impedance, which is provided between the other power supply potential different from the one and the output of the inverting amplifier circuit. Ring oscillator to 6. An inverting amplifier circuit, a capacitive element for feeding back an inverting signal of the output of the inverting amplifier circuit to an input of the inverting amplifier circuit, and a normal signal of the output of the inverting amplifier circuit. A ring oscillator including a resistance element for feeding back to the input of the inverting amplification circuit, the input potential at which the output of the inverting amplification circuit is inverted when the input of the inverting amplification circuit falls, and the input of the inverting amplification circuit. A ring oscillator, comprising means for making the potential of an input at which the output of the inverting amplifier circuit rises at the time of rising substantially the same when the power source potential supplied to the inverting amplifier circuit is lowered. 7. The ring oscillator according to claim 1, further comprising: a constant voltage circuit which converts a given power supply potential into a constant voltage and supplies it as a power supply potential of the inverting amplifier circuit. 8. An inverting signal output from an inverting amplifier circuit including a P-type field effect transistor and an N-type field effect transistor is fed back to the input of the inverting amplifier circuit by using a capacitive element, and the output of the inverting amplifier circuit is positive. An oscillating method for obtaining an oscillating signal by feeding back an inverted signal to an input of the inverting amplifier circuit using a resistance element, wherein both of the P-type field effect transistor and the N-type field effect transistor are in an off state, An oscillating method characterized in that the output of the inverting amplifier circuit is set to one of a P-side power source potential and an N-side power source potential. 9. An inverting signal output from the inverting amplifier circuit is fed back to the input of the inverting amplifier circuit using a capacitive element, and a normal signal output from the inverting amplifier circuit is fed back to the input of the inverting amplifier circuit using a resistance element. An oscillating method for obtaining an oscillating signal by feeding back to an input, comprising: using a P-type or N-type field effect transistor, one of a P-side power supply potential and an N-side power supply potential and an output of the inverting amplifier circuit. Characterized by connecting or disconnecting between the two, and using a connecting means having a given impedance to connect between the power supply potential on the P side or the N side different from the one and the output of the inverting amplifier circuit. And the oscillation method. 10. An inverting signal output from the inverting amplifier circuit is fed back to the input of the inverting amplifier circuit by using a capacitive element, and a non-inverted signal output from the inverting amplifier circuit is output by using a resistor element. An oscillating method for obtaining an oscillating signal by feeding back to the input, wherein the input potential at which the output of the inverting amplifier circuit is inverted when the input of the inverting amplifier circuit falls and the input potential of the inverting amplifier circuit rises. In the oscillation method, the input potential at which the output of the inverting amplifier circuit is inverted is made substantially the same when the power supply potential supplied to the inverting amplifier circuit is lowered. 11. The oscillating method according to claim 8, wherein a given power supply potential is converted into a constant voltage and supplied as a power supply potential of the inverting amplifier circuit.