JPS5817723A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To prevent instability of oscillation frequency caused by the dispersion of protective resistors at semiconductor manufacturing process, by providing a limit resistor to a capacitance positive feedback circuit to an input terminal of an inverter of the 1st stage. CONSTITUTION:In an oscillation circuit consisting a plurality of inverters 11-13 in series connection, a resistor Rx is provided between a capacitor C charged/ discharged with an input signal (d) of the inverter 13 and an input terminal A. The resistance value of this resistor Rx is set to limit the voltage range of an input signal (a) of the inverter 11 within a power supply voltage VDD-Vss. If the signal (d) goes to 1 level, the voltage of the signal (a) rises to 1 level momentarily but this voltage is lower than the voltage VDD. Thus, the current path to the input protection circuit of the inverter 11 can not be formed. On the other hand, when the signal (d) changes from 1 to 0 level, the voltage of the signal (a) is higher than the voltage VSS. Thus, no current path to the circuit 31 can be formed. Then, no effect is given by protection resistors Rs1 and Rs2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation circuit that improves element variation Km (frequency instability) resulting from a 4IK semiconductor manufacturing process.

The /4 pulse generating circuit is one of the important circuits in electronic circuits, as it serves as a circuit operation source for electronic devices. This /f
Although various circuits have been proposed as pulse generating circuits, CB oscillation circuits are often used because they have many advantages such as a simple configuration and high integration. This CR oscillation circuit (
The oscillation circuit (hereinafter simply referred to as an oscillation circuit) is a circuit that generates a nof pulse with a frequency determined by the time constant of the °C/4 capacitor and the resistor. Conventionally, such an oscillation circuit consists of multiple stages of impurities 11.11 connected in K11 rows as shown in Fig. 1.
ell, each of these Inno Parables 11.12.11 usually consists of complementary MO8) Lanzoster circuits. Further, in the inverter 11 to JjD connected to the inverter 1, a capacitor C is provided which charges or discharges in response to the input signal dic of the inverter 13 at the output stage. The terminals are connected to form a capacitive positive feedback circuit. The input terminal of the first stage inverter 110 is
It is connected to the output terminal of the output stage inverter IJ via a resistor 8, forming a resistor negative feedback circuit. The voltage a at the input terminal of the first-stage inverter 11 changes depending on the time constant of this resistor R and the four-stage inverter C.

In such an oscillation circuit, each inverter 11 to IJ
The power supply voltage supplied by K is assumed to be VDII (rlJ level hereinafter)-Was (hereinafter referred to as "0" level), and the circuit threshold of each inverter 11 to 13, that is, the complementary M08 transistor circuit is assumed to be voltage Vthc. Then, if the input signal 4 of inverter IJ is at the "1" level, the output signal
When becomes the "0" level, the input signal 1 of the first stage inverter 11 becomes the instantaneous rlJ level, as shown in Figure 2.
That is, it rises at (Van +Vthe-Vss)Ki, and therefore its output signal is at the "0" level.

Immediately after that, the capacitor C enters the discharge state due to the current path consisting of the inverter-ISO input terminal (V, ), the capacitor C, the input terminal of the inverter 11, the resistor R, and the output terminal (Vmm) of the inverter 11. , the input signal aO voltage begins to decrease. When this input signal aO voltage decreases by the circuit threshold voltage vth@t of the inverter 11,
f--11 performs an inversion operation and its output signal changes from the rOJ level to the rlJ level. Therefore, Imper Yu 13
The input signal d of , that is, the output signal of impurity 12 is r
Change from lJ level to "0" level L, inverter 13
The output signal .changes from the "0" level to the "1" level. At this time, the input signal a instantaneously decreases to the "0" level, that is, (Vss Vmn+Vthc)i, but immediately after that, the output terminal (VDD) of the impurator 13 and the resistor R
, the current path consisting of the input terminal of the inverter 11, the input terminal of the inverter 11, the input terminal (vII) of the inverter 13, the input signal 1.
begins to rise.

This input signal a is the circuit threshold voltage vth of the impurator 11.
When e t rises, the imperder 11 performs an inverting operation and its output signal b d, r I J changes from level to "0" level, and at the same time, the input signal d of imper 13 changes to "0" level.
The output signal changes from the ``0'' level to the ``1'' level, and from the ``1'' level to the ``0'' level. Since this kind of operation occurs repeatedly, the inverter I
An output signal ∆rus is generated from the output terminal of J.

Therefore, in such an oscillation circuit, an input protection circuit consisting of a film-retaining resistor and a protection diode is usually provided at the input of the complementary MONO8) Lanzoster circuit constituting each of the impurities 11 to 13. In other words, this input protection circuit 3
As shown in FIG.
O8) Lanzostar Tr1 and NII [MOS) Lanzostar Tr! From here, each transistor Tr1sTr
A protection resistor Bm1*Rs2 is provided in series between the two commonly connected r-) of z and the input terminal M.

And this protective resistance Rsl # Rs! A protection diode DI is provided between the common connection point of the transistors Try and the power supply 71, and a protection diode DI is provided between the common connection point of the transistors Try and Tr2. -) and protective resistance R
A protection diode D1 is provided between the common connection point of s2 and ground V-. In an oscillation circuit having such an input protection circuit J1, as shown in FIG.
When the voltage of input signal a of is inverted, K r I J level (
Vsm+Vtk*-Vg g) or "0" rep k
(Was -Van +Vthe) When K is removed, this voltage (VDD +Vth@-Vsg) is the source I
The IE voltage Vllell is also high, and the voltage (Was-V
mn+V1hO is a voltage lower than the voltage v■. Therefore, if the voltage of the input signal a (the voltage at the input terminal) rises to the "1" level (VDD +Vth@-Vss) t, the voltage at the input terminal C1 of the canopy as shown in FIG. - A current path consisting of a resistor B, 1, a protective terminal 1'DI, and a power supply VDD is formed during the period when the voltage Vent decreases (@2'rt period shown in Figure 2). Konoto 1
Switch 81#8* in the figure is Inno Do-Yu 12°J.
Compatible with JK. Similarly, the voltage of input signal 1 is r OJ l
/4 k (Vll - VDD + Vthc), the current path consisting of the voltage v, the protective diode Do, the protective resistor R51eR1b input terminal, and the capacitor C as shown in FIG. A period (Ts period shown in FIG. 2) is formed during which the temperature rises to .

The period T1 of the noisy pulse generated from the conventional oscillation circuit that performs such an operation, that is, the period Tl e shown in FIG.
If we calculate Tm m Ts a Ta respectively, then R* B@1 e IRs 2””resistance 8. Each resistance value c of the protective resistor "NaTl-@2" is the capacitance of the capacitor C. Therefore, according to the above equations (1) to (4), the frequency f' of the /parse is expressed as follows.

In other words, according to equation (5), the / generated from the conventional oscillation circuit
The frequency f of the four pulses depends on the value of the resistor R11a R[p. However, this protective resistance R abuse 1#R1
2. Normally, when integrating an oscillation circuit, there are large variations due to the diffusion resistance of the semiconductor and the manufacturing process. Therefore, the pulse frequency f is
Therefore, there is a drawback that it fluctuates and becomes unstable.

This invention was made in view of the above circumstances, and aims to provide an oscillation circuit that generates pulses with a stable frequency by eliminating the influence of the protection resistor that constitutes the input protection circuit of the first stage inverter. purpose.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows its configuration. In an oscillation circuit consisting of a plurality of inverters 11 to 13 connected in series, similar to that shown in FIG. Cano f where charging or discharging is expressed as
A resistor R is connected between the output terminal C and the input terminal A of the first stage inverter 11.
8 are provided in series. The resistance value of this resistor R8 is set so as to limit the range of the voltage of the input signal 1 of the inverter 11, which varies depending on the time constant of the capacitor C and the resistor R, to within the power supply voltage VBD=VII. Note that the other configurations are the same as those in Figure 1, so the same reference numerals are given and explanations are omitted.

In such an oscillation circuit, if the input signal d of the impurator IJ at the output stage also becomes the "1" level, the power supply voltage VDD% cap a is shown in the 6th #A(A)K.
+Shita C1 resistance Rx1 input terminal A1 resistance R and voltage W
A current path starting from as (rOJ level) is formed, and the capacitor C enters a discharged state. When the power is on, the voltage of the input signal a generated at the input terminal of the first stage inverter 11 is:
As shown in Fig. 11g7, the instantaneous K "1" level, that is, the terminal voltage a2 of the electric capacitor C (shown in Fig. 6 (A) K) is ("-", -1R1j!) as shown in Fig. 7. L-
Therefore, the input protection circuit J1 of the first stage inverter 11 similar to that shown in FIG. A current path consisting of the terminal, protection resistor R, 1, protection diode D1%, and power supply voltage V11ml is never formed. Therefore, the input of the input terminal The voltage of signal 1 begins to decrease. When the voltage of this input signal a decreases by the threshold voltage vtbs+1 of the impur 5110 circuit as shown in FIG. The input signal aartJ of the inverter lJ changes from the level to "0" level. At this time, the voltage of the input signal 1 is at the rOJ level, that is, the potential. Kya 7f Shita C at this time
As shown in FIG. 7, the terminal voltage a2 (shown in FIG. 6 (2) K) is 2VD D + .Vt h@J.

Therefore, as shown in FIG. 6 (Bl), the power supply voltage VDD s
A current path consisting of the resistor 81 input terminal M, the resistor Rx% capacitor C, and the voltage VaS is formed, and the capacitor C
is in a charging state, but the input protection circuit J of inverter 1
1. That is, the voltage Vl shown in the above figure 4, etc. is similar to that shown by K.
A current path consisting of the protection diode PDs, the protection resistor 2, the input terminal, and the capacitor C is formed at a rate of 1%/%. Therefore, the protective resistance R11
The voltage of the input signal 1 at the input terminal starts to rise, independent of e Ra2.

Then, when the voltage of the input signal a rises to the voltage Vth@, the inverter 11 is inverted and the input signal d becomes "0".
level to rlJ level.

When such an operation is repeated, the output signal 71 from the output terminal of the inverter IJ in the output stage becomes
The signal is generated as an inverted signal of the input signal d.

It is generated from such an oscillation circuit. When calculating the oscillation frequency f of the pulse, first, as shown in Figure 7, the period T1
%, that is, the voltage V of input signal a is (Vthe≦v,≦
Rx within a range such as VDI + Vthe)
+R, Ts "'=(R+Rx)('hTh&'F;+R-brain pain-""(6).Furthermore, when the period T', that is, within the input signal a range, Te,= a-(R1-Rx)-C-muα-G
Vtbe (7). Since the period T of the pulse is "T, +T," the above formula (6)
, (7)), the oscillation frequency f of the pulse is. That is, according to the above equation (8), the oscillation frequency f of the current is determined by the time constant of the resistor Re R1 and the capacitor C. It becomes an unrelated value that does not depend on it.

By setting one resistor in this way, the change in the input voltage of the first-stage inverter 11 is limited to within the range of the power supply voltage van -Vllll. Therefore, the input protection circuit and This also prevents current from flowing to the I/iode. Therefore, it is possible to prevent instability of the oscillation frequency caused by variations in the protective resistance due to the semiconductor manufacturing process.

As detailed above, according to the present invention, it is possible to limit the range of the input voltage of the first stage inverter, which changes in response to the C8 time constant, and to eliminate the influence on the frequency of the protection resistor constituting the input protection circuit. Accordingly, it is possible to provide an oscillation circuit that generates a nof pulse having a stable frequency.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional oscillation circuit, Figure 2 is a diagram showing its timing chart, Figure 3 is a configuration diagram of a conventional oscillation circuit, and Figure 4 (4) (loosely explains its operation). 5 is a configuration diagram of an oscillation circuit according to an embodiment of the present invention, FIG. 6 is an equivalent circuit diagram explaining its operation, and FIG. 7 is a diagram showing its timing chart. be. 11.11.11-in/4-ta, Ra R1l a”
12 e RX...Resistance, C・-Ca/4C, D
s a Ds - diode, TrleTr2・-M
OS ) transistor.

Claims (1)

[Claims] An inverter circuit in which a plurality of stages of inverters made of M08 transistor circuits connected in series between power supplies are connected in series, and an input protection circuit made of a resistor and a diode is provided on the input side of the first stage innoper. , this inverter circuit Kl! It is connected to a resistor negative feedback circuit that provides negative feedback to the input terminal of the first stage impurator, and to the above inverter circuit! 1. An oscillation circuit characterized by comprising: a capacitive positive feedback circuit which is connected to the input terminal of an impurator in the first stage and provides positive feedback to the input end of a first-stage impurator; and a limiting resistor connected in series with the capacitor in the positive feedback circuit. .