JP2001102866A - Cr oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of an oscillation frequency by absorbing dispersion of a circuit constant in production. SOLUTION: A capacitor 23 performs charging/discharging through a resistor 22 corresponding to the comparing output of a comparator circuit 20. The comparing output of the comparator circuit 20 becomes a low level until increasing the terminal voltage of the capacitor 23 to a first reference voltage V1 and becomes high level until lowering the terminal voltage to a second reference voltage V2. A reference voltage generating part 13 has first and second voltage divider circuits 14 and 15 for generating the first reference voltage V1 and the second reference voltage V2 at the interval of plural stages, a first selector circuit 17 for outputting the reference voltage selected by a select signal from an EEPROM 19 out of the first reference voltages V1 of plural stages and a second selector circuit 18 for outputting the reference voltage selected by the select signal out of the second reference voltages V2 of plural stages. The selected reference voltages V1 and V2 are inputted to the comparator circuit 20 by any one of first and second switching circuits 24 and 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CR oscillating circuit which generates an oscillation signal of a predetermined frequency based on the charging / discharging characteristics of a capacitor. The present invention relates to a CR oscillating circuit configured to perform the above operation.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration example of a CR oscillation circuit used for a portable transmitter of a keyless entry system for a vehicle, for example. In FIG. 3, the CR oscillation circuit 1 is a one-chip IC as a whole, and the power supply of each internal circuit element is a power supply terminal V connected to a built-in battery.
DD. This power terminal V
Reference voltage generator 2 connected between DD and ground terminal
Is composed of, for example, a resistance voltage dividing circuit using a polycrystalline silicon film as a resistance element, and outputs a first reference voltage V1 and a second reference voltage V2 (V1> V2).

[0005] The output terminal of the comparison circuit 3 is connected to the output terminal 1 a of the CR oscillation circuit 1 via an inverter circuit 4. The output terminal 1a is connected to a ground terminal via a series circuit of a resistor 5 and a capacitor 6, and a terminal voltage of the capacitor 6 is applied to a non-inverting input terminal (+) of the comparison circuit 3. It has a configuration. One of the first reference voltage V1 and the second reference voltage V2 is selectively supplied to the inverting input terminal (-) of the comparison circuit 3 through the first switching circuit 7 or the second switching circuit 8. It has a configuration. Note that the resistance 5
Is formed using, for example, a polycrystalline silicon film, and the capacitor 6 is formed using an insulating film (for example, a silicon oxide film).

The first switching circuit 7 has a P-channel FET 7a and an N-channel FET 7b connected in parallel. The output of the inverter circuit 4 is supplied to the gate of the FET 7a via the inverter circuit 9, and the gate of the FET 7b is connected to the gate of the FET 7a. , The output of the inverter circuit 4 is directly given. The second switching circuit 8 has a P-channel FET 8a and an N-channel FET 8b connected in parallel. The output of the inverter circuit 4 is directly applied to the gate of the FET 8a, and the gate of the FET 8b is connected to the inverter circuit. 4 is provided through an inverter circuit 9.

According to this configuration, the charging period of the capacitor 6, that is, the period when the output of the inverter circuit 4 is inverted to the high level (the period when the comparison output of the comparing circuit 3 is at the low level)
Are the FETs 7a, 7b in the first switching circuit 7.
Is turned on, the first reference voltage V1 is supplied to the inverting input terminal (−) of the comparison circuit 3. Thereafter, when the terminal voltage of the capacitor 6 rises to the first reference voltage V1, the comparison output of the comparison circuit 3 is inverted to a high level, and the output of the inverter circuit 4 is inverted to a low level. Then
When the discharging operation of the capacitor 6 is started and the FETs 8a and 8b in the second switching circuit 8 are turned on, the second reference voltage V2 is applied to the inverting input terminal (-) of the comparison circuit 3. I will be able to. When the terminal voltage of the capacitor 6 decreases to the second reference voltage V2 in response to the discharge of the capacitor 6, the comparison circuit 3
Is inverted to a low level and the output of the inverter circuit 4 is inverted to a high level, so that the charging operation of the capacitor 6 is restarted and the first reference voltage is applied to the inverting input terminal (-) of the comparison circuit 3. V1 is provided.
In short, the charging / discharging operation of the capacitor 6 is periodically executed in accordance with the alternate inversion operation of the comparison output of the comparison circuit 3, whereby an oscillation operation of outputting a triangular oscillation signal of a predetermined frequency from the output terminal 1a is performed. Things.

[0006]

In the above-described CR oscillation circuit 1 formed into an IC, in the manufacturing process (semiconductor manufacturing process), the initial capacitance value of the capacitor 6, the resistor 5, and the reference voltage generation unit There is a situation that the initial resistance value of the resistance voltage dividing circuit in 2 varies. For this reason, in manufacturing the CR oscillation circuit 1, it is inevitable that the charging / discharging time constant of the capacitor 6 and the output voltage of the reference voltage generation unit 2 deviate from the design target value. However, there is a problem that the temperature is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to make it possible to absorb variations in circuit constants in a manufacturing process, thereby making it possible to improve the accuracy of an oscillation frequency. Is to provide a CR oscillation circuit that achieves the above.

[0008]

According to the first aspect of the invention, the charge / discharge cycle of the capacitor is determined by the charge / discharge time constant, the first reference voltage and the second reference voltage applied to the comparison input terminal of the comparison circuit. (In particular, the voltage difference between the reference voltages). That is,
The oscillation frequency of the CR oscillation circuit becomes lower as the charge / discharge time constant of the capacitor becomes larger, and the first reference voltage and the second
Becomes lower as the voltage difference between the reference voltages is larger.

In this case, the charge / discharge time constant of the capacitor is
The first reference voltage and the second reference voltage applied to the comparison input terminal of the comparison circuit are uniquely determined by the capacitance of the capacitor and the resistance value of the charge / discharge resistor. The configuration is such that it can be selected from the first reference voltage and the second reference voltage in a plurality of steps generated by the voltage dividing circuit and the second voltage dividing circuit through the first selecting circuit and the second selecting circuit. I have. Therefore, for example, the oscillation frequency can be adjusted by selecting the first reference voltage and the second reference voltage based on the result of actually measuring the charging / discharging time constant of the capacitor. It is possible to make the oscillation frequency close to the design target value by absorbing the variation of the circuit constants (capacitance of the capacitor, resistance value of the charging / discharging resistor, etc.) to be performed. As a result, even when the initial capacitance value of the capacitor, the charge / discharge resistance, and the initial resistance value of the resistive element for the voltage dividing circuit in the reference voltage generator vary, the accuracy of the oscillation frequency can be improved.

According to the second aspect of the present invention, a first voltage dividing circuit for generating a plurality of stages of a first reference voltage and a second voltage dividing circuit for generating a plurality of stages of a second reference voltage. The voltage circuit is connected in series between terminals that generate a predetermined voltage via a voltage dividing resistor, and the resistance temperature coefficient of the voltage dividing resistor is set to a value larger than the resistance temperature coefficient of each of the resistance elements. I have. Therefore, when the ambient temperature rises, the rate of increase of the resistance value of the voltage dividing resistor becomes larger than the rate of increase of the resistance value of each resistance element, and the level of the shared voltage of each resistance element decreases. A first reference voltage and a second
Is reduced.

In this case, when the ambient temperature rises,
As the resistance value of the charging / discharging resistor increases, the charging / discharging time constant of the capacitor increases, which acts to lower the oscillation frequency. The characteristic of slowing down) also acts to decrease the oscillation frequency, but at this time, the voltage difference between the first reference voltage and the second reference voltage acts to decrease and increase the oscillation frequency. In this way, the effect of reducing the oscillation frequency and the effect of increasing the oscillation frequency are canceled out, and the fluctuation of the oscillation frequency due to the temperature characteristics of the charge / discharge resistor can be prevented beforehand. Become like

According to the third aspect of the present invention, the selection signal for selecting a predetermined reference voltage from the first reference voltage and the second reference voltage in each of the plurality of stages is designated by the addressing of the storage means. Output according to
The reference voltage can be easily and reliably selected.

According to the fourth aspect of the present invention, the power supply for the comparison circuit is obtained from a regulator that generates a stabilized voltage having a level lower than the lower limit voltage of the power supply voltage of the CR oscillation circuit. Even when the power supply voltage fluctuates, the power supply voltage level of the comparison circuit is always stable. As a result, there is no danger of being affected by the voltage characteristics of the general comparison circuit (the characteristic that the operation speed decreases as the power supply voltage decreases), and the oscillation frequency changes due to the power supply voltage fluctuation. Can be prevented beforehand.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a configuration example of a CR oscillation circuit used in a portable transmitter of a keyless entry system for a vehicle. In FIG. 1, the CR oscillation circuit 11 of the present embodiment is a one-chip IC as a whole. The power of each internal circuit element is supplied from a power supply terminal VDD connected to a built-in battery through a regulator 12. Is to be given.
Note that the regulator 12 is configured to generate a stabilized voltage at a level lower than the lower limit voltage of the power supply voltage (voltage of the power supply terminal VDD) of the CR oscillation circuit 11.

The reference voltage generator 13 connected between the output terminal of the regulator 12 and the ground terminal provides a first reference voltage V1 and a second reference voltage V2 at different levels.
(V1> V2), which has the following configuration. That is, the reference voltage generator 1
Reference numeral 3 denotes a configuration in which a first voltage dividing circuit 14, a second voltage dividing circuit 15, and a voltage dividing resistor 16 are connected in series. Specifically, the first voltage dividing circuit 14 is configured by connecting a plurality of resistive elements 14a in series, and divides an applied voltage by each resistive element 14a to thereby form a first-stage first reference voltage V1.
Occurs. The second voltage dividing circuit 15 is configured by connecting a plurality of resistance elements 15a in series.
Divides the applied voltage to generate a second reference voltage V2 in a plurality of stages.

In this case, the resistance elements 14a, 15a
Is formed using, for example, a polycrystalline silicon film, whereas the voltage dividing resistor 16 is formed using, for example, an N-channel FET in which the drain and the source are short-circuited. The resistance temperature coefficient of the voltage dividing resistor 16 is set to a value larger than the resistance temperature coefficient of each of the resistance elements 14a and 15a (about 0.000685 / ° C. in the case of polycrystalline silicon).

Although FIG. 1 shows an example in which four resistive elements 14a and 15a are provided to generate the reference voltages V1 and V2 in three steps, actually, more resistive elements are provided. , So that the reference voltages V1 and V2 can be generated in multiple steps (for example, about 32 steps).

On the other hand, the first selecting circuit 17 including the first voltage dividing circuit 14 is connected to each of the output points of the first reference voltage V1 in a plurality of stages (common connection points of the respective resistance elements 14a). ,
The switching element 17 is provided between the switching element 17 and the output terminal 17a.
The switching element 17b outputs a predetermined reference voltage V1 from the output terminal 17a when one of the switching elements 17b is turned on. In addition, the second selection circuit 1 including the second voltage dividing circuit 15
Reference numeral 8 denotes a configuration in which a switching element 18b is connected between each output point (a common connection point of each resistance element 15a) of the second reference voltage V2 in a plurality of stages and an output terminal 18a. When one of the switching elements 18b is turned on, a predetermined reference voltage V2 is output from the output terminal 18a. Note that each of the above switching elements 1
7b and 18b can be configured using, for example, a P-channel FET.

The selection signal for turning on any one of the switching elements 17b and the selection signal for turning on any one of the switching elements 18b are designated by an address in the EEPROM 19 (corresponding to storage means). Is output from the EEPROM 19 in response to

The comparison circuit 20 has an output terminal connected to an output terminal 11a of the CR oscillation circuit 11 through an inverter circuit 21.
It is connected to the. The output terminal 11a is connected to a ground terminal via a series circuit of a charging / discharging resistor 22 and a capacitor 23. The non-inverting input terminal (+) of the comparison circuit 20 is connected to the terminal of the capacitor 23. The voltage is applied. One of the first reference voltage V1 from the first selection circuit 17 and the second reference voltage V2 from the second selection circuit 18 is supplied to the inverting input terminal (-) of the comparison circuit 20 in the first input terminal. , Or the second switching circuit 25. The resistor 22 is formed using, for example, a polycrystalline silicon film.
It is formed using an insulating film (for example, a silicon oxide film).

The first switching circuit 24 has a P-channel FET 24a and an N-channel FET 24b connected in parallel. The output of the inverter circuit 21 is supplied to the gate of the FET 24a via an inverter circuit 26.
The output of the inverter circuit 21 is directly given to the gate of the FET 24b. The second switching circuit 25 includes a P-channel FET 25a and an N-channel FET
25b are connected in parallel. The output of the inverter circuit 21 is directly supplied to the gate of the FET 25a.
The output of the inverter circuit 21 is provided to the gate of the ET 25b via the inverter circuit 26.

The operation of the above configuration is as follows. That is, the charging period of the capacitor 23, that is, the period in which the output of the inverter circuit 21 is inverted to the high level (the comparison circuit 20).
During the period when the comparison output of the first switching circuit 24 is at a low level (corresponding to the first level in the present invention), the FETs 24a and 24b in the first switching circuit 24 are turned on.
Are supplied with a first reference voltage V1. Thereafter, when the terminal voltage of the capacitor 23 rises to the first reference voltage V1, the comparison output of the comparison circuit 20 is inverted to a high level (corresponding to the first level in the present invention), and the output of the inverter circuit 21 is changed. Invert to low level. Then, the discharging operation of the capacitor 23 is started, and at the same time, the FET 25a in the second switching circuit 25,
25b is ON (FET in the first switching circuit 24)
24a and 24b are turned off), the comparison circuit 2
The second reference voltage V2 is supplied to the 0 inverting input terminal (-). When the terminal voltage of the capacitor 23 decreases to the second reference voltage V2 in response to such discharge of the capacitor 23, the comparison output of the comparison circuit 20 is inverted to low level, and the output of the inverter circuit 21 becomes high. Because of the inversion to the level, the charging operation of the capacitor 23 is restarted, and the first reference voltage V1 is applied to the inverting input terminal (−) of the comparison circuit 20.

In short, as the charging / discharging operation of the capacitor 23 is periodically executed in response to the alternate inversion operation of the comparison output of the comparison circuit 20, the terminal voltage of the capacitor 23 becomes as shown in FIG. It changes between the first reference voltage V1 and the second reference voltage V2, whereby an oscillation operation of outputting a triangular wave-like oscillation signal of a predetermined frequency from the output terminal 1a is performed.

Incidentally, the charge / discharge cycle T of the capacitor 23
(Refer to FIG. 2) is the charge / discharge time constant, the first reference voltage V1 and the second
And the voltage difference ΔV of the reference voltage V2 (see FIG. 2). That is, the oscillation frequency of the CR oscillation circuit 11 decreases as the charge / discharge time constant of the capacitor 23 increases, and decreases as the voltage difference ΔV between the first reference voltage V1 and the second reference voltage V2 increases.

In this case, the charging / discharging time constant of the capacitor 23 is uniquely determined by the capacity of the capacitor 23 and the resistance value of the charging / discharging resistor 22.
The first reference voltage V1 and the second reference voltage V2 given to the inverting input terminal (−) of 0 are the first reference voltage V1 and the second reference voltage V2, respectively.
The first reference voltage V1 and the second reference voltage V2 generated by the voltage dividing circuit 14 and the second voltage dividing circuit 15 in a plurality of stages.
Among the first selection circuit 17 and the second selection circuit 18
It can be selected through.

Therefore, for example, the oscillation frequency can be adjusted by selecting the first reference voltage V1 and the second reference voltage V2 based on the result of actually measuring the charging / discharging time constant of the capacitor 23, The circuit constants (capacity of capacitor 23, charge / discharge resistor 2
2 and the like, the oscillation frequency can be made closer to the design target value by absorbing the variation in the resistance value. As a result,
The initial capacitance value of the capacitor 23, the charge / discharge resistor 22, and the voltage dividing circuit resistance elements 14 a, 1
Even under the situation where the initial resistance value of 5a varies, the accuracy of the oscillation frequency can be improved.

A first voltage dividing circuit 14 for generating a plurality of stages of a first reference voltage V1 and a second voltage dividing circuit 15 for generating a plurality of stages of a second reference voltage V2 are:
It is connected in series between terminals that generate a predetermined voltage (between the output terminal of the regulator 12 and the ground terminal) via a voltage dividing resistor 16, and the temperature coefficient of resistance of the voltage dividing resistor 16 is determined by each voltage dividing circuit 14 and 15, the resistance elements 14a and 1
The value is set to a value larger than the temperature coefficient of resistance 5a. Therefore, when the ambient temperature rises, the rate of increase in the resistance value of the voltage dividing resistor 16 becomes larger than the rate of increase in the resistance value of each of the resistance elements 14a and 15a, and the resistance element 14a
, And 15a, the voltage difference ΔV between the first reference voltage V1 and the second reference voltage V2 is reduced.

In this case, when the ambient temperature rises,
Since the charging / discharging time constant of the capacitor 23 increases as the resistance value of the charging / discharging resistor 22 increases, it acts to lower the oscillating frequency. The characteristic that the operation is slowed down also acts to lower the oscillation frequency. At this time, however, the voltage difference ΔV between the first reference voltage V1 and the second reference voltage V2 is reduced to increase the oscillation frequency. As a result, the effect of reducing the oscillation frequency and the effect of increasing the oscillation frequency are offset as a result, and the oscillation frequency due to the temperature characteristics of the charge / discharge resistor is reduced. Fluctuations can be prevented beforehand.

Further, the first reference voltage V1 in a plurality of stages
And a selection signal for selecting a predetermined reference voltage from the second reference voltage V2 is output in accordance with the address designation of the EEPROM 19, so that the selection of the reference voltages V1 and V2 can be performed easily and easily. You can do it reliably.

Further, since the power supply of the comparison circuit 20 is obtained from the regulator 12 which generates a stabilized voltage having a level lower than the lowermost limit voltage of the power supply voltage of the CR oscillation circuit 11, when the power supply voltage fluctuates. But the comparison circuit 2
The power supply voltage level of 0 is always stable at all times. As a result, there is no danger of being affected by the voltage characteristics of the general comparison circuit 20 (the characteristic that the operation speed decreases as the power supply voltage decreases), and the oscillation frequency decreases due to the fluctuation of the power supply voltage. Changes can be prevented beforehand.

Note that the present invention is not limited to the above-described embodiment, and the following modifications or extensions are possible. Although the first voltage dividing circuit 14 and the second voltage dividing circuit 15 are connected in series, the first voltage dividing circuit 14 and the second voltage dividing circuit 15 are connected between terminals for generating a predetermined voltage.
The voltage dividing circuit 14 and the second voltage dividing circuit may be connected in parallel with each other. The point is that the relationship between the first reference voltage V1 and the second reference voltage V2 selected from a plurality of stages is different. V
It suffices that 1> V2. In addition, the first
When the voltage dividing circuit 14 and the second voltage dividing circuit 15 are connected in parallel, in order to reduce the voltage difference ΔV between the first reference voltage and the second reference voltage when the ambient temperature rises, one of the two The voltage dividing resistor 16 may be connected in series only with the voltage dividing circuit (for example, when the voltage dividing resistor 16 is connected to the ground terminal side, it is connected in series with the second voltage dividing circuit 15).

A configuration in which the terminal voltage of the capacitor 23 is applied to the non-inverting input terminal (+) of the comparison circuit 20, and the first reference voltage V1 and the second reference voltage V2 are selectively applied to the inverting input terminal (-). However, it is a matter of course that the present invention is not limited to this. Further, the voltage dividing resistor 16 is constituted by an N-channel FET because it is connected to the ground terminal side, but when it is connected to the output terminal side of the regulator 12, it is constituted by a P-channel FET. Of course, the voltage dividing resistor 16 may be formed by another element.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of a capacitor terminal voltage.

FIG. 3 is a diagram corresponding to FIG. 1 showing a conventional configuration.

[Explanation of symbols]

11 is a CR oscillation circuit, 12 is a regulator, 13 is a reference voltage generator, 14 is a first voltage dividing circuit, 14a is a resistance element, 15 is a second voltage dividing circuit, 15a is a resistance element, and 16 is a voltage dividing resistor. , 17 is a first selection circuit, 18 is a second selection circuit, 19 is an EEPROM (storage means), 20 is a comparison circuit, 22 is a resistor, 23 is a capacitor, 24 is a first switching circuit, and 25 is a second switching circuit. 2 shows a switching circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J043 AA26 GG01 5J081 AA08 BB04 CC17 CC46 DD09 EE03 EE04 FF08 FF11 FF18 FF23 FF25 GG05 KK02 KK12 KK23 LL05 MM01

Claims (5)

[Claims] 1. A reference voltage generator for generating an oscillation signal of a predetermined frequency based on a charge / discharge operation of a capacitor through a resistor, wherein the reference voltage generator outputs a first reference voltage and a second reference voltage having different levels from each other. , A terminal voltage of the capacitor and an output voltage of the reference voltage generation unit, and the comparison output is a first voltage.
A comparison circuit that performs the charging operation of the capacitor when the comparison output is at the second level and discharges the capacitor when the comparison output is at the second level. And a first switching circuit for applying the first reference voltage to a comparison input terminal of the comparison circuit, and turning on when the comparison output of the comparison circuit is at a second level. In a CR oscillation circuit comprising: a second switching circuit that supplies a voltage to a comparison input terminal of the comparison circuit; wherein the reference voltage generation unit is configured by connecting a plurality of resistance elements in series; A first voltage dividing circuit for generating a first reference voltage in a plurality of stages by dividing the voltage, a plurality of resistance elements are connected in series, and the applied voltage is divided by each resistance element A second voltage dividing circuit that generates a second reference voltage of a plurality of stages; a first selection circuit that outputs a reference voltage selected by a selection signal among the plurality of first reference voltages; A second selection circuit for outputting a reference voltage selected by a selection signal from a plurality of second reference voltages. 2. The first voltage dividing circuit and the second voltage dividing circuit are connected in series via a voltage dividing resistor between terminals for generating a predetermined voltage, and the voltage dividing resistor has a resistance temperature coefficient. 2. The CR oscillation circuit according to claim 1, wherein the resistance value is set to a value larger than a resistance temperature coefficient of each of the resistance elements. 3. The method according to claim 1, wherein the selection signal supplied to the first selection circuit and the second selection circuit is output in accordance with an address specification of a storage unit. CR oscillation circuit. 4. The regulator according to claim 1, further comprising a regulator for generating a stabilized voltage having a level lower than a lowermost limit voltage of a power supply voltage, wherein an output of the regulator is used as a power supply for the comparison circuit. Or a CR oscillation circuit according to any of the above. 5. The CR oscillation circuit according to claim 1, wherein the whole is formed as a one-chip IC.