JP3641345B2 - Delay circuit using substrate bias effect - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit technology of a semiconductor memory device, and more particularly to a delay circuit using a MOSFET.
[0002]
[Prior art]
In recent years, semiconductor storage devices have been used in general electric products such as home appliances and electronic cameras, in addition to electronic computers and measuring instruments. The demand for pricing is getting stronger.
[0003]
Among semiconductor memory devices, the one that has a particularly large amount of use is a DRAM (Dynamic Random Access Memory) that can access stored contents at an arbitrary address. In the DRAM, an ATD (Address Transition Detection) circuit for controlling the operation of the internal circuit is provided. In the ATD circuit, an input signal is delayed for a predetermined time, A delay circuit for outputting to the subsequent circuit is provided.
[0004]
What is indicated by reference numeral 110 in FIG. 7A is the prior art of the delay circuit described above, and the input signal V _IN is commonly input to the gate terminals of the p-channel MOSFET 111 and the n-channel MOSFET 112. When the input signal V _IN is switched from the high state to the low state, the p-channel MOSFET 111 is turned on, the n-channel MOSFET 112 is turned off, and a current is supplied from the power supply voltage V _DD to the capacitor 114 via the p-channel MOSFET 111 and the resistance element 113. The voltage is increased by charging the capacitor 114.
[0005]
On the other hand, when the input signal V _IN is switched from the low state to the high state, the p-channel MOSFET 111 is turned off, the n-channel MOSFET 112 is turned on, and the charged capacitor 114 is discharged through the n-channel MOSFET 112. It is configured to decrease.
[0006]
When the voltage of the capacitor 114 rises, if the power supply voltage V _DD is a constant voltage, the rate of voltage rise is such as the capacitance of the capacitor 114, the ON resistance value of the p-channel MOSFET 111, the resistance value of the resistance element 113, etc. Since it is determined by the characteristics, the input signal V _IN is output to the subsequent inverter 119 with a delay of a certain delay time, inverted by the inverter 119, and output as the output signal V _OUT .
[0007]
However, the voltage value of the power supply voltage V _DD supplied to the delay circuit 110 varies depending on the operation state of the peripheral circuit in the DRAM and the operation state of other semiconductor devices. When the power supply voltage V _DD fluctuates, the magnitude of the charging current to the capacitor 114 fluctuates, so that the delay time becomes shorter or longer. For example, when the power supply voltage V _DD increases, the conductance of the p-channel MOSFET 111 increases and the charging current to the capacitor 114 increases, resulting in a shorter delay time.
[0008]
Accordingly, countermeasures have also been taken in the prior art, and a stable power source 117 is provided in the DRAM as in the delay circuit indicated by reference numeral 120 in FIG. 7B, so that it is not affected by fluctuations in the power supply voltage V _DD. The stabilization voltage V _DL is generated, the stabilization voltage V _DL is applied to the source terminal of the p-channel MOSFET 111, and the charging current is supplied from the stabilization power source 117 to the capacitor 114. According to such a configuration, the delay time is not subject to fluctuations in the power supply voltage V _DD .
[0009]
However, it is difficult to supply the voltage from the stabilized power source 117 to all the circuits from the standpoint of current consumption during standby and access speed. Therefore, semiconductor integrated circuit on, will be the circuit is not affected by variations in the circuit and the power supply voltage V _DD affected by fluctuations in the power supply voltage V _DD are mixed, influence of variation of the overall power supply voltage V _DD It is difficult to eliminate.
[0010]
In recent years, the time margin (circuit operation margin) for matching the operation timing between the circuits has been reduced in order to increase the speed of the DRAM, and in such a case, the circuit due to the fluctuation of the power supply voltage V _DD is reduced. It is important to finely adjust the speed variation and to suppress the reduction of the circuit operation margin as much as possible while not affecting the entire circuit configuration optimized for the access speed.
[0011]
For the reasons stated above, the power supply voltage V _DD is shortened the delay time when the rising circuit (e.g., above the delay circuit 110) and, conversely, the delay time becomes longer when the power supply voltage V _DD rises with it Since a delay circuit is required, development of a technique for achieving this with a small number of elements has been awaited.
[0012]
[Problems to be solved by the invention]
The present invention was created in response to the above development requirements, and an object of the present invention is to provide a delay circuit in which the delay time becomes longer as the power supply voltage increases. Another object is to provide a semiconductor memory device using the delay circuit.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 is a capacitive element connected between a first node and a first power supply terminal, and the first node and a second power supply terminal. And a first MOS transistor that conducts in response to an input signal to charge or discharge the capacitive element, and a first MOS transistor that supplies an output signal corresponding to the voltage value of the first node. The first voltage is supplied to the substrate region of the first MOS transistor, and the voltage obtained by stabilizing the first voltage is supplied to the second power supply terminal. .
[0014]
The delay circuit according to claim 1 is configured such that the current supplied to the capacitive element via the first MOS transistor is limited by the current limiting element, as in the invention according to claim 2. Can do.
[0015]
According to a third aspect of the present invention, a p-channel MOS transistor is used as the first MOS transistor, and an n-channel MOS transistor that is placed in a conductive state when the p-channel MOS transistor is placed in a cutoff state is provided. The capacitive element can be configured to be charged via the p-channel MOS transistor and discharged via the n-channel MOS transistor.
[0016]
In the delay circuit according to claim 3, as in the invention according to claim 4, the voltage applied to the substrate region (back gate) of the p-channel MOS transistor is an external power supply voltage, and the p-channel MOS transistor The voltage applied to the source terminal can be a stabilized voltage having a voltage value lower than that of the external power supply voltage.
[0017]
The delay circuit according to any one of claims 1 to 4 described above can be provided in a semiconductor memory device as in the invention according to claim 5.
[0018]
The delay circuit of the present invention is configured as described above, and the capacitive element is connected to the stabilized power supply via the MOS transistor that is in the conductive state, and the charge / discharge current is supplied via the current limiting element such as the resistance element. Since it flows, the voltage value of the capacitive element changes. The output signal of the subsequent circuit changes according to the voltage value of the capacitor (first node).
[0019]
In the delay circuit of the present invention, since a power supply voltage different from the voltage at the source terminal is applied to the substrate region (back gate) of the MOS transistor, the conductance of the MOS transistor is affected by the substrate bias effect. Varies with size. When the voltage difference between the source terminal and the substrate region becomes large due to fluctuations in the power supply voltage, the conductance decreases, but the stabilization voltage is applied to the source terminal of the MOS transistor, so the conductance decreases. Then, since the charge / discharge current flowing through the capacitor element decreases, the delay time becomes longer.
On the contrary, when the voltage difference between the source terminal and the substrate region is reduced, the conductance is increased and the charge / discharge current flowing through the capacitor is increased, so that the delay time is shortened.
[0020]
As such a MOS transistor, an n-channel MOS transistor can be used when the power supply voltage is negative, and a p-channel MOS transistor can be used when the power supply voltage is positive. When a p-channel MOS transistor is used, if the source terminal is connected to the stabilized power supply side and the drain terminal is connected to the capacitive element side, an output signal delayed when the capacitive element is charged can be obtained. .
[0021]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
Referring to FIG. 1, reference numeral 10 denotes a delay circuit according to an example of the present invention, and is provided as a part of a timing adjustment circuit in a DRAM. A power supply voltage V _DD (first voltage) and a ground voltage V _SS supplied from an external power supply are applied to the DRAM. The power supply voltage V _DD is used as a power source for internal memory cells. It is configured to allow data input / output.
[0022]
The delay circuit 10 includes a p-channel MOSFET 11 (first MOS transistor), an n-channel MOSFET 12, a resistance element 13, a capacitor 14 (capacitance element), a stabilized power supply 17, and an inverter 19 (output corresponding to the voltage value of the first node). The stabilized power supply 17 is configured to stabilize the power supply voltage V _{DD and} to supply a constant stabilized voltage V _DL (constant voltage control). Is based on the ground voltage V _SS ). Here, the power supply voltage V _DD is about 3.3V, and the stabilization voltage V _DL is about 2.2V.
[0023]
The source terminal of the p-channel MOSFET 11 is connected to the stabilized power supply 17 so that a stabilized voltage V _DL (a voltage obtained by stabilizing the first voltage) is applied, and the drain terminal is connected to the resistance element 13. Are connected to the terminal on the high voltage side of the capacitor 14 and the drain terminal (first node: indicated by symbol A) of the n-channel MOSFET 12. The low voltage side terminal of the capacitor 14 and the source terminal of the n-channel MOSFET 12 are connected to an internal wiring (first power supply terminal) to which the ground voltage V _SS is applied.
[0024]
An input signal V _IN is applied in common to the gate terminal of the p-channel MOSFET 11 and the gate terminal of the n-channel MOSFET 12, and the terminal on the high voltage side of the capacitor 14 is connected to the input terminal of the inverter 19. It is connected.
[0025]
In the inverter 19, a p-channel MOSFET 15 and an n-channel MOSFET 16 are provided. With the drain terminals connected to each other, the source terminal of the p-channel MOSFET 15 is connected to the stabilization voltage V _DL side and the n-channel MOSFET 16 is connected. The source terminal is connected to the ground voltage V _SS side. The terminal on the high voltage side of the capacitor 14 is commonly connected to the gate terminal of the p-channel MOSFET 15 and the gate terminal of the n-channel MOSFET 16. An output signal V _OUT is taken out from the drain terminals of the p-channel MOSFET 15 and the n-channel MOSFET 16 that are connected to each other, and is input to a subsequent circuit (not shown).
[0026]
The operation of the delay circuit 10 will be described. In the initial state, when the input signal V _IN is in the high state, the p-channel MOSFET 11 is OFF (cut-off state), and the n-channel MOSFET 12 is ON (conductive state), it is assumed that no charge is accumulated in the capacitor 14.
[0027]
In this case, the midpoint of connection between the resistance element 13, the n-channel MOSFET 12 and the capacitor 14 (the first node denoted by reference symbol A) is in the low state, and the output signal _VOUT output from the inverter 19 is in the high state.
[0028]
When the input signal V _IN is switched from the high state to the low state, the n-channel MOSFET 112 is turned off and the p-channel MOSFET 11 is turned on. When the p-channel MOSFET 11 is turned on, the terminal on the high voltage side of the capacitor 14 is connected to the stabilized power supply 17 via the p-channel MOSFET 11 and the resistance element 13, and the capacitor is in a state where current is limited by the p-channel MOSFET 11 and the resistance element 13. A charging current flows for 14.
[0029]
Since the stabilization voltage V _DL applied to the source terminal of the p-channel MOSFET 11 is not affected by the fluctuation of the power supply voltage V _DD and is a constant voltage, if the conductance of the p-channel MOSFET 11 is constant, the capacitor 14 The voltage value increases at a speed corresponding to the ON resistance value of the p-channel MOSFET 11, the resistance value of the resistance element 13, and the capacitance of the capacitor 14.
[0030]
The output of the inverter 19 is configured to switch from a high state to a low state when it exceeds a predetermined threshold voltage, the time delay circuit of the voltage of the capacitor 14 to greater than its threshold voltage from the ground voltage V _SS 10 Delay time. The input signal V _IN is transmitted through the delay circuit 10 with a delay time, and is output as an output signal V _OUT .
[0031]
In this case, in the p-channel MOSFET 15 in the inverter 19, the substrate region (back gate) and the source terminal are short-circuited, and the stabilization voltage V _DL is applied in common. Even if the power supply voltage V _DD varies, the inverter The 19 threshold voltages are configured so as not to fluctuate.
[0032]
On the other hand, in the p-channel MOSFET 11 that supplies a current to the capacitor 14, the stabilization voltage V _DL is applied to the source terminal, and the power supply voltage V _DD is applied to the substrate region (back gate). FIG. 2 shows a schematic diagram of the diffusion structure of the p-channel MOSFET 11 and the n-channel MOSFET 12. In this DRAM, a p-type silicon substrate 31 having an N-well 41 is used, and a p-type region 32 is diffused in the N-well 41. The p-type region 32, the gate oxide film 51 formed on the surface, and the gate electrode 52 constitute a p-channel MOSFET 11 having the p-type region 32 as a source terminal and a drain terminal.
[0033]
On the other hand, an n-type region 42 is diffused and formed in the p-type silicon substrate 31. The n-type region 42, the gate oxide film 51 and the gate electrode 52 on the surface, and the n-type region 42 is connected to a source terminal and a drain terminal. An n-channel MOSFET 12 is configured.
[0034]
Therefore, the substrate region of the p-channel MOSFET 11 is the N well 41, and the substrate region of the n-channel MOSFET 12 is the p-type silicon substrate 31 itself.
[0035]
A power supply voltage V _DD is applied to the N well 41, and therefore, in the p-channel MOSFET 11, the power supply voltage V _DD is applied to the substrate region. A ground voltage V _SS is applied to the p-type silicon substrate 31, and the substrate region of the p-channel MOSFET 11 and the p-type silicon substrate 31 are in a reverse bias state.
[0036]
Since the stabilization voltage V _DL is generated from the power supply voltage V _DD ,
V _DL <V _DD
There is a large and small relationship. As shown in FIG. 3, with reference to the source terminal voltage of the p-channel MOSFET, the gate terminal voltage is V _GS , the back gate voltage (substrate region voltage) is V _BS , the drain terminal voltage is V _DS, and When the current flowing from the source terminal to the drain terminal is I _DS , the following expression is established between the back gate voltage V _BS and the power supply voltage V _DD and the stabilization voltage V _DL :
V _BS = V _DL −V _DD <0
There is a relationship.
[0037]
In the normal connection of the MOSFET, the source terminal and the substrate region are short-circuited, so that the back gate voltage V _BS is zero (V _BS = 0). The relationship between the gate voltage V _GS of the p-channel MOSFET and the drain current I _DS is shown in the graph of FIG. 4 when the back gate voltage V _BS is zero and when it is not zero (V _BS <0). When the gate voltage V _GS having the same magnitude is applied, the drain current I _DS decreases as the back gate voltage V _GS increases in the negative voltage direction.
[0038]
The relationship between the drain voltage V _DS and the drain current I _DS of the p-channel MOSFET is shown in the graphs of FIG. 5A and FIG. 5B for the case where the back gate voltage V _BS is zero and the case of the negative voltage, respectively. .
[0039]
The gate voltage V _GS as is apparent from the characteristics in the case of a _{V G1 ~V G4 (V G4 <} V G3 <V G2 <V G1 <0), when a gate voltage is applied V _GS of the same magnitude As the back gate voltage V _BS increases in the negative voltage direction, the drain current I _DS decreases.
[0040]
The graph of FIG. 6 shows the relationship between the back gate voltage V _BS and the drain current I _DS when the gate voltage V _GS and the drain voltage V _DS are constant. For each curve, V _GS = V _DS . As the back gate voltage V _BS increases in the negative voltage direction, the amount of drain current I _DS decreases.
[0041]
As described above, the conductance of the p-channel MOSFET 11 is lowered when the potential of the substrate region is made higher than the potential of the source terminal and the back gate voltage is applied. As can be seen from FIG. 6, the conductance value largely varies depending on the potential difference between the substrate region and the source terminal. Specifically, when the power supply voltage V _DD increases, the back gate voltage V _BS increases in the negative voltage direction, so that the conductance of the p-channel MOSFET 11 decreases and the charging current to the capacitor 14 decreases, resulting in a delay time. Becomes longer. On the other hand, when the power supply voltage V _DD is lowered, the back gate voltage V _BS becomes smaller in absolute value, so that the conductance becomes larger and the delay time becomes shorter. As described above, the delay time is automatically expanded and contracted by the fluctuation of the power supply voltage V _DD .
[0042]
In the above-described embodiment, the delay circuit 10 in the case of using the positive power supply voltage V _DD has been described. However, in the case of using the negative power supply, the delay in applying the negative power supply voltage to the substrate region of the n-channel MOSFET is described. A circuit may be configured.
[0043]
【The invention's effect】
Since the delay time becomes longer due to the power supply voltage rise and the delay time becomes shorter due to the power supply voltage drop, the timing adjustment circuit can be easily designed.
Since the delay time is automatically expanded and contracted by the power supply voltage fluctuation, the timing adjustment circuit can be simplified.
[Brief description of the drawings]
FIG. 1 is an example of a delay circuit of the present invention. FIG. 2 is a schematic diagram of a diffusion structure of a p-channel MOSFET and an n-channel MOSFET. FIG. 3 is a diagram for explaining V _GS , V _DS and V _BS of a p-channel MOSFET. Figure 4 is a graph showing the V _DS -I _DS characteristics when V _GS -I graph Figure 5 for explaining the differences in the _DS characteristics (a) V _BS = 0 by V _BS
(b) Graph showing V _DS -I _DS characteristics when V _BS <0 [FIG. 6] Graph showing V _BS -I _DS characteristics when V _GS and V _DS are constant [FIG. 7] (a) Prior art delay circuit that shortens delay time due to power supply voltage rise
(b) Delay circuit of prior art in which delay time is not affected by power supply voltage fluctuation
DESCRIPTION OF SYMBOLS 10 ... Delay circuit 11 ... 1st MOS transistor (p channel MOS transistor) 12 ... N channel MOS transistor 13 which conducts complementarily 13 ... Current limiting element (resistance element) 14 ... Capacitance element 17 ... Stable Power source 19... First circuit (inverter) 41... Substrate area A... First node V _DD ... First voltage (power supply voltage) V _DL . _IN …… Input signal V _OUT …… Output signal V _SS …… First power supply terminal

Claims (5)

A capacitive element connected between the first node and the first power supply terminal;
A first MOS transistor connected between the first node and a second power supply terminal, and charging or discharging the capacitive element by conducting in response to an input signal;
A first circuit for supplying an output signal corresponding to the voltage value of the first node;
A delay circuit in which a first voltage is supplied to a substrate region of the first MOS transistor, and a voltage obtained by stabilizing the first voltage is supplied to the second power supply terminal. 2. The delay circuit according to claim 1, wherein a current limiting element is connected between the first node and the first MOS transistor or between the second power supply terminal and the first MOS transistor. . The first MOS transistor is a p-channel MOS transistor, and an n-channel MOS transistor that is complementarily conductive with the p-channel MOS transistor is connected between the first node and the first power supply terminal. The delay circuit according to claim 1 or 2. 4. The delay circuit according to claim 3, wherein the first voltage is a power supply voltage supplied from the outside, and the stabilization voltage is a voltage lower than the power supply voltage obtained by stabilizing the power supply voltage in an internal circuit. A semiconductor memory device comprising the delay circuit according to claim 1, 2, 3 or 4.

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