CN112383291B - Digital controllable delay chain - Google Patents

Digital controllable delay chain Download PDF

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CN112383291B
CN112383291B CN202011248739.6A CN202011248739A CN112383291B CN 112383291 B CN112383291 B CN 112383291B CN 202011248739 A CN202011248739 A CN 202011248739A CN 112383291 B CN112383291 B CN 112383291B
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gating
voltage
stage
circuit
substrate
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CN112383291A (en
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胡毅
唐晓柯
李振国
侯佳力
胡伟波
肖知明
尹芸婷
燕翔
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State Grid Corp of China SGCC
Nankai University
State Grid Information and Telecommunication Co Ltd
State Grid Zhejiang Electric Power Co Ltd
Beijing Smartchip Microelectronics Technology Co Ltd
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State Grid Corp of China SGCC
Nankai University
State Grid Information and Telecommunication Co Ltd
State Grid Zhejiang Electric Power Co Ltd
Beijing Smartchip Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

The invention provides a digital controllable delay chain, and belongs to the technical field of integrated circuits. The digitally controllable delay chain comprises: the reference voltage generation module is used for dividing the power supply voltage into a plurality of reference voltages; a digital signal gating module for selecting a control voltage from a plurality of the reference voltages; and the clock delay module is used for delaying the input clock under the control of the control voltage. The clock delay module of the digital controllable delay chain provided by the invention is based on the back gate effect of the MOS device, can realize accurate delay of an input clock under the control of control voltage, and has better linearity.

Description

Digital controllable delay chain
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a digital controllable delay chain.
Background
Digitally controllable delay chains have an important role in high-speed high-precision analog-to-digital converters, high-precision phase-locked loops and chips with high demands on clock delay, such as adjusting for mismatch between multiple clocks. When skew errors occur in multiple clocks due to different paths or unreasonable routing, the performance of the circuit controlled by the clocks can be greatly reduced, and even in some applications where clock overlap is not allowed, the circuit fails due to the skew errors, so that accurate and controllable adjustment of the clocks is required.
The existing design method for realizing the delay clock has certain defects, such as a delay mode based on a multi-stage inverter chain, because the delay of a one-stage inverter in a high-speed chip needs to be controlled to be in the order of tens of picoseconds, the accuracy of adjustment is too low based on the delay mode of the multi-stage inverter chain.
At present, a method for precisely controlling the clock, for example, a digital controllable delay chain based on a capacitor array, adopts the idea of charging and delaying a resistor and a capacitor, converts the adjustable delay time into the size of the load capacitance of an inverter, adjusts the number of the load capacitance connected with the inverter through a digital control signal, and finally realizes the controllable delay of the clock. Based on the delay chain of the capacitor array, the accuracy of adjustment can reach hundreds of femtoseconds by using smaller MOS capacitors as delay units. Because the MOS capacitors are mismatched in the manufacturing process, the unit capacitors are inconsistent in size, and non-monotonicity increase or non-monotonicity decrease can occur in the time adjustment process, so that the matching of the MOS capacitors is poor, and the delay of the delay chain can occur in a non-linear condition; and the delay chain area formed by the MOS capacitor array is larger, and the power consumption and the cost are higher.
Disclosure of Invention
The invention aims to provide a digital controllable delay chain so as to realize accurate delay of an input clock and have better linearity.
To achieve the above object, the present invention provides a digitally controllable delay chain comprising:
the reference voltage generation module is used for dividing the power supply voltage into a plurality of reference voltages;
a digital signal gating module for selecting a control voltage from a plurality of the reference voltages;
and the clock delay module is used for delaying the input clock under the control of the control voltage.
Further, the clock delay module comprises a delay circuit based on a back gate effect of the MOS device;
the substrate voltage of the MOS device of the delay circuit is controlled by the control voltage.
Further, the delay circuit comprises a first-stage inverter and a second-stage inverter;
the first-stage inverter comprises a first PMOS transistor and a first NMOS transistor, the substrate voltage of the first PMOS transistor is controlled by the control voltage, and the substrate of the first NMOS transistor is connected with the source electrode;
the second-stage inverter comprises a second PMOS transistor and a second NMOS transistor, wherein the substrate of the second PMOS transistor is connected with the source electrode, and the substrate of the second NMOS transistor is connected with the source electrode.
Further, the delay circuit comprises a first-stage inverter and a second-stage inverter;
the first-stage inverter comprises a first PMOS transistor and a first NMOS transistor, wherein the substrate of the first PMOS transistor is connected with the source electrode, and the substrate voltage of the first NMOS transistor is controlled by the control voltage;
the second-stage inverter comprises a second PMOS transistor and a second NMOS transistor, wherein the substrate of the second PMOS transistor is connected with the source electrode, and the substrate of the second NMOS transistor is connected with the source electrode.
Further, the reference voltage generating module comprises a reference voltage generating circuit, the reference voltage generating circuit comprises a plurality of resistors connected in series, the resistance value of each resistor is equal, and a plurality of reference voltages with equal intervals can be generated through a plurality of resistors.
Further, the number of the resistors is positively correlated with the number of bits of the digital control signal of the digital signal gating module.
Further, the resistor has 2 N And pass 2 N A resistance of 2 N The reference voltages are equally spaced, where N is the number of bits of the binary digital control signal.
Further, the digital signal gating module comprises a thermal code gating circuit based on a MOS switch, wherein the thermal code gating circuit is used for gating a substrate voltage of a MOS device serving as the delay circuit from a plurality of reference voltages.
Further, the thermal code gating circuit is capable of converting the plurality of reference voltages generated by the reference voltage generating circuit into a thermal code form by a dichotomy and gating the plurality of reference voltages.
Further, the thermal code gating circuit comprises N-stage gating switches, wherein a first stage gating switch of the N-stage gating switches comprises 2 N A second stage of the N-stage gating switches comprises 2 MOS switches N-1 A third stage of the N stage gating switches comprises 2 MOS switches N-2 A MOS switch, and so on, the N-th gating switch of the N-th gating switches comprises 2 1 A plurality of MOS switches; where N is the number of bits of the binary digital control signal.
The digital controllable delay chain based on the back gate effect of the MOS device provided by the invention is characterized in that the reference voltage generating module is used for equally dividing the power supply voltage to generate the equally spaced reference voltages, then the digital signal gating module is used for selecting a plurality of reference voltages to obtain the control voltage, and finally the accurate delay of the input clock is realized under the control of the control voltage. Specifically, the invention uses the mechanism of adjusting the threshold voltage based on the back gate effect of the MOS device to enable the conduction speed of the MOS inverter to be adjustable, and compared with the thought of charging delay based on the MOS capacitor, the invention uses the MOS inverter with the adjustable conduction speed to replace the MOS capacitor array to realize accurate delay of the input clock, and has better linearity. In addition, the invention adjusts the mechanism of the threshold voltage based on the back gate effect of the MOS device, so that the digital controllable delay chain has fewer devices, simple circuit structure and lower cost.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a block diagram of a digitally controllable delay chain provided by one embodiment of the present invention;
FIG. 2 is a circuit diagram of a delay circuit of a digitally controllable delay chain provided in one embodiment of the present invention;
FIG. 3A is the substrate voltage V of a PMOS transistor B <Back gate effect at VDD;
FIG. 3B is the substrate voltage V of the PMOS transistor B Back gate effect at=vdd;
FIG. 4 is a diagram of waveforms input and output of a delay circuit of a digitally controllable delay chain according to one embodiment of the present invention;
fig. 5 is a circuit diagram of a delay circuit of a digitally controllable delay chain according to another embodiment of the present invention;
FIG. 6 is a circuit diagram of a reference voltage generation circuit of a digitally controllable delay chain according to one embodiment of the present invention;
fig. 7 is a circuit diagram of a thermal code gating circuit of a digitally controllable delay chain according to one embodiment of the present invention.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Fig. 1 is a block diagram of a digitally controllable delay chain provided in accordance with one embodiment of the present invention. As shown in fig. 1, an embodiment of the present invention provides a digitally controllable delay chain, including: the device comprises a reference voltage generation module, a digital signal gating module and a clock delay module. The reference Voltage generation module is used for dividing the power Supply Voltage into a plurality of reference voltages VB [ i ]. The Digital signal gating module is used for selecting a control voltage VC from a plurality of reference voltages VB [ i ] through a Digital control signal Digital Code. The clock delay module is used for precisely delaying the input clock Clk_in under the control of the control voltage VC and then outputting Clk_Out.
The clock delay module comprises a delay circuit based on a back gate effect of the MOS device. The substrate voltage of the MOS device of the delay circuit is controlled by the control voltage, namely, the control voltage VC output by the digital signal gating module is used as the substrate voltage of the MOS device of the delay circuit.
Fig. 2 is a circuit diagram of a delay circuit of a digitally controllable delay chain according to one embodiment of the present invention. As shown in fig. 2, the delay circuit includes a first-stage inverter and a second-stage inverter; the first-stage inverter comprises a first PMOS transistor MP1 and a first NMOS transistor MN1, wherein the substrate voltage of the first PMOS transistor MP1 is controlled by a control voltage VC, and the substrate of the first NMOS transistor MN1 is connected with a source electrode; the second-stage inverter includes a second PMOS transistor MP2 and a second NMOS transistor MN2, where a substrate of the second PMOS transistor MP2 is connected to a source, and a substrate of the second NMOS transistor MN2 is connected to a source.
As shown in fig. 3A and 3B, the voltage V at the gate of the PMOS transistor G Slightly smaller than threshold voltage V TH When a depletion layer is formed under the gate but no inversion layer is present. As shown in fig. 3A, the substrate voltage V B <At VDD, at substrate voltage V B During the increase to VDD, more electrons will be attracted to the substrate electrode while leaving a large positive charge; as shown in FIG. 3B, when the substrate voltage V B When=vdd, the depletion layer of the PMOS transistor widens.
According to the formula:
Figure BDA0002770893470000051
it can be seen that the threshold voltage V TH Is a function of the total number of depletion layer charges Qd. Since the gate charge must mirror the depletion layer charge Qd before the inversion layer is formed, with V B Increase in Qd increase, V TH Also increases, thereby requiring a lower gate voltage V G So that the PMOS transistor is turned on, which is the back gate effect of the MOS device.
The delay circuit built based on the back gate effect of the PMOS transistor is shown in fig. 2, wherein the substrate voltage of the first PMOS transistor MP1 in the first-stage inverter is controlled by the control voltage VC, the substrate and the source of the first NMOS transistor MN1 are shorted, and the second-stage inverter adopts the existing connection method. By increasing the control voltage VC of the delay circuit MP1 to increase the threshold voltage of MP1, a lower gate voltage is required to turn on based on the back gate effect MP1, thereby delaying the falling edge of the input clock clk_in. As shown IN fig. 4, the falling edge of the input clock clk_in is delayed by the first-stage inverter to form the rising edge of clk_delay, and then the falling edge of the delayed output clock clk_out is obtained by the second-stage inverter.
In designing the delay circuit, the delayed clock edges may be determined as desired. If the falling edge is delayed, controlling the substrate voltage of the PMOS transistor; if the rising edge is delayed, the substrate voltage of the NMOS transistor is controlled. Fig. 5 is a circuit diagram of a delay circuit of a digitally controllable delay chain according to another embodiment of the present invention. In another embodiment, as shown in fig. 5, a delay circuit for delaying a rising edge includes a first stage inverter and a second stage inverter; the first-stage inverter comprises a first PMOS transistor MP1 and a first NMOS transistor MN1, wherein the substrate of the first PMOS transistor MP1 is connected with the source electrode, and the substrate voltage of the first NMOS transistor MN1 is controlled by the control voltage VC; the second-stage inverter includes a second PMOS transistor MP2 and a second NMOS transistor MN2, where a substrate of the second PMOS transistor MP2 is connected to a source, and a substrate of the second NMOS transistor MN2 is connected to a source.
Fig. 6 is a circuit diagram of a reference voltage generation circuit of a digitally controllable delay chain according to one embodiment of the present invention. The reference voltage generating module provided in this embodiment includes a reference voltage generating circuit, where the reference voltage generating circuit includes a plurality of resistors connected in series, each of which has an equal resistance value, and is capable of generating a plurality of reference voltages with equal intervals through the plurality of resistors, so as to provide a voltage for controlling the MOS transistor substrate of the delay circuit. The number of resistors of the reference voltage generating circuit is positively correlated with the number of bits of the digital control signal of the digital signal gating module, namely, the number of resistors is determined by the number of bits of the digital control signal. If there is a digital control signal with N bits binary, the number of resistors is 2 N (N.gtoreq.1), wherein the resistance value of each resistor is equal to each other by 2 N A resistance of 2 N Reference voltages equally spaced apart to divide VDD into 2 N And a number of gears, wherein N is the number of bits of the binary digital control signal. Taking a 2-bit binary digital control signal as an example, as shown in FIG. 6, the reference voltage generating circuit is composed of a resistor R 1 、R 2 、R 3 、R 4 Is connected in series to correspondingly generate voltage V B1 、V B2 、V B3 、V B4 VDD is equally divided into 4 gears.
FIG. 7 is a schematic illustration of an embodiment of the inventionA circuit diagram of a thermal code gating circuit of a digital controllable delay chain is provided. The digital signal gating module comprises a thermal code gating circuit based on a MOS switch, wherein the thermal code gating circuit is used for gating a substrate voltage of a MOS device serving as the delay circuit from a plurality of reference voltages. The thermal code gating circuit converts the plurality of reference voltages generated by the reference voltage generating circuit into a thermal code form through a dichotomy and gates the plurality of reference voltages. Specifically, the thermal code gating circuit comprises N-stage gating switches, wherein a first-stage gating switch of the N-stage gating switches comprises 2 N A second stage of the N-stage gating switches comprises 2 MOS switches N-1 A third stage of the N stage gating switches comprises 2 MOS switches N-2 A MOS switch, and so on, the N-th stage gating switch comprises 2 1 A plurality of MOS switches, wherein N is the number of bits of the digital control signal; and finally, outputting one path of voltage as the substrate voltage (namely the control voltage VC of the substrate) of the MOS device through the gating of the N-stage gating switch. Taking a 2-bit digital control signal as an example, as shown in FIG. 7, the thermal code gating circuit outputs an input signal D<1:0>The Db is obtained by taking the inverse<1:0>The first stage gating switch comprises 4 MOS switches, which are formed by D<1>From 4-way voltage (V B1 、V B2 、V B3 、V B4 ) 2-way gating, the second stage gating switch comprises 2 MOS switches, and D<0>The 1-way is gated from the 2-way voltage as the final output (VC).
In designing the digitally controllable delay chain of the present invention, it is preferable to determine the delay clock edges, and thus the delay circuit, according to the requirements. And then determining the number of resistors required by the reference voltage generating circuit and the number of MOS switches required by the thermal code gating circuit according to the bit number of the digital control signal. If the digital control signal has N bits, 2 is needed N Resistance generation 2 N A plurality of reference voltages; meanwhile, the thermal code gating circuit is provided with N-level gating switches so as to realize control of binary thermal code gating forms. Finally, the maximum adjustable range of clock delay is realized by setting the width of the MOS device with the back gate effect, for example, when the delay falling edge is needed, the total delay adjustable range is selected when the PMOS width is 1.05um and the length is 60nmThe circumference is 3ps.
The digital controllable delay chain based on the back gate effect of the MOS device provided by the embodiment of the invention equally divides the power supply voltage into a series of control voltages with equal intervals through a group of series resistors with equal size, then adds the generated voltages to the substrate end of the MOS device according to the digital control signals, and changes the threshold voltage of the MOS device by utilizing the back gate effect of the MOS device, thereby controlling the conduction speed of the MOS device, and finally realizing accurate delay of an input clock signal through an inverter built by the MOS device.
In this embodiment, the principle of adjusting the conduction speed of the MOS inverter is: the turn-on speed of the inverter is adjusted by adjusting the threshold voltage of the PMOS devices in the inverter. Based on the principle of the body effect of the MOS device, namely, the threshold voltage of the MOS device is changed along with the change of the difference value between the substrate voltage and the source terminal voltage. Typically, the source of a PMOS device is connected to a power supply voltage, and the lower the substrate voltage, the higher the threshold voltage of the PMOS, and the lower the voltage required for the gate of the PMOS to turn on. When the MOS device is applied to the inverter, if the threshold voltage of the PMOS is high, the delay time when the falling-edge clock is turned on is longer.
Compared with the thought of MOS capacitor charge delay, the digital controllable delay chain provided by the invention uses the MOS inverter with adjustable conduction speed to replace the MOS capacitor array to realize the accurate delay of the input clock, and the minimum adjustable time of the digital controllable delay chain can be accurate to 35fs because the inverter based on the MOS device back gate effect is more accurate than the delay of the MOS capacitor array. Because the MOS capacitor has mismatch in the manufacturing process, the unit capacitor is inconsistent in size, and non-monotonicity increase or decrease can occur in the time adjustment process. However, no matter whether the MOS device has mismatch or not, the body effect is invariable, namely the time adjustment is monotonous, so the digital controllable delay chain based on the back gate effect of the MOS device has better linearity. In addition, the invention adjusts the mechanism of the threshold voltage based on the back gate effect of the MOS device, so that the digital controllable delay chain has fewer devices, simple circuit structure and lower cost.
The alternative embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the embodiments of the present invention are not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solutions of the embodiments of the present invention within the scope of the technical concept of the embodiments of the present invention, and all the simple modifications belong to the protection scope of the embodiments of the present invention. It should be noted that, in the above-described specific embodiments, the specific features may be combined in any suitable manner without contradiction, so long as they do not deviate from the idea of the embodiments of the present invention, and they should also be regarded as the disclosure of the embodiments of the present invention.

Claims (5)

1. A digitally controllable delay chain comprising:
the reference voltage generation module is used for dividing the power supply voltage into a plurality of reference voltages;
a digital signal gating module for selecting a control voltage from a plurality of the reference voltages;
the clock delay module is used for delaying an input clock under the control of the control voltage;
the clock delay module comprises a delay circuit based on a back gate effect of the MOS device; the substrate voltage of the MOS device of the delay circuit is controlled by the control voltage;
the reference voltage generation module comprises a reference voltage generation circuit, wherein the reference voltage generation circuit comprises a plurality of resistors connected in series, the resistance value of each resistor is equal, and a plurality of reference voltages with equal intervals can be generated through the plurality of resistors;
the digital signal gating module comprises a thermal code gating circuit based on an MOS switch, wherein the thermal code gating circuit is used for gating a path of substrate voltage of an MOS device serving as the delay circuit from a plurality of reference voltages;
the delay circuit comprises a first-stage inverter and a second-stage inverter;
the first-stage inverter comprises a first PMOS transistor and a first NMOS transistor, wherein the source electrode of the first PMOS transistor is connected to a power supply voltage VDD, the substrate voltage of the first PMOS transistor is controlled by the control voltage, and the substrate of the first NMOS transistor is connected with the source electrode; alternatively, the substrate and the source of the first PMOS transistor are connected to the power supply voltage VDD, and the substrate voltage of the first NMOS transistor is controlled by the control voltage;
the second-stage inverter comprises a second PMOS transistor and a second NMOS transistor, wherein the substrate of the second PMOS transistor is connected with the source electrode, and the substrate of the second NMOS transistor is connected with the source electrode.
2. The digitally controllable delay chain of claim 1 wherein the number of resistors is positively correlated with the number of bits of a digital control signal of said digital signal gating module.
3. The digitally controllable delay chain of claim 2 wherein said resistor has a value of 2 N And pass 2 N A resistance of 2 N The reference voltages are equally spaced, where N is the number of bits of the binary digital control signal.
4. The digitally controllable delay chain of claim 1 wherein said thermal code gating circuit is capable of halving and gating a plurality of said reference voltages generated by said reference voltage generating circuit.
5. The digitally controllable delay chain of claim 4 wherein said thermal code gating circuit comprises N-stage gating switches, a first one of said N-stage gating switches comprising 2 N A second stage of the N-stage gating switches comprises 2 MOS switches N-1 A third stage of the N stage gating switches comprises 2 MOS switches N-2 A MOS switch, and so on, the N-th gating switch of the N-th gating switches comprises 2 1 A plurality of MOS switches; where N is the number of bits of the binary digital control signal.
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