CN109613323B - Programmable signal amplitude detection circuit - Google Patents
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- CN109613323B CN109613323B CN201811279437.8A CN201811279437A CN109613323B CN 109613323 B CN109613323 B CN 109613323B CN 201811279437 A CN201811279437 A CN 201811279437A CN 109613323 B CN109613323 B CN 109613323B
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Abstract
The invention relates to a programmable signal amplitude detection circuit, which comprises an amplitude detection circuit and a comparator circuit, wherein the amplitude detection circuit is used for detecting an externally input differential signal CKPAnd CKNBy a predetermined threshold reference voltage VTFor reference, a differential signal CK reflecting an external input is outputPAnd CKNAmplitude detection voltage V of amplitude magnitudeATo a comparator circuit for a certain threshold reference voltage VTAmplitude detection voltage VAIs inversely proportional to the amplitude of the externally input differential signal, and the amplitude detection voltage V is set for a given amplitude of the externally input differential signalAAnd a threshold reference voltage VTIs in direct proportion; a comparator circuit for comparing the amplitude detection voltage VAAnd a reference comparison voltage VRAnd generates an amplitude indication signal QCIndicating whether the voltage amplitude is sufficiently strong. The invention can be used for realizing flexible control of high-speed signal amplitude in circuits such as high-speed signal receiving, automatic gain control and the like.
Description
Technical Field
The invention relates to a programmable signal amplitude detection circuit, and belongs to the technical field of high-speed data interfaces.
Background
Data transmission rate in military electronic equipment such as broadband communication, radar navigation and electronic countermeasure is continuously improved. Because the transmission channel bandwidth is limited, for high-speed clock and data signals with the frequency exceeding 5GHz, signal distortion and distortion are generally reduced by controlling the amplitude of the signals, so that high-speed and high-reliability signal transmission is realized, and the power consumption of a signal transmission system can be reduced; however, since the signal is affected by noise, mismatch and other non-ideal factors during transmission, too small signal amplitude may cause the signal-to-noise ratio of the signal to be reduced, causing a problem of high-speed data error or poor quality of high-speed clock signal. In order to achieve the best performance of signal transmission, it is important to control the amplitude of high-speed transmission signals. Therefore, how to detect the high-speed clock or data signal and flexibly control and precisely adjust the amplitude of the high-speed signal is a technical problem to be solved in the field.
Disclosure of Invention
The technical problem of the invention is solved: the programmable signal amplitude detection circuit overcomes the defects of the prior art, obviously improves the precision and flexibility of high-speed signal amplitude detection and control, improves the quality of transmitted signals, and is favorable for improving the signal transmission rate and reliability.
The technical solution of the invention is as follows: a programmable signal amplitude detection circuit comprises an amplitude detection circuit and a comparator circuit, wherein the amplitude detection circuit is used for detecting an externally input differential signal CKPAnd CKNBy a predetermined threshold reference voltage VTFor reference, a differential signal CK reflecting an external input is outputPAnd CKNAmplitude detection voltage V of amplitude magnitudeATo a comparator circuit for a certain threshold reference voltage VTAmplitude detection voltage VAIs inversely proportional to the amplitude of the externally input differential signal, and the amplitude detection voltage V is set for a given amplitude of the externally input differential signalAAnd a threshold reference voltage VTIs in direct proportion;
a comparator circuit for comparing the amplitude detection voltage VAAnd a reference comparison voltage VRAnd generates an amplitude indication signal QCIndicating whether the voltage amplitude is sufficient.
The amplitude detection circuit comprises PMOS tubes M1, M2 and M3, resistors R1 and R2, and capacitors C1, C2 and C3;
the grid electrode of the PMOS tube M1 is connected with a resistor R1 and a capacitor C1, the drain electrode is grounded GND, the source electrode is connected with the source electrode of the PMOS tube M2, the drain electrode of the PMOS tube M3 and the capacitor C3 and is used as an amplitude detection voltage VAAn output terminal of (a); the other end of the resistor R1 is connected with a resistor R2 and is connected with an input end VTThe other end of the capacitor C1 is connected to the positive end CK of the clock input signalPThe other end of the capacitor C3 is grounded GND; the grid electrode of the PMOS tube M2 is connected with a resistor R2 and a capacitor C2, and the drain electrode is grounded GND; the other end of the capacitor C2 is connected with the clock input signal negative end CKN(ii) a The grid electrode of the PMOS tube M3 is connected with a bias voltage VBPAnd the source electrode is connected with a power supply VDD.
The programmable high-speed signal amplitude detection circuit further comprises a threshold programming circuit for generating a threshold reference voltage VTAnd a reference comparison voltage VRReference the threshold voltage VTSending to amplitude detection circuit, comparing voltage V with referenceRSent to the comparator.
The threshold programming circuit comprises: NMOS transistors M7 and M8, resistors R4, R5 and R6, and a resistor string circuit;
the gate of the NMOS transistor M7 is connected with the gate of the M8 and the bias voltage VBNSource connected to GND, drain connected to terminal V of resistor stringRn；
The source electrode of the NMOS tube M8 is grounded GND, and the drain electrode is connected with a resistor R4; the other end of the resistor R4 is connected with a resistor R5 and used as a reference comparison voltage VRAn output terminal of (a); the other end of the resistor R5 is connected with a power supply VDD; one end of the resistor R6 is connected with a power supply VDD, and the other end is connected with a resistor string head end VRpThe resistor string will be input to its head end VRpVoltage division of (1), with the division node as the threshold reference voltage VTTo the output terminal of (a).
The resistor string circuit is a programmable resistor string circuit, including: n same resistors Rs 1-RsN, N same switches S1-SN and a capacitor Cf, wherein N is more than or equal to 1;
the head end of the resistor Rs1 is connected to the input terminal of the switch S1 and to the resistor string VRnA terminal; the tail end of the resistor Rs1 is connected with the head end of the resistor Rs2 and the input end of the switch S2; the tail end of the resistor Rs2 is connected with the head end of the resistor Rs3 and the input end of the switch S3, and so on, the tail end of the resistor RsN-1 is connected with the head end of the resistor RsN and the input end of the switch SN; the end of the resistor RsN is connected to the resistor string VRpA terminal; control signals of the N same switches Sn are Kn and NKn, and output ends are connected with a capacitor Cf and used as a threshold reference voltage VTOutput port of which 0<N is less than or equal to N, and the other end of the capacitor Cf is grounded GND.
The resistor string circuit further comprises a decoding circuit for decoding the received M-bit binary code configuration signal A<M:1>Decoding to obtain a first control signal Kn and a second control signal NKn of K identical switches Sn, wherein 0<n≤K，K＝2M。
The decoding circuit adopts one-hot codes for encoding, namely the bit number N after A < M:1> decoding is equal to the state number N, and different states have different states, and only one bit is different from other bits.
The decoding circuit comprises: m input inverters, N nand gates and N output inverters, where N ═ 2M；
The mth input inverter is used for carrying out logical negation operation on the configuration code A < M > and outputting a control signal NA < M >, wherein M is more than or equal to 1 and less than or equal to M;
the nth NAND gate is used for carrying out NAND logical operation on the control signals A <1: n-1> and NA < n: M > and outputting a switching signal Kn; kn is input to the nth output inverter to generate a switch inverse signal NKn; only when a < M: n > is 0 and a < n-1:1> is 1, Kn is 0 and NKn is 1, otherwise Kn is 1 and NKn is 0.
The programmable high-speed signal amplitude detection circuit also comprises a bias circuit for providing a bias voltage V required by the amplitude detection circuit and the threshold programming circuitBPAnd VBN。
The bias circuit includes: NMOS tubes M4 and M5, a PMOS tube M6 and a resistor R3;
one end of the resistor R3 Is connected with the drain of the NMOS transistor M4, and the other end Is connected with the gates of the NMOS transistors M4 and M5 and the negative terminal of the current source Is, and Is used as a bias voltage VBNAn output terminal of (a); the source electrode of the NMOS tube M4 is grounded GND; the positive end of the current source Is connected with a power supply VDD; the source of the NMOS transistor M5 is grounded GND, and the drain is connected to the gate and drain of the PMOS transistor M6 as a bias voltage VBPAn output terminal of (a); the source of the PMOS pipe M6 is connected with the power supply VDD.
Compared with the prior art, the invention has the beneficial effects that:
(1) the programmable high-speed signal amplitude detection circuit can monitor the amplitude of the high-speed signal in real time, when the amplitude exceeds a certain threshold value, an amplitude indication signal is output, and programming control over the threshold value can be realized by inputting a configuration signal, so that the amplitude detection circuit can meet different application requirements;
(2) the programmable high-speed signal amplitude detection circuit is independent of a high-speed signal path, no additional influence is brought to high-speed signal transmission, and meanwhile, after the amplitude is locked, the programmable high-speed signal amplitude detection circuit can be independently closed through configuration to reduce the system power consumption;
(3) the threshold programming circuit realizes the programming control of the reference threshold voltage through the configuration signal, and can conveniently expand the configuration signal to N bits by expanding the structure of the decoder and the length of the resistor string, thereby not only improving the threshold programming precision, but also expanding the threshold programming range.
(4) The bias circuit has simple structure, can provide the required bias voltage for the amplitude detection circuit and the threshold programming circuit only by biasing of the external current source, and enhances the stability and the reliability of the circuit.
(5) The programmable high-speed signal amplitude detection circuit can realize the amplitude detection of high-speed clock and data signals, and has simple circuit structure, low power consumption and high reliability;
drawings
FIG. 1 is a block diagram of a programmable high-speed signal amplitude detection circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of an amplitude detection circuit according to an embodiment of the present invention;
FIG. 3 is a block diagram of a threshold programming circuit of an embodiment of the present invention;
FIG. 4 is a block diagram of a decoding circuit of an embodiment of the present invention;
FIG. 5 is a block diagram of a resistor string circuit according to an embodiment of the invention;
fig. 6 is a block diagram of a bias circuit of an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, common embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
As shown in fig. 1, a programmable high-speed signal amplitude detection circuit includes: amplitude detection circuit, threshold value programming circuit, biasing circuit and comparator circuit.
The amplitude detection circuit is used for detecting an externally input differential signal CKPAnd CKNBy a predetermined threshold reference voltage VTFor reference, a differential signal CK reflecting an external input is outputPAnd CKNAmplitude detection voltage V of amplitude magnitudeATo a comparator circuit for a certain threshold reference voltage VTAmplitude detection voltage VAIs inversely proportional to the amplitude of the externally input differential signal, and the amplitude detection voltage V is set for a given amplitude of the externally input differential signalAAnd a threshold reference voltage VTIs in direct proportion;
a threshold programming circuit for generating a threshold reference voltage VTAnd a reference comparison voltage VRReference the threshold voltage VTSending to amplitude detection circuit, comparing voltage V with referenceRSent to the comparator.
A bias circuit for providing a bias voltage V required by the amplitude detection circuit and the threshold programming circuitBPAnd VBN。
Comparator with a comparator circuitCircuit for comparing amplitude detection voltage VAAnd a reference comparison voltage VRAnd generates an amplitude indication signal QC。
According to the embodiment of the invention, the configuration signal A is used<2:0>Realize the reference voltage V to the threshold valueTAt high speed differential signal CKPAnd CKNIs lower than the threshold voltage, the amplitude detection voltage VAHigher than reference comparison voltage VRAt this time, the output amplitude indication signal Q is comparedCIs 1; when high speed differential signal CKPAnd CKNWhen the amplitude of (2) increases to the threshold voltage, the amplitude detection voltage VALower than a reference comparison voltage VRAt this time, the output amplitude indication signal Q is comparedCIs 0, thereby implementing an amplitude detection function for a high-speed signal. Meanwhile, the configuration signal can flexibly configure the threshold reference voltage VTAnd further, the threshold value of the high-speed signal amplitude detection circuit is programmed and controlled.
As shown in fig. 2, in a programmable high-speed signal amplitude detection circuit, the amplitude detection circuit includes:
PMOS tubes M1, M2 and M3, resistors R1 and R2, capacitors C1, C2 and C3;
the grid electrode of the PMOS tube M1 is connected with a resistor R1 and a capacitor C1, the drain electrode is grounded GND, the source electrode is connected with the source electrode of the PMOS tube M2, the drain electrode of the PMOS tube M3 and the capacitor C3 and is used as an amplitude detection voltage VAAn output terminal of (a); the other end of the resistor R1 is connected with a resistor R2 and is connected with an input end VTThe other end of the capacitor C1 is connected to the positive end CK of the clock input signalPThe other end of the capacitor C3 is grounded GND; the grid electrode of the PMOS tube M2 is connected with a resistor R2 and a capacitor C2, and the drain electrode is grounded GND; the other end of the capacitor C2 is connected with the clock input signal negative end CKN(ii) a The grid electrode of the PMOS tube M3 is connected with a bias voltage VBPAnd the source electrode is connected with a power supply VDD.
The capacitors C1 and C2 are used for high-speed signal AC coupling, can obtain the amplitude information of the high-speed signal and isolate the common mode level of the high-speed signal at the same time, and have a certain threshold reference voltage VTThe amplitude detection voltage V increases with the amplitude of the high-speed signalAGradually decreasing; to a certain degreeSignal amplitude, amplitude detection voltage VAWill follow the threshold reference voltage VTIs increased by an increase in;
as shown in fig. 3, in a programmable high-speed signal amplitude detection circuit, the threshold programming circuit includes: NMOS transistors M7 and M8, resistors R4, R5 and R6, and a resistor string circuit;
the gate of the NMOS transistor M7 is connected with the gate of the M8 and the bias voltage VBNSource connected to GND, drain connected to terminal V of resistor stringRn；
The source electrode of the NMOS tube M8 is grounded GND, and the drain electrode is connected with a resistor R4; the other end of the resistor R4 is connected with a resistor R5 and used as a reference comparison voltage VRAn output terminal of (a); the other end of the resistor R5 is connected with a power supply VDD; one end of the resistor R6 is connected with a power supply VDD, and the other end is connected with a resistor string head end VRpThe resistor string will be input to its head end VRpVoltage division of (1), with the division node as the threshold reference voltage VTTo the output terminal of (a).
The resistors R5 and R6 have equal resistance values, and R6 and the whole resistance value of the programmable resistor string are equal, namely the reference comparison voltage VREqual to the programmable resistor string VRpA terminal voltage; bias voltage VBNThe programming precision range of the threshold reference voltage is determined by controlling the current flowing through the resistor.
The resistor string circuit is a programmable resistor string circuit, including: n same resistors Rs 1-RsN, N same switches S1-SN and a capacitor Cf, wherein N is more than or equal to 1;
the head end of the resistor Rs1 is connected to the input terminal of the switch S1 and to the resistor string VRnA terminal; the tail end of the resistor Rs1 is connected with the head end of the resistor Rs2 and the input end of the switch S2; the tail end of the resistor Rs2 is connected with the head end of the resistor Rs3 and the input end of the switch S3, and so on, the tail end of the resistor RsN-1 is connected with the head end of the resistor RsN and the input end of the switch SN; the end of the resistor RsN is connected to the resistor string VRpA terminal; control signals of the N same switches Sn are Kn and NKn, and output ends are connected with a capacitor Cf and used as a threshold reference voltage VTOutput port of which 0<N is less than or equal to N, and the other end of the capacitor Cf is grounded GND.
The resistor string circuit further comprises a decoderA code circuit, a decoding circuit for configuring the received M-bit binary code signal A<M:1>Decoding to obtain a first control signal Kn and a second control signal NKn of K identical switches Sn, wherein 0<n≤K，K＝2M. The bit number of the configuration signal A determines the programming precision of the threshold reference voltage; and the resistance value of the resistor can be adjusted according to different design requirements.
The decoding circuit adopts one-hot codes for encoding, namely the bit number N after A < M:1> decoding is equal to the state number N, and different states have different states, and only one bit is different from other bits.
The decoding circuit comprises: m input inverters, N nand gates and N output inverters, where N ═ 2M；
The mth input inverter is used for carrying out logical negation operation on the configuration code A < M > and outputting a control signal NA < M >, wherein M is more than or equal to 1 and less than or equal to M;
the nth NAND gate is used for carrying out NAND logical operation on the control signals A <1: n-1> and NA < n: M > and outputting a switching signal Kn; kn is input to the nth output inverter to generate a switch inverse signal NKn; only when a < M: n > is 0 and a < n-1:1> is 1, Kn is 0 and NKn is 1, otherwise Kn is 1 and NKn is 0.
As shown in fig. 4, in the embodiment of the present invention, the configuration signal is a [2:0], the decoding circuit is configured to receive a three-bit binary code configuration signal a <2:0>, decode a <2:0> to obtain control signals Ki and NKi, where 0< i ≦ 8; the decoding circuit comprises: three input inverters, eight nand gates and eight output inverters;
the first input inverter is used for carrying out logical negation operation on the configuration code A <1> and outputting a control signal NA 1;
the second input inverter is used for carrying out logical negation operation on the configuration code A <2> and outputting a control signal NA 2;
the third input inverter is used for carrying out logical negation operation on the configuration code A <3> and outputting a control signal NA 3;
the first NAND gate is used for performing NAND logical operation on the control signals NA1, NA2 and NA3 and outputting a switching signal K1; k1 is input into the first output inverter to generate a switch inverse signal NK 1; only when a <3:1> -000, K1-0, NK 1-1;
a second nand gate, configured to perform a nand logic operation on the configuration signal a1 and the control signals NA2 and NA3, and output a switching signal K2; k2 is input into the second output inverter to generate a switch inverse signal NK 2; only when a <3:1> -001, K2-0, NK 2-1;
a third nand gate, configured to perform a nand logic operation on the configuration signal a2 and the control signals NA1 and NA3, and output a switching signal K3; k3 is input into a third output inverter to generate a switch inverse signal NK 3; only when a <3:1> -010, K3-0, NK 3-1;
a fourth nand gate, configured to perform a nand logic operation on the configuration signals a1 and a2 and the control signal NA3, and output a switching signal K4; k4 is input into a fourth output inverter to generate a switch inverse signal NK 4; only when a <3:1> -011, K4-0, NK 4-1;
a fifth nand gate, configured to perform a nand logic operation on the configuration signal a3 and the control signals NA1 and NA2, and output a switching signal K5; k5 is input into a fifth output inverter to generate a switch inverse signal NK 5; only when a <3:1> -100, K5-0, NK 5-1;
a sixth nand gate, configured to perform a nand logic operation on the configuration signals a1 and A3 and the control signal NA2, and output a switching signal K6; the K6 is input into a sixth output inverter to generate a switch inverse signal NK 6; only when a <3:1> -101, K6-0, NK 6-1;
a seventh nand gate, configured to perform a nand logic operation on the configuration signals a2 and A3 and the control signal NA1, and output a switching signal K7; the K7 is input into a seventh output inverter to generate a switch inverse signal NK 7; only when a <3:1> ═ 110, K7 ═ 0, NK7 ═ 1;
an eighth nand gate for performing a nand logic operation on the configuration signals a1, a2, and A3 and outputting a switching signal K8; the K8 is input into the eighth output inverter to generate a switch inverse signal NK 8; only when a <3:1> -111, K8-0, NK 8-1;
the decoding circuit uses the one-hot code principle, i.e. the number of bits equals the stateA number, and different states have one and only one bit different from the other. For example, when signal A is configured<3:1>When the decimal number is 0 when the current value is 000, the decoding result of the 8-bit switching signal Ki is 11111110, the switching inverse signal NKi is 00000001, and the lowest bit voltage of the resistor string is connected to the threshold reference voltage VTAn output end; when configuring signal A<3:1>When the decimal number is 4 when 100, the decoding result of the 8-bit switching signal Ki is 11101111, the inverse switching signal NKi is 00010000, and the intermediate voltage in the resistor string is switched on to the threshold reference voltage VTAn output end; when configuring the signal A<3:1>When the voltage is 111 and the corresponding decimal number is 7, the decoding result of the 8-bit switching signal Ki is 01111111, the inverse switching signal NKi is 10000000, and the highest bit voltage of the resistor string is connected to the threshold reference voltage VTAn output end;
as shown in fig. 5, in the present embodiment, the resistor string circuit is composed of eight identical resistors Rs1 to Rs8, eight identical switches S1 to S8, and a capacitor Cf; the head end of the resistor Rs1 is connected to the input terminal of the switch S1 and to the resistor string VRnA terminal; the tail end of the resistor Rs1 is connected with the head end of the resistor Rs2 and the input end of the switch S2; the tail end of the resistor Rs2 is connected with the head end of the resistor Rs3 and the input end of the switch S3, and so on, and the tail end of the resistor Rs7 is connected with the head end of the resistor Rs8 and the input end of the switch S8; the end of the resistor Rs8 is connected to the resistor string VRpA terminal; eight identical switches Sj have control signals Kj and NKj, and output ends are connected with a capacitor Cf and used as VTOutput port of which 0<j is less than or equal to 8; the other end of the capacitor Cf is grounded to GND.
Corresponding to N bits configuration signal A<N:1>The number of the resistors is 2NThe number of the switches is 2N. Thus, increasing the number of configuration signal bits can improve threshold programming accuracy, but the number of required resistors and switches can increase dramatically. The switching circuit Sj is opened only when the control signal Kj is 0 and NKj is 1; the capacitor Cf is used for decoupling filtering and stably outputting a threshold reference voltage VT。
As shown in fig. 6, the bias circuit includes: NMOS transistors M4 and M5, a PMOS transistor M6 and a resistor R3.
One end of the resistor R3 Is connected with the drain of the NMOS transistor M4, and the other end Is connected with the gates of the NMOS transistors M4 and M5 and the negative terminal of the current source Is, and Is used as a bias voltage VBNAn output terminal of (a); the source electrode of the NMOS tube M4 is grounded GND; the positive end of the current source Is connected with a power supply VDD; the source of the NMOS transistor M5 is grounded GND, and the drain is connected to the gate and drain of the PMOS transistor M6 as a bias voltage VBPAn output terminal of (a); the source of the PMOS pipe M6 is connected with the power supply VDD.
In addition, the comparator circuit is used for comparing the amplitude detection voltage VAAnd a reference comparison voltage VRAnd generates an amplitude indication signal QC(ii) a When V isA>VRTime, output amplitude indication signal Q C1, the differential signal CK inputted from the outside is representedPAnd CKNThe amplitude is not large enough, and further up-regulation is needed; otherwise, outputting an amplitude indication signal Q C0 indicates that the signal amplitude is sufficiently large.
In conclusion, the programmable high-speed signal amplitude detection circuit can realize the detection of the amplitude of the high-speed clock and data signals, and has the advantages of simple circuit structure, low power consumption and high reliability; the programming control of the threshold value can be realized by inputting the configuration signal, so that the amplitude detection circuit can meet different application requirements;
the embodiments in the present description are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
Claims (7)
1. A programmable signal amplitude detection circuit, characterized by: comprises an amplitude detection circuit and a comparatorAn amplitude detection circuit for detecting an externally input differential signal CKPAnd CKNBy a predetermined threshold reference voltage VTFor reference, a differential signal CK reflecting an external input is outputPAnd CKNAmplitude detection voltage V of amplitude magnitudeATo a comparator circuit for a certain threshold reference voltage VTAmplitude detection voltage VAIs inversely proportional to the amplitude of the externally input differential signal, and the amplitude detection voltage V is set for a given amplitude of the externally input differential signalAAnd a threshold reference voltage VTIs in direct proportion;
a comparator circuit for comparing the amplitude detection voltage VAAnd a reference comparison voltage VRAnd generates an amplitude indication signal QCIndicating whether the voltage amplitude is sufficient;
a threshold programming circuit for generating a threshold reference voltage VTAnd a reference comparison voltage VRReference the threshold voltage VTSending to amplitude detection circuit, comparing voltage V with referenceRSending to a comparator;
the threshold programming circuit comprises: NMOS transistors M7 and M8, resistors R4, R5 and R6, and a resistor string circuit;
the gate of the NMOS transistor M7 is connected with the gate of the M8 and the bias voltage VBNSource connected to GND, drain connected to terminal V of resistor stringRn；
The source electrode of the NMOS tube M8 is grounded GND, and the drain electrode is connected with a resistor R4; the other end of the resistor R4 is connected with a resistor R5 and used as a reference comparison voltage VRAn output terminal of (a); the other end of the resistor R5 is connected with a power supply VDD; one end of the resistor R6 is connected with a power supply VDD, and the other end is connected with a resistor string head end VRpThe resistor string will be input to its head end VRpVoltage division of (1), with the division node as the threshold reference voltage VTAn output terminal of (a);
the resistor string circuit is a programmable resistor string circuit, including: n same resistors Rs 1-RsN, N same switches S1-SN and a capacitor Cf, wherein N is more than or equal to 1;
the head end of the resistor Rs1 is used as the head end of the programmable resistor string circuitThe input terminal of the switch S1 is connected to the resistor string VRnA terminal; the tail end of the resistor Rs1 is connected with the head end of the resistor Rs2 and the input end of the switch S2; the tail end of the resistor Rs2 is connected with the head end of the resistor Rs3 and the input end of the switch S3, and so on, the tail end of the resistor RsN-1 is connected with the head end of the resistor RsN and the input end of the switch SN; the end of the resistor RsN is connected to the resistor string V as the end of the programmable resistor string circuitRpA terminal; control signals of the N same switches Sn are Kn and NKn, and output ends are connected with a capacitor Cf and used as a threshold reference voltage VTOutput port of which 0<N is less than or equal to N, and the other end of the capacitor Cf is grounded GND.
2. The programmable signal amplitude detection circuit of claim 1, wherein the amplitude detection circuit comprises: PMOS tubes M1, M2 and M3, resistors R1 and R2, capacitors C1, C2 and C3;
the grid electrode of the PMOS tube M1 is connected with a resistor R1 and a capacitor C1, the drain electrode is grounded GND, the source electrode is connected with the source electrode of the PMOS tube M2, the drain electrode of the PMOS tube M3 and the capacitor C3 and is used as an amplitude detection voltage VAAn output terminal of (a); the other end of the resistor R1 is connected with a resistor R2 and is connected with an input end VTThe other end of the capacitor C1 is connected to the positive end CK of the clock input signalPThe other end of the capacitor C3 is grounded GND; the grid electrode of the PMOS tube M2 is connected with a resistor R2 and a capacitor C2, and the drain electrode is grounded GND; the other end of the capacitor C2 is connected with the clock input signal negative end CKN(ii) a The grid electrode of the PMOS tube M3 is connected with a bias voltage VBPAnd the source electrode is connected with a power supply VDD.
3. The programmable signal amplitude detection circuit of claim 1, wherein the programmable resistor string circuit further comprises a decoding circuit for decoding the received M-bit binary code configuration signal A<M:1>Decoding to obtain a first control signal Kn and a second control signal NKn of K identical switches Sn, wherein 0<n≤K，K＝2M。
4. A programmable signal amplitude detection circuit as claimed in claim 3, wherein the decoding circuit is encoded using a one-hot code, i.e. the number of bits N after a < M:1> decoding is equal to the number of states N, and only one bit of the different states is different from the other bits.
5. The programmable signal amplitude detection circuit of claim 4, wherein the decoding circuit comprises: m input inverters, N nand gates and N output inverters, where N ═ 2M；
The mth input inverter is used for carrying out logical negation operation on the configuration code A < M > and outputting a control signal NA < M >, wherein M is more than or equal to 1 and less than or equal to M;
the nth NAND gate is used for carrying out NAND logical operation on the control signals A <1: n-1> and NA < n: M > and outputting a switching signal Kn; kn is input to the nth output inverter to generate a switch inverse signal NKn; only when a < M: n > is 0 and a < n-1:1> is 1, Kn is 0 and NKn is 1, otherwise Kn is 1 and NKn is 0.
6. The programmable signal amplitude detection circuit of claim 1, further comprising a bias circuit for providing a bias voltage V required by the amplitude detection circuit and the threshold programming circuitBPAnd VBN。
7. The programmable signal amplitude detection circuit of claim 6, wherein the bias circuit comprises: NMOS tubes M4 and M5, a PMOS tube M6 and a resistor R3;
one end of the resistor R3 Is connected with the drain of the NMOS transistor M4, and the other end Is connected with the gates of the NMOS transistors M4 and M5 and the negative terminal of the current source Is, and Is used as a bias voltage VBNAn output terminal of (a); the source electrode of the NMOS tube M4 is grounded GND; the positive end of the current source Is connected with a power supply VDD; the source of the NMOS transistor M5 is grounded GND, and the drain is connected to the gate and drain of the PMOS transistor M6 as a bias voltage VBPAn output terminal of (a); the source of the PMOS pipe M6 is connected with the power supply VDD.
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| CN201811279437.8A CN109613323B (en) | 2018-10-30 | 2018-10-30 | Programmable signal amplitude detection circuit |
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| CN111208347A (en) * | 2020-03-16 | 2020-05-29 | 成都纳能微电子有限公司 | High-speed differential signal amplitude detection circuit |
| CN112383291B (en) * | 2020-11-10 | 2023-04-28 | 北京智芯微电子科技有限公司 | Digital controllable delay chain |
| CN116859112B (en) * | 2023-09-05 | 2023-11-21 | 中国电子科技集团公司第十四研究所 | Dynamic amplitude monitoring circuit for improving precision |
| CN117650072B (en) * | 2023-11-28 | 2024-06-14 | 广州润芯信息技术有限公司 | Process detection method, system and circuit |
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