CN102624346A - Automatic gain amplification circuit with inverse exponential characteristic type digital control circuit - Google Patents
Automatic gain amplification circuit with inverse exponential characteristic type digital control circuit Download PDFInfo
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Abstract
The invention discloses an automatic gain amplification circuit with an inverse exponential characteristic type digital control circuit, which is formed by a digital variable gain amplifier, a 2-bit flash analog-to-digital converter of a digital circuit and the inverse exponential characteristic type digital control circuit, wherein the digital variable gain amplifier is formed by cascading a plurality of digital variable gain amplifier stages; the 2-bit flash analog-to-digital converter comprises three comparator circuits, a coding circuit and a fixed reference voltage configuration circuit; and the inverse exponential characteristic type digital control circuit comprises a peak detector, a subtracter circuit, an integrator circuit and a decoding circuit. The inverse exponential characteristic type digital control circuit detects a digital signal output by the 2-bit flash analog-to-digital converter; the detected signal amplitude is compared with a reference value of a reference voltage by the subtracter circuit; and after a comparison result is integrated and decoded, a feedback control signal is output to regulate the gain of the variable gain amplifier PGA (Programmable Gain Amplifier). The automatic gain amplification circuit further comprises a switch for the control circuit, the switching between the inverse exponential characteristic type digital control circuit and an external control circuit can be implemented, and the automatic gain amplification circuit is particularly suitable for a radio frequency front-end circuit with the requirements on few off-chip components and compact structure.
Description
Background technology
Along with the continuous appearance of areas of information technology new technology and the continuous progress of technology, the radio-frequency front-end of various receiver systems and baseband chip have all been obtained bigger development in recent years.Radio frequency chip and High-speed Control scheme with high integration more and more receive people's favor; This radio frequency chip requires outer member minimum, needs to control automatically amplifying circuit simultaneously for the enough fast degree of catching up with the input signal variation of the reaction speed of input signal.
As everyone knows; The radio frequency chip of high integration requires the outer member of chip few more good more; The automatic gain control amplifier circuit of traditional reaction type all requires must have a big electric capacity to offer charge pump outside the chip and discharges and recharges, and the numeral of this electric capacity is generally greater than 1n, and this has just determined that such electric capacity can not be integrated in our radio frequency chip; Need to add extra chip pin output; So not only increased the pin of chip, and, both increased pin and also increased power consumption because the influence of the big dead resistance of the output port of chip can cause circuit need increase extra electric current.
The formation of traditional controllable gain amplifier comprises the amplifier main circuit, control circuit, testing circuit and with reference to input circuit.In the prior art, front end signal amplifies through gain adjustable amplifier wherein, and the control of gain adjustable amplifier normally realizes with analog control circuit.Though the continuable adjusting gain of analog control circuit size realizes the seamless link of each stepping, has significant disadvantages, the speed of regulating continuously is slow, can only adopt charge pump circuit to improve the speed of adjusting.The paper name of prior art is called " design and the realization of low-power consumption charge pump programmable gain amplifier "; Adopt the electric current that increases charge pump to improve the speed of adjusting; This implementation makes operating current increase by an one magnitude, and the ripple of controlling simultaneously on the voltage increases, and has directly caused the reduction of the signal to noise ratio of output signal; So this analog control circuit can only be suitable for the gain adjustable amplifier not too high to stabilization signal time requirement; Be not suitable for the exigent occasion of continuous variation to signal, and the system very high to the time requirement of stabilization signal, for example digital television system.
If there is a kind of automatic gain control amplifier can not need the outside electric capacity that increases; The integrated level of raising system; And satisfy input signal and set up fast and stable demand, owing to change than very fast some noncontinuities that change when intermediate-freuqncy signal is stablized; Can not cause interference effect, thereby better adapt to the ever-increasing market demand of technology for radio frequency field letter new technology system.
Summary of the invention
The invention belongs to the technology for radio frequency field; Relate to a kind of automatic gain amplifying circuit with anti-indicial response type digital control circuit; Relate in particular to a kind of anti-indicial response type digital control circuit; Amplifying electric circuit with auto-gain-controlling function of the present invention is used for radio-frequency transmitter, and it is mainly used in the application that needs under the big dynamic range signal initial conditions, and baseband chip can select to provide or do not provide the application scenario of FEEDBACK CONTROL when being particularly useful for needing integrated level very high.
Summary of the invention
The objective of the invention is to be the above problem of controllable gain amplifying circuit in the radio frequency receiver front end formation that solves prior art; A kind of automatic gain amplifying circuit with anti-indicial response type digital control circuit is provided; It does not need external capacitive; Be integrated into the variable gain amplifier module of numeral; The anti-indicial response type digital control circuit that module carries adopts the anti-indicial response of the common generation of digital decoder and digital amplifier, the increase of going forward one by one of digital decoder ride gain, and the every stage gain stepping of digital amplifier all is the dB stepping; Be combined to form anti-index control characteristic, be used for the fast-changing high integration radio-frequency transmitter of input signal and other need carry out the receiver of quick processing and amplifying to signal.The function that it removes the variable gain amplifier of the numeral that possesses traditional receiver has also reduced outside charge and discharge capacitance, can better reduce hardware and system power dissipation, improves system signal noise ratio.
The present invention combines variable gain amplifier and a kind of new digital control pattern of numeral, is utilizing hardware resource to greatest extent and is practicing thrift on the basis of expense outside the sheet, with the small-signal amplification of front end; Offering the digital baseband process chip handles; Thereby make this radio frequency chip can be applied to fast-changing input signal occasion, saved outer member, reduced circuit overhead and power consumption; The performance of raising system; And the sensitivity of radio-frequency transmitter etc., can also reduce equipment power dissipation and volume thus, practice thrift cost.A kind of automatic gain amplifying circuit of the present invention with anti-indicial response type digital control circuit; Applicable to the simulated television radio frequency chip on DTV and the bus; Be particularly suitable for the integrated level of system is required very high, the workplace that needs the fast reaction input signal to change simultaneously again.
Above-mentioned purpose of the present invention is to realize through following technical scheme:
A kind of automatic gain amplifying circuit with anti-indicial response type digital control circuit; It is characterized in that: it is the two-way differential configuration that said automatic gain amplifying circuit with anti-indicial response type digital control circuit is called for short the automatic gain amplifying circuit, and the composition of automatic gain amplifying circuit comprises:
The variable gain amplifier (PGA) of numeral,
The quickflashing analog to digital converter, and
Anti-indicial response type control circuit; Wherein
The variable gain amplifier of said numeral is the variable-gain amplification circuit of a multi-stage cascade;
Said quickflashing analog to digital converter is a 2bit quickflashing analog to digital converter; The analog signal that the two-way radio-frequency differential gain of the variable gain amplifier of numeral output is amplified converts digital signal respectively into, delivers to the input of the anti-indicial response type of two-way digital control circuit module;
Said anti-indicial response type control circuit is anti-indicial response type digital control circuit, and the range signal that is used for that 2bit quickflashing analog to digital converter is quantized is handled the back and produced the 2bit control signal to the variable gain amplifier of numeral.
Described automatic gain amplifying circuit; It is that the automatic gain amplifying circuit is a programmable-gain module in the radio-frequency front-end; This module is a two-way difference automatic gain amplification circuit structure; The input of every road automatic gain amplifying circuit inserts the radio-frequency front-end intermediate-freuqncy signal; The output of two-way automatic gain amplifying circuit connects next stage digital baseband process chip respectively, and the external interface of programmable-gain module comprises reference value port and gain digital control port of the reference voltage that two-way signal input end of intermediate frequency and two-way are shared;
The reference value of said reference voltage is a digital values of built-in chip type, and one of the inside that the reference value port of reference voltage connects radio-frequency transmitter is register fixedly, is used to provide final stable reference foundation;
The reference value Vref of system's setting is that the reference voltage that the LDO circuit of level base-band digital processing module after coming from provides is a reference voltage.
Said gain digital control port connects the output control terminal mouth of anti-indicial response type digital control circuit or the output control terminal mouth of next stage digital baseband process chip.
Described moving gain amplifying circuit, it is that the variable-gain amplification circuit of said multi-stage cascade comprises M the digital variable gain amplifying stage that is connected in series, the M span is 7～3; Depend on needs how many controlled dynamic ranges in the reality, as preferably, the M value is 5, with Pyatyi digital variable gain amplifying stage series connection cascade; The input of the 1st stages of digital variable gain amplifying stage of M digital variable gain amplifying stage connects one road radio-frequency differential input signal and connects, and the output of M stages of digital variable gain amplifying stage connects the right input of 2bit quickflashing analog to digital converter; 2bit quickflashing analog to digital converter with the two-way differential gain amplifying signal of programmable-gain module output receive anti-indicial response type digital control circuit module two inputs, feed back to the digital control port of digital variable gain amplification grade circuit after the processing.
Described automatic gain amplifying circuit, it is said anti-indicial response type digital control circuit by peak detector, subtraction circuit, digital integrator circuit and decoding circuit are formed; Anti-indicial response type digital control circuit is anti-indicial response circuit, wherein
Two input signal ends of said subtraction circuit connect the output and the reference value end of peak detector, and the output of subtraction circuit connects digital integrator circuit input;
Said digital integrator circuit and decoding circuit are connected in series, and the digital integrator circuit adopts two fens algorithm digital integrations, and the digital integrator circuit output end connects decoding circuit;
Said decoding circuit input connects digital integrator circuit output; The decoding circuit output connects the gain control end of M the digital variable gain amplifying stage that is connected in series of digital variable-gain amplification circuit; Decoding circuit obtains optimum control output with the digital integrator circuit the soonest with two fens algorithms and does the decoding processing, the output control signal.
Anti-indicial response type digital control circuit detects wherein maximum amplitude part with the amplitude output signal of 2bit quickflashing analog-digital converter circuit through peak detector; Subtraction circuit compares back output numeral output result relatively with the amplitude of detected maximum and the reference value of chip internal; This result is through a digital integrator circuit, and the result behind the integration feeds back to the digital control port of the variable gain amplifier of numeral again through a digital decoder decoding back output.
Two input signals of subtraction circuit are respectively peak detector to the output peak value sampling of 2bit quickflashing analog to digital converter with from the fixing reference value of register of chip internal; Subtraction circuit subtracts each other the relatively output result that the back directly quantizes to obtain two signals with two inputs, and the digital integrator circuit that offers the back level is made further quantification treatment.
The digital integrator circuit function is through in the time of setting, the output comparative result of subtracter being carried out statistical analysis, digital integrator export to decoding circuit, finally providing gain by decoding circuit increases the control signal that reduces or keep.The integral result of digital integrator is to compare with the comparative voltage of setting; Comparative voltage is set at the set point of two different numerical value of height, if the integral result of integrator is higher than high set point, integral result is set at yield value is reduced so; If the integral result of integrator is lower than low set point; Integral result is set at so increases gain, if the integral result of integrator between two high and low set points, to be set at yield value constant for the result so.
Anti-indicial response type digital control circuit provides the control signal of anti-indicial response; Its output connects the variable gain amplifier of numeral; The amplifier's gain that makes numeral is with the anti-index linear change of control voltage dB-linear; Control signal output connects the gain control end of each digital variable gain amplifying stage, and the variable gain amplifier of control figure is to the undistorted amplification of input signal.
If adopt switchable digital control circuit; When the digital baseband processing module requires gain to increase; Control its switch switches to the external digital control circuit, at first is increased to intermediate gain, if gain is too big; Be increased to the gain of the mean value of maximum gain and intermediate gain, and the like up to finding optimum gain controlling word; Otherwise, if when requiring gain to reduce, at first be reduced to intermediate gain, if gain is too little, reduce to the gain of the mean value of least gain and intermediate gain, and the like up to the gain controlling word that finds optimum.
Described automatic gain amplifying circuit; It is that said 2bit quickflashing analog to digital converter comprises three comparator circuits, coding circuit and fixed reference potential configuration circuit; Three comparators adopt the high-speed comparator of same structure, adopt based on quickflashing analog-to-digital conversion structure; Input signal inserts the reference voltage of three comparators and three comparators simultaneously and makes comparisons; The input of the reference voltage of two comparators all comes from the fixed reference potential configuration circuit; By the divider resistance string supply voltage dividing potential drop is produced, the output of two comparators is through forming the range signal position of 2bit after the digital coding combination of circuits; The reference voltage of another comparator is ground, and the comparative result of comparator output is the mark signal position of 2bit.
Described automatic gain amplifying circuit, it is that the subtraction circuit of said anti-indicial response type digital control circuit comprises a subtracter and comparator that is connected in series; A comparator is that the parallelly connected comparator of output is right; The reference value of the variable gain amplifier of numeral being exported the Signals & Systems inner setting compares; The output signal offers the integrator integration; The change direction of controlled signal thus, the yield value of the variable-gain amplification circuit in the digital control voltage control digital amplifier that provides by decoding circuit, the variable gain amplifier output voltage amplitude that guarantees numeral is within the scope of setting.
Described automatic gain amplifying circuit; It is that said digital variable gain amplifying stage is the Precise Discrete gain amplifier; It is based on the amplifier of discrete gain dB stepping of the precise gain control of resistance-feedback network; Comprise the wake flow source, difference amplifier tube, the variable negative feedback resistor of variable load resistance and source class; Be used for the precise figures control voltage that the anti-Kui rotation road according to digital control pattern provides, the gain of control automatic gain amplifying circuit is for back one-level digital baseband processing module chip provides the radio-frequency front-end signal of high-gain with the big range of linearity.
Described automatic gain amplifying circuit; It is that said M the digital variable gain amplifying stage that is connected in series is the digital gain amplifying circuit of the adjustable band common-mode feedback of resistance; The circuit of every stages of digital variable gain amplifying stage is basic identical; The resistance of corresponding adjustment gain is different with the resistance of feedback circuit, and the digital control termination digital control circuit of circuit is used for the accurately digital amplifier's gain of adjustment.
As preferably, adopt Pyatyi digital variable gain amplification grade circuit to be connected in series; The basic structure circuit of Pyatyi digital variable gain amplifying stage is identical, and the digital control end linking number word control circuit output of circuit is used for accurately adjusting the gain of digital variable gain amplifying stage; The afterbody digital variable gain amplifying stage of the variable gain amplifier of numeral adopts and what identical structure of front, has just increased the electric current of circuit, has reduced the output resistance of circuit, is used to provide driving force and big output voltage swing.
Described automatic gain amplifying circuit; It is that also said automatic gain amplifying circuit with anti-indicial response type digital control circuit also comprises a control model diverter switch; Carry anti-indicial response type digital control circuit in the automatic gain amplifying circuit sheet and can constitute a kind of automatic gain amplifying circuit of switchable many control models with the outer one or more control circuits of sheet; By digital baseband processing module chip controls control automatic gain amplifying circuit sheet internal schema diverter switch the two-way control model is switched; Realize the switching of anti-indicial response type digital control circuit and external control circuit, break off anti-indicial response type digital control circuit, connect external control circuit; Vice versa, is used to realize the switching of various control pattern.
A kind of automatic gain amplifying circuit with anti-indicial response type digital control circuit comprises the variable gain amplifier of numeral, the digital gain control circuit of anti-indicial response type, 2bit quickflashing analog to digital converter, and digital decoder.The variable gain amplifier of numeral comprises a plurality of digital variable gain amplifying stages.Digital variable gain amplifying stage adopts the amplifier architecture of the adjustable band common-mode feedback of resistance, and the basic digital variable amplifier circuit of afterbody provides big driving force and big output voltage swing.
Anti-indicial response type digital control circuit feeds back to digital variable-gain amplification circuit with testing result, guarantees that the output amplitude of digital variable gain amplifier is constant basically, gives adc circuit and accurately samples;
The gain-changeable amplifier circuit of the numeral of automatic gain amplifying circuit can be regulated the gain size through regulating load and source negative feedback changes in resistance; Implementation is simple; And the structure of each digital variable gain amplifying stage is basic identical; Make the simplicity of design of digital decoder, the layout design of circuit is also simple relatively.
Anti-indicial response type digital control circuit is by peak detector, subtraction circuit, and digital integrator circuit and decoding circuit are formed.Anti-indicial response type digital control circuit detects wherein maximum amplitude part with the amplitude output signal of 2bit quickflashing analog to digital converter through peak detector; Subtraction circuit is with the detected amplitude peak of peak detector; Promptly be that the output of the range signal position of 2bit quickflashing analog to digital converter is added up, the output digital signal is after comparing with the fixed reference Vref of chip internal; Output numeral output result relatively; This result is through digital integrator circuit integration, and again through the decoding circuit of a numeral, the control signal port of the numeral of the variable gain amplifier that feeds back to numeral is exported in the decoding back with the result behind the integration.
When the automatic gain amplifying circuit works under the automatic gain control mode; If input signal a little less than; ADC can offer digital control circuit with the changes in amplitude information that quantizes; Anti-indicial response type digital control circuit compares the amplitude and the reference voltage of the signal of output, and with the integration as a result that repeatedly compares, obtaining gain according to the threshold value that is provided with in advance simultaneously is the variation of phase transformation general orientation; Then the result is offered digital decoder, digital amplifier's gain is set in high gain mode work by digital decoder.When input signal is strong; ADC can offer digital control circuit with the changes in amplitude information that quantizes; Anti-indicial response type digital control circuit compares the amplitude and the reference voltage of the signal of output, and with the integration as a result that repeatedly compares, obtaining gain according to the threshold value that is provided with in advance simultaneously is the direction variation that diminishes mutually; Then the result is offered digital decoder, digital amplifier's gain is set in low gain mode work by digital decoder.
Digital integrator circuit in the anti-indicial response type digital control circuit adopts two fens algorithms to come the fastest searching to obtain optimum control and exports to decoding circuit, handle successively and find optimum gain controlling word.This algorithm that adopts can find in certain input fast will reach the corresponding digital control word of exporting signal down; Can improve the corresponding time of system so greatly for input signal; Be different from traditional base band that needs simultaneously the scheme of Control and Feedback is provided; Just accomplish this automatic fast controlled function in the inside of radiofrequency signal, can reduce the time of delaying owing to communication owing between radio frequency and the baseband chip, reduced the hardware spending of base band simultaneously.
Adopt digital integrator with the integrator in the anti-indicial response type digital control circuit; Adopt digital integrator to compare and to reduce hardware spending with analogue integrator; The integrator of simulation is done the integration of long time if desired and need be added electric capacity simultaneously; And digital integrator does not need, like this can save pins, pare down expenses.
Advantages such as control AGC realizes that the feedback and the two kinds of patterns that feedover are arranged automatically, and feedback-type AGC is a closed loop configuration, has strong robustness, and precision is high, and low-frequency noise is lower.Yet, because feedback-type AGC loop bandwidth is lower than signal bandwidth, so its settling time is long.The present invention has adopted numerically controlled PGA and anti-indicial response type digital control circuit in order to satisfy the requirement of quick settling time of some system requirements, shortens settling time greatly, improves systematic function.
The progression M value of the variable gain amplifier of numeral of the present invention is selected through optimization; Realize as the basic identical structural circuit of preferred employing Pyatyi; Main purpose is the optimization that reaches power consumption and bandwidth, adopts the disposal ability that can utilize the hardware digital circuit based on the digital control unit of the dichotomy algorithm of integrator, accomplish that simulation control can't realize algorithm; Do not receive the influence of temperature, technology, noise etc., can realize controlling more accurately.Able to programmely make control more flexible, can the needed characteristic of easier realization.
With the automatic gain amplifying circuit of anti-indicial response type digital control circuit, carry the automatic gain amplifying circuit that anti-indicial response type digital control circuit can constitute a kind of switchable many control models with the outer one or more control circuits of sheet in its sheet.Different system and digital baseband process chip can select for use above-mentioned any scheme to realize; The present invention proposes an integrated circuit can satisfy above-mentioned a plurality of requirement simultaneously; Especially in the chip miniaturization; Under the increasingly high market background of integrated level; This integrated integral system of simulating controllable intermediate frequency amplifier and digital programmable control intermediate frequency amplifier can well adapt to the multimode multi frequency system and require and only adopt a cover hardware spending, has saved a large amount of areas, makes the hardware multiplexing of system reach maximization.
Substantial effect of the present invention:
1, a kind of automatic gain amplifying circuit with anti-indicial response type digital control circuit of the present invention can be able to adapt to the needs of many fast-changing system requirements of input and quick response of other needs and high integration work system.
2, the present invention has the digital control function of anti-indicial response type, and circuit structure makes chip exterior need not to add electric capacity, can better reduce hardware and system power expense, improves system signal noise ratio, optimization system design.
3, the dichotomy algorithm of circuit adding of the present invention, the corresponding different inputs of ability obtain corresponding digital fast and control voltage.
4, circuit digital control model of the present invention is utilized 2bit quickflashing analog to digital converter and peak detector; Utilize the integrating circuit disposal ability of Digital Implementation simultaneously; Accomplish the dichotomy algorithm, do not receive the influence of temperature, technology, noise etc., can realize more accurately control more flexibly.
Description of drawings
Fig. 1 is a conventional analogue peak value detection type AGC control mode schematic block circuit diagram.
Among the figure: 101 is the variable gain amplifier of numeral, and 102 is peak detector, and 103 is a logarithmic amplifier; 104 is low pass filter, and wherein 142 is the resistance of low pass filter, and 141 is external filters electric capacity; 105 is correlator, and Vref is the reference voltage of input.
Fig. 2 is traditional charge-pump type AGC control mode schematic block circuit diagram.
Among Fig. 2: 201-203 is the variable gain amplifying stage of multi-stage cascade in the variable gain amplifier of numeral, and 204 are the fixed gain level, and 205 is voltage-current converter; 206 and 207 is that comparator is right, the 208th, and charge pump, 209 is capacitor C 3; 210 and 211 are respectively the biasing resistor on the differential signal path; 212 is that analog to digital converter is right, and VINP and VINN are differential input signal, and Vbias1 and V bias2 are the bias voltage on the differential signal path; Vref is a reference voltage, and VOUTP and VOUTN are differential output signal.
Fig. 3 constitutes block diagram for the automatic gain amplifying circuit with anti-indicial response type digital control circuit of the embodiment of the invention;
Among Fig. 3: 31 is the variable gain amplifier of numeral, and 32 is 2bit quickflashing analog to digital converter, and 33 is anti-indicial response type digital control circuit; Wherein 301 is peak detector, and 302 is subtraction circuit, and 303 is the digital integrator circuit; 304 is decoding circuit, and VIN is an input signal.
Fig. 4 is the forming circuit figure of digital variable gain amplifying stage in the automatic gain amplifying circuit of the present invention;
Among Fig. 4: I1, I2 are tail current source, and M1, M2 are the differential signal input pipe, and RL is the variable load resistance of differential signal, and Rd is the variable negative feedback resistor of source class.
Fig. 5 adopts the 2bit quickflashing analog-digital converter circuit in the automatic gain amplifying circuit of the anti-indicial response type of band of the present invention digital control circuit to constitute schematic block diagram.
Among Fig. 5: 51 ~ 53 is comparator circuit, R1, and R2, R3 are the divider resistance that is used to produce reference voltage, and 54 is coding circuit, and 55 is the comparative voltage bleeder circuit.
Fig. 6 for the embodiment of the invention with the automatic gain amplifying circuit of anti-indicial response type digital control circuit and the schematic block diagram that is connected of digital baseband processing module.
Among Fig. 6: 61 is the digital integrator circuit, and 62 is decoding circuit, and 63 is peak detector, and 64 is subtraction circuit, and 65,66 is dichotomy algorithm circuit, and 63 is the output from 2bit quickflashing analog to digital converter range signal position.
Fig. 7 for the embodiment of the invention with the automatic gain amplifying circuit of anti-indicial response type digital control circuit and digital baseband block join and another kind formation schematic block diagram.
Among Fig. 7: 71 are the amplifying electric circuit with auto-gain-controlling function with anti-indicial response type digital control circuit, and 72 is the chip of digital baseband processing module, and 701 is the variable gain amplifier of numeral; 702 is 2bit quickflashing analog to digital converter; 703 is anti-indicial response type digital control circuit, and wherein 711 is peak detector, and 712 is decoding circuit; 713 is the digital integrator circuit, and 714 is subtraction circuit.
Fig. 8 is the formation block diagram of the anti-indicial response type digital control circuit of the embodiment of the invention
Among Fig. 8: 81 are configured in the external control pattern for the digital Auto Gain control amplifier; 82 is the chip of digital baseband processing module; 801 is the variable gain amplifier of numeral, and 802 is 2bit quickflashing analog to digital converter, and 803 is the anti-indicial response type digital control circuit of band in the sheet; 804 is the diverter switch of band in the sheet, and 83 is sheet outer control circuit.
The control circuit theory diagram of the AGC of traditional peak value detection type is as shown in Figure 1; The variable gain amplifier 101 of the numeral that simulation AGC is made up of the cascade of some stage gain amplifying stages; Peak detector 102, logarithmic amplifier 103, low pass filter 104 and correlator 105 are formed.In whole radio-frequency receiving system; AGC is between plural intermediate-frequency filter and analog to digital converter ADC; It is according to the intermediate-freuqncy signal intensity that receives, and other amplifies to carry out the different gains level, and the intensity stabilization of making every effort to make the output signal is on certain level; Thereby give relatively-stationary input voltage of follow-up adc circuit, let ADC reach preferable performance and bigger signal to noise ratio with lower resolution.But low pass filter will obtain the filter capacitor that lower cut-off frequency must add a high capacitance.
The charge-pump type agc circuit theory diagram of prior art is as shown in Figure 2; The charge-pump type agc circuit is by the variable gain amplifier 201 of the numeral of multistage variable gain amplifying stage cascade; Fixed gain amplifying stage 202, ADC converter 203, control logic 204; Charge pump circuit 205, electric capacity 206 is formed with V-I change-over circuit 207.Variable gain amplifier VGA and fixed gain amplifying stage 202 that input signal VINP and VINN get into numeral amplify; Compare in ADC converter 203 and the reference voltage Vref of setting; The comparator 206 of difference and 207 output are through 209 charge or discharge of 208 couples of C3 of charge pump circuit (external) electric capacity; Make the input of its output appropriate control voltage to voltage-current converter circuit 205; 205 convert voltage control signal into current controling signal; Deliver to the control end of variable gain amplifying stage 201～203, control the gain of variable gain amplifying stages at different levels, thereby the amplifying signal that difference is amplified on the path is exported intermediate frequency amplified output signals VOUTP and VOUTN through analog to digital converter to 212.
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Embodiment
Through embodiment and combine accompanying drawing, technical scheme of the present invention is further specified below.
First embodiment
The big circuit of the automatic gain with anti-indicial response type digital control circuit that Fig. 3 has provided the embodiment of the invention constitutes block diagram.Explain that in conjunction with Fig. 3 automatic control mode is realized constituting among the present invention, it is 5 that the M value is set.Input signal VIN gets into the input of the variable gain amplifier 31 of numeral; The variable gain amplifier of numeral is that the variable gain amplifying stage cascade of Pyatyi connects; 2bit quickflashing analog to digital converter 32 is received in the output of the variable gain amplifier 31 of numeral; The range signal position of 2bit quickflashing analog to digital converter 32 outputs to the peak detector 301 in the anti-indicial response type digital control circuit 33; The reference value that the output of peak detector 301 and chip provide compares through subtraction circuit 302, and the output of subtraction circuit 302 offers 303 digital integrator circuit, and the output of 303 digital integrators offers decoding circuit 304; Decoding circuit 304 will be controlled direction and transfer digital controlled signal to; The gain-changeable amplifier circuit of control 31 numerals, the gain-changeable amplifier circuit of 31 numerals is given 322bit analog to digital converter with stable amplitude, so that guarantee the output that can obtain full range signal of analog digital conversion module.
Fig. 4 provides the forming circuit figure of the one-level variable gain amplifying stage of the variable gain amplifier of numeral in the automatic gain amplifying circuit of the present invention.As shown in the figure, one-level digital variable gain amplifying stage comprises the first tail current source I1 and the second tail current source I2, differential signal input pipe M1 and M2, the load resistance RL of two paths of differential signals and source class negative feedback resistor Rd.RL wherein, Rd is an adjustable resistance, is used for regulating the gain size, control signal from the sheet with the decoding circuit in the digital control circuit of anti-indicial response type digital control circuit or next stage digital baseband processing module.The output signal VN of the gain-changeable amplifier circuit of numeral and the peak detector that VP offers in the digital control circuit detect.
Fig. 5 provides 2bit quickflashing analog-digital converter circuit of the present invention and constitutes schematic block diagram, and as shown in the figure, 2bit quickflashing analog-digital converter circuit comprises comparison circuit 51,52 and 53, divider resistance R1, R2 and the R3 of coding circuit 54 and comparative voltage bleeder circuit 55.Wherein comparator 51,52 and an input of 53 be from the output of the variable gain amplifier afterbody of numeral, the voltage division signal that another input produces from resistance string in the comparative voltage bleeder circuit 55 respectively.Coding circuit 54 is the digital encoder of being made up of not gate 501 and NAND gate 502; The input of not gate 502 is from the output of first comparator 51; Its output connects an input of NAND gate 502; Another input of NAND gate 502 is from the input of second comparator 52; The output of 502 NAND gates is exactly the range signal position, and the output of coding circuit 54 is exactly the range signal position of 2bit quickflashing analog to digital converter output, and comparator 53 outputs are exactly the mark signal position of 2bit quickflashing analog to digital converter output; The mark signal position and the range signal position of the output of 2bit quickflashing analog to digital converter offer the digital baseband process chip, and while range signal position also offers the peak detector of anti-exponential type digital control circuit and handles.
Second embodiment
Fig. 6 provides the formation block diagram of the anti-indicial response type digital control circuit in the second embodiment of the invention, and the 4th embodiment combines Fig. 6 to specify the control principle of anti-indicial response type digital control circuit.Anti-indicial response type digital control circuit comprises digital integrator circuit 61, decoding circuit 62, and peak detector 63 and subtraction circuit 64, wherein digital integrator circuit 61 is made up of two dichotomy algorithm circuit 65 and 66.The range signal position that is obtained by 2bit quickflashing analog to digital converter quantification intermediate-freuqncy signal is input to peak detector 63; Peak detector 63 obtains the range signal of intermediate-freuqncy signal through the number of continuous high level number maximum in the processing amplitude position; The range signal of the intermediate-freuqncy signal that obtains is a digital signal; The reference value of this digital signal and internal system register is delivered to subtracter 64 to be handled; Subtracter 64 at first will characterize the digital signal and the reference value of range signal and subtract each other; Subtract each other output and obtain a digital signal through the judgement of making comparisons of a digital comparator: when the output of peak detector 63 during greater than reference value Vref, subtracter 64 is output as high level, on the contrary the low level of being output as.The output of subtracter 64 is handled through dichotomy algorithm circuit 65, and processing procedure is following: if subtracter 64 is output as low level, dichotomy algorithm circuit 65 is increased to maximum control output with current control signal; If feed back afterwards; The output signal of subtracter 64 is a low level, just keeps current control signal output, if subtracter 64 is output as high level; Then the half the of maximum output is transferred in output, and the like up to finding optimum control level.If subtracter 64 is output as high level; Dichotomy algorithm circuit 65 reduces to minimum control output with present control signal, if feed back afterwards, the output signal of subtracter 64 is a high level; Keep current control signal output; If subtracter 64 is output as low level, then a times of minimum output is transferred in output, and the like up to finding optimum control level; The output of digital integrator circuit 61 offers decoding circuit 62 decodings, and decoding circuit 62 obtains the control signal output of numeral.
The 3rd embodiment
Fig. 7 has the automatic gain control amplifier of anti-indicial response type digital control circuit and the block diagram that is connected of back stages of digital baseband chip for the radio frequency chip of the embodiment of the invention.The 71st, have anti-indicial response type digital control circuit automatic gain control amplifier, the 72nd, the chip of configuration baseband processing module.The automatic gain amplifier 71 of radio frequency chip comprises variable gain amplifier 701,2bit quickflashing analog to digital converter 702 and the anti-indicial response type digital control circuit 703 of numeral.Wherein, Baseband processing module 72 has numeral output measuring ability; It can be controlled automatic gain control amplifier 71 through receiver and be disposed at the external control pattern; To amplify the signal of path through analog-to-digital conversion circuit 702 and sampled by digital baseband block 72, the feedback digital signal of digital baseband block 72 is also delivered to the variable gain amplifier 701 of numeral through digital interface circuit 73, with the stable output of outside control model differential signal amplitude.
The 4th embodiment
It is a kind of based on the automatic gain amplifying circuit with switchable many control models of the automatic gain amplifying circuit 81 of anti-exponential type digital control circuit that Fig. 8 gives the embodiment of the invention.It by in the sheet with the automatic gain amplifying circuit 81 of anti-exponential type digital control circuit and the outer control circuit 83 of sheet, and control model diverter switch 804 constitutes.Control model diverter switch 804 by the outer digital baseband processing module 82 control two-way control models of sheet realizes that the control circuit of the control model of two-way control model switches.Realize the switching of anti-indicial response type digital control circuit and external control circuit, break off anti-indicial response type digital control circuit, connect the RF front-end circuit that external control circuit is particularly useful for the few and compact conformation of the outer components and parts of requirement sheet.A kind of automatic gain control amplifier circuit that has anti-indicial response type digital control circuit that Fig. 8 has provided application implementation of the present invention example another kind of baseband chip of arranging in pairs or groups constitutes block diagram.The analog intermediate frequency input signal at first obtains exporting vout through variable gain amplifier 801 amplifications of numeral; Output is sampled through the analog to digital converter of 2bit and is quantized; Obtain amplitude and sign bit information after the quantification; 811 peak detectors in the anti-indicial response type digital control circuit 803 carry out peak value to the amplitude information in the analog to digital converter and detect, and obtain the largest peaks signal, and peak signal that obtains and reference value are compared; Obtain the output signal of comparison through subtraction circuit 814; Through digital integrator circuit 813 integrations, the change direction that obtains gain controlling is carried out the dichotomy algorithm process again, controlled signal after the dichotomy algorithm process again in the relatively output of subtraction circuit 814; The digital controlled signal that control signal is transferred to the variable gain amplifier 801 of control figure through decoding circuit 812; The variable gain amplifier 801 of digital controlled signal FEEDBACK CONTROL numeral reaches the stationary value of setting up to the output of the variable gain amplifier 801 of numeral, and the amplitude after output Vout quantizes through 2bit quickflashing analog to digital converter offers 82 processing of digital baseband process chip with mark signal; Only behind stable output signal, the data that digital baseband process chip 82 obtains just can have maximum signal to noise ratio.
It will be understood by those skilled in the art that and under the prerequisite that does not deviate from broad scope of the present invention, the foregoing description is made some changes.Thereby the present invention is not limited in disclosed specific embodiment.Its scope should contain core of the present invention and the interior all changes of protection range that appended claims limits.
Claims (9)
1. automatic gain amplifying circuit with anti-indicial response type digital control circuit; It is characterized in that: it is the two-way differential configuration that said automatic gain amplifying circuit with anti-indicial response type digital control circuit is called for short the automatic gain amplifying circuit, and the composition of automatic gain amplifying circuit comprises:
The variable gain amplifier (PGA) of numeral,
The quickflashing analog to digital converter, and
Anti-indicial response type control circuit; Wherein
The variable gain amplifier of said numeral is the variable-gain amplification circuit of a multi-stage cascade;
Said quickflashing analog to digital converter is a 2bit quickflashing analog to digital converter; The analog signal that the two-way radio-frequency differential gain of the variable gain amplifier of numeral output is amplified converts digital signal respectively into, delivers to the input of the anti-indicial response type of two-way digital control circuit module;
Said anti-indicial response type control circuit is anti-indicial response type digital control circuit, and the range signal that is used for that 2bit quickflashing analog to digital converter is quantized is handled the back and produced the 2bit control signal to the variable gain amplifier of numeral.
2. automatic gain amplifying circuit according to claim 1; It is characterized in that: the automatic gain amplifying circuit is a programmable-gain module in the radio-frequency front-end; This module is a two-way difference automatic gain amplification circuit structure; The input of every road automatic gain amplifying circuit inserts the radio-frequency front-end intermediate-freuqncy signal; The output of two-way automatic gain amplifying circuit connects next stage digital baseband process chip respectively, and the external interface of programmable-gain module comprises reference value port and gain digital control port of the reference voltage that two-way signal input end of intermediate frequency and two-way are shared;
The reference value of said reference voltage is a digital values of built-in chip type, and one of the inside that the reference value port of reference voltage connects radio-frequency transmitter is register fixedly, is used to provide final stable reference foundation;
Said gain digital control port connects the output control terminal mouth of anti-indicial response type digital control circuit or the output control terminal mouth of next stage digital baseband process chip.
3. moving gain amplifying circuit according to claim 1 is characterized in that: the variable-gain amplification circuit of said multi-stage cascade comprises M the digital variable gain amplifying stage that is connected in series, and the M span is 7～3; The input of the 1st stages of digital variable gain amplifying stage of M digital variable gain amplifying stage connects one road radio-frequency differential input signal and connects, and the output of M stages of digital variable gain amplifying stage connects the right input of 2bit quickflashing analog to digital converter; 2bit quickflashing analog to digital converter with the two-way differential gain amplifying signal of programmable-gain module output receive anti-indicial response type digital control circuit module two inputs, feed back to the digital control port of digital variable gain amplification grade circuit after the processing.
4. automatic gain amplifying circuit according to claim 1 is characterized in that: said anti-indicial response type digital control circuit is by peak detector, subtraction circuit, and digital integrator circuit and decoding circuit are formed; Anti-indicial response type digital control circuit is anti-indicial response circuit, wherein
Two input signal ends of said subtraction circuit connect the output and the reference value end of peak detector, and the output of subtraction circuit connects digital integrator circuit input;
Said digital integrator circuit and decoding circuit are connected in series, and the digital integrator circuit adopts two fens algorithm digital integrations, and the digital integrator circuit output end connects decoding circuit;
Said decoding circuit input connects digital integrator circuit output; The decoding circuit output connects the gain control end of M the digital variable gain amplifying stage that is connected in series of digital variable-gain amplification circuit; Decoding circuit obtains optimum control output with the digital integrator circuit the soonest with two fens algorithms and does the decoding processing, the output control signal.
5. automatic gain amplifying circuit according to claim 1; It is characterized in that: said 2bit quickflashing analog to digital converter comprises three comparator circuits, coding circuit and fixed reference potential configuration circuit, and three comparators adopt the high-speed comparator of same structure; Input signal inserts the reference voltage of three comparators and three comparators simultaneously and makes comparisons; The input of the reference voltage of two comparators all comes from the fixed reference potential configuration circuit; By the divider resistance string supply voltage dividing potential drop is produced, the output of two comparators is through forming the range signal position of 2bit after the digital coding combination of circuits; The reference voltage of another comparator is ground, and the comparative result of comparator output is the mark signal position of 2bit.
6. automatic gain amplifying circuit according to claim 4 is characterized in that: the subtraction circuit of said anti-indicial response type digital control circuit comprises a subtracter and comparator that is connected in series; A comparator is that the parallelly connected comparator of output is right; The reference value of the variable gain amplifier of numeral being exported the Signals & Systems inner setting compares; The output signal offers the integrator integration; The change direction of controlled signal thus, the yield value of the variable-gain amplification circuit in the digital control voltage control digital amplifier that provides by decoding circuit, the variable gain amplifier output voltage amplitude that guarantees numeral is within the scope of setting.
7. automatic gain amplifying circuit according to claim 3; It is characterized in that: said digital variable gain amplifying stage is the Precise Discrete gain amplifier; It is based on the amplifier of discrete gain dB stepping of the precise gain control of resistance-feedback network; Comprise the wake flow source, difference amplifier tube, the variable negative feedback resistor of variable load resistance and source class; Be used for the precise figures control voltage that the anti-Kui rotation road according to digital control pattern provides, the gain of control automatic gain amplifying circuit is for back one-level digital baseband processing module chip provides the radio-frequency front-end signal of high-gain with the big range of linearity.
8. automatic gain amplifying circuit according to claim 3; It is characterized in that: said M the digital variable gain amplifying stage that is connected in series is the digital gain amplifying circuit of the adjustable band common-mode feedback of resistance; The circuit of every stages of digital variable gain amplifying stage is basic identical; The resistance of corresponding adjustment gain is different with the resistance of feedback circuit, and the digital control termination digital control circuit of circuit is used for the accurately digital amplifier's gain of adjustment.
9. according to the described automatic gain amplifying circuit of claim 1-8; Its characteristic also is: said automatic gain amplifying circuit with anti-indicial response type digital control circuit also comprises a control model diverter switch; Carry anti-indicial response type digital control circuit in the automatic gain amplifying circuit sheet and can constitute a kind of automatic gain amplifying circuit of switchable many control models with the outer one or more control circuits of sheet; By digital baseband processing module chip controls control automatic gain amplifying circuit sheet internal schema diverter switch the two-way control model is switched; Realize the switching of anti-indicial response type digital control circuit and external control circuit, break off anti-indicial response type digital control circuit, connect external control circuit; Vice versa, is used to realize the switching of various control pattern.
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