CN111263090B - Reading circuit structure and working time sequence control method thereof - Google Patents

Reading circuit structure and working time sequence control method thereof Download PDF

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Publication number
CN111263090B
CN111263090B CN202010136968.2A CN202010136968A CN111263090B CN 111263090 B CN111263090 B CN 111263090B CN 202010136968 A CN202010136968 A CN 202010136968A CN 111263090 B CN111263090 B CN 111263090B
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mos transistor
switch
voltage
signal
operational amplifier
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CN111263090A (en
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何学红
严慧婕
杨海玲
金毓奇
连夏梦
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Shanghai IC R&D Center Co Ltd
Chengdu Image Design Technology Co Ltd
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Shanghai IC R&D Center Co Ltd
Chengdu Image Design Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

The invention provides a reading circuit structure and a working time sequence control method thereof, wherein the reading circuit structure comprises: a programmable gain amplifier circuit and an analog-to-digital converter circuit that are coupled, the programmable gain amplifier circuit includes a sampling capacitor, a feedback capacitor, an operational amplifier and a reset control switch, the analog-to-digital converter circuit includes a comparator and a counter, and also includes: a signal adjusting capacitor, a first switch, a second switch and a latch; the output end of the comparator is connected with the input end of the counter and the input end of the latch, the first output end of the latch is connected with the counter, the second output end of the latch is connected with the control end of the first switch, and the third output end of the latch is connected with the control end of the second switch. According to the technical scheme, the reading circuit structure can realize signal processing with a high dynamic range under the condition of adding fewer devices, and further the overall performance of the chip is improved.

Description

Reading circuit structure and working time sequence control method thereof
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a readout circuit structure and a method for controlling a working timing thereof.
Background
In an image sensor, a photosensitive unit (pixel) generally converts an optical signal into a voltage signal, and then a PGA (Programmable Gain Amplifier) amplifies the voltage signal, and then an ADC (Analog Digital Converter) circuit converts an Analog voltage signal into a Digital signal, and finally transmits the converted Digital signal to the outside of a chip. Since the light-sensing units are usually in an array form, in order to increase the frame rate, each column of light-sensing units is usually connected with a column of readout circuit composed of PGA and ADC. In order to reduce noise, a Correlated Double Sampling (CDS) technique is usually adopted in the readout circuit, which is expressed by performing two analog-to-digital conversions by the ADC, and finally converting the obtained digital signal into a difference value between two conversion results of the ADC.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional readout circuit structure suitable for an image sensor, and as can be seen from fig. 1, the readout circuit structure is formed by cascading a PGA and an ADC. The PGA is a switched capacitor structure, and the amplification factor is adjustable by adjusting the proportion of the sampling capacitor Cs to the feedback capacitor Cf; the ADC is a single integration structure and is composed of a comparator COMP and a COUNTER.
Referring to fig. 1 and 2, fig. 2 is a timing diagram illustrating the operation of the readout circuit structure of fig. 1, wherein the time from t0 to t5 is a complete timing cycle, which is usually referred to as a row cycle Trow in the image sensor, and the dashed waveform is the waveform of the output voltage V _ PGA of the PGA output node. At time t0, the timing cycle starts, the reset signal PGA _ RST of the PGA changes to high level, the reset switch PGA _ RST in the PGA in fig. 1 is controlled to be turned on, and the PGA is in a reset state; when the time t1 comes, the reset state is finished, the reset signal PGA _ RST of the PGA changes from high level to low level, the input signal VIN keeps the initial voltage VIN1 unchanged, the PGA enters the 1 st establishment state, and the establishment is finished when the time t2 comes; the time point t2 to t3 is the 1 st analog-to-digital conversion time of the ADC, at this time, the output voltage V _ PGA of the output node of the PGA still remains close to the common-mode voltage VCM, the reference voltage VRAMP of the ADC starts to rise with time according to a specific slope until the reference voltage VRAMP of the ADC exceeds the output voltage V _ PGA of the output node of the PGA, that is, VRAMP > VCM, the comparator COMP in the ADC is inverted, and the ADC completes the 1 st analog-to-digital conversion; at time t3, the signal of the reference voltage VRAMP is reset to the initial voltage VINI, and from time t3, the input signal VIN starts to change from VIN1 voltage to VIN2 voltage, and from time t3 to time t4, the PGA output establishment process is performed, and if the input signal VIN finally changes to VIN2 voltage, the output voltage V _ PGA of the output node of the PGA changes from the common-mode voltage VCM to the voltage VCM + (VIN1-VIN2) × Cs/Cf; the time point from t4 to t5 is the 2 nd conversion time of the ADC, the reference voltage VRAMP of the ADC rises along with the time according to the characteristic slope until the reference voltage VRAMP exceeds the output voltage V _ PGA of the output node of the PGA, namely VRAMP > VCM + (Vin1-Vin2) Cs/Cf, the comparator COMP is inverted, and the ADC completes the 2 nd analog-to-digital conversion; finally, the results of the two analog-to-digital conversions are subtracted by the logic in the COUNTER after the comparator COMP, and an effective digital signal is output.
Since the range of voltage signals that can be handled by the operational amplifier OTA and comparator COMP circuits used in the PGA and ADC is limited by the circuit configuration and the supply voltage, the maximum value of the output voltage V _ PGA of the output node of the PGA does not normally exceed the supply voltage minus the overdrive voltage (Vdsat) of one transistor. In order to effectively utilize the output voltage range of the PGA, it is generally designed that the output voltage of the PGA corresponding to the maximum value of the input valid signal approaches the saturation voltage when the PGA gain is 1, so that when the PGA gain is greater than 1, for example, 2 times, the PGA output saturation voltage limits, and therefore only half of the input signal can be effectively processed, which greatly limits the dynamic range of the signal that can be processed by the readout circuit.
In the design of an image sensor chip, the dynamic range is a very important index. Due to the above limitations, the conventional PGA + ADC readout circuit structure cannot increase the dynamic range of the readout circuit when the PGA gain is set to a large multiple, and thus cannot increase the dynamic range of the image sensor chip.
Therefore, a new readout circuit structure is needed to be provided, so that signal processing with a high dynamic range is realized with fewer devices added, and the overall performance of the chip is further improved.
Disclosure of Invention
The invention aims to provide a reading circuit structure and a working sequence control method thereof, so that the reading circuit structure can realize signal processing with a high dynamic range under the condition of adding fewer devices, and further the overall performance of a chip is improved.
To achieve the above object, the present invention provides a readout circuit structure, comprising: a programmable gain amplifier circuit and an analog-to-digital converter circuit that are coupled, the programmable gain amplifier circuit includes a sampling capacitor, a feedback capacitor, an operational amplifier and a reset control switch, the analog-to-digital converter circuit includes a comparator and a counter, the readout circuit structure further includes: a signal adjusting capacitor, a first switch, a second switch and a latch; wherein, one end of the sampling capacitor is used as the signal input end of the programmable gain amplifier circuit, one input end of the operational amplifier is connected with the other end of the sampling capacitor, one end of the feedback capacitor, one end of the reset control switch, one end of the signal adjusting capacitor and one end of the second switch, the other input end of the operational amplifier is connected with a common mode voltage, the output end of the operational amplifier is connected with the other end of the feedback capacitor, the other end of the reset control switch and one input end of the comparator, the other end of the signal adjusting capacitor is connected with the other end of the second switch and one end of the first switch, the other end of the first switch is connected with a reference voltage, the other input end of the comparator is connected with another reference voltage, the output end of the comparator is connected with the input end of the counter and the input end of the latch, the first output end of the latch is connected with the counter, the second output end of the latch is connected with the control end of the first switch, and the third output end of the latch is connected with the control end of the second switch.
Optionally, the other end of the sampling capacitor, one end of the feedback capacitor, one end of the reset control switch, one end of the signal conditioning capacitor, and one end of the second switch are connected to the inverting input terminal of the operational amplifier, the common-mode voltage is connected to the inverting input terminal of the operational amplifier, the inverting input terminal of the comparator is connected to the inverting input terminal of the comparator, and the inverting input terminal of the comparator is connected to the other reference voltage.
Optionally, the control signal of the second switch is an inverted signal of the control signal of the first switch.
Optionally, the sampling capacitor, the feedback capacitor and the signal adjusting capacitor are MOS capacitors.
Optionally, the reset control switch, the first switch and the second switch are MOS switches.
Optionally, the operational amplifier includes first to fifth MOS transistors; the source electrode of the first MOS transistor is connected with a first power supply, the drain electrode of the first MOS transistor is connected with the source electrode of the second MOS transistor and the source electrode of the fifth MOS transistor, and the grid electrode of the first MOS transistor is connected with a direct-current bias voltage; the drain electrode of the second MOS transistor is connected with the drain electrode of the third MOS transistor and forms the output end of the operational amplifier, and the grid electrode of the second MOS transistor is connected with one input end of the operational amplifier; the source electrode of the third MOS transistor is connected with the source electrode of the fourth MOS transistor and is connected with a second power supply, and the grid electrode of the third MOS transistor is connected with the grid electrode of the fourth MOS transistor and the drain electrode of the fifth MOS transistor; the drain electrode of the fourth MOS transistor is connected with the drain electrode of the fifth MOS transistor; the grid electrode of the fifth MOS transistor is connected with the other input end of the operational amplifier;
or the drain electrode of the first MOS transistor is connected with a first power supply, the source electrode of the first MOS transistor is connected with the drain electrode of the second MOS transistor and the drain electrode of the fifth MOS transistor, and the grid electrode of the first MOS transistor is connected with a direct-current bias voltage; the source electrode of the second MOS transistor is connected with the source electrode of the third MOS transistor and forms the output end of the operational amplifier, and the grid electrode of the second MOS transistor is connected with one input end of the operational amplifier; the drain electrode of the third MOS transistor is connected with the drain electrode of the fourth MOS transistor and is connected with a second power supply, and the grid electrode of the third MOS transistor is connected with the grid electrode of the fourth MOS transistor and the source electrode of the fifth MOS transistor; the source electrode of the fourth MOS transistor is connected with the source electrode of the fifth MOS transistor; and the grid electrode of the fifth MOS transistor is connected with the other input end of the operational amplifier.
Optionally, the comparator includes sixth to tenth MOS transistors; the source electrode of the sixth MOS transistor is connected with a first power supply, the drain electrode of the sixth MOS transistor is connected with the source electrode of the seventh MOS transistor and the source electrode of the tenth MOS transistor, and the grid electrode of the sixth MOS transistor is connected with a direct-current bias voltage; the drain electrode of the seventh MOS transistor is connected with the drain electrode of the eighth MOS transistor and forms the output end of the comparator, and the grid electrode of the seventh MOS transistor is connected with one input end of the comparator; the source electrode of the eighth MOS transistor is connected with the source electrode of the ninth MOS transistor and is connected with a second power supply, and the grid electrode of the eighth MOS transistor is connected with the grid electrode of the ninth MOS transistor and the drain electrode of the tenth MOS transistor; the drain electrode of the ninth MOS transistor is connected with the drain electrode of the tenth MOS transistor; the grid electrode of the tenth MOS transistor is connected with the other input end of the comparator;
or the drain electrode of the sixth MOS transistor is connected with the first power supply, the source electrode of the sixth MOS transistor is connected with the drain electrode of the seventh MOS transistor and the drain electrode of the tenth MOS transistor, and the grid electrode of the sixth MOS transistor is connected with a direct-current bias voltage; the source electrode of the seventh MOS transistor is connected with the source electrode of the eighth MOS transistor and forms the output end of the comparator, and the grid electrode of the seventh MOS transistor is connected with one input end of the comparator; the drain electrode of the eighth MOS transistor is connected with the drain electrode of the ninth MOS transistor and is connected with a second power supply, and the gate electrode of the eighth MOS transistor is connected with the gate electrode of the ninth MOS transistor and the source electrode of the tenth MOS transistor; the source electrode of the ninth MOS transistor is connected with the source electrode of the tenth MOS transistor; and the grid electrode of the tenth MOS transistor is connected with the other input end of the comparator.
The invention also provides a working time sequence control method of the reading circuit structure, which comprises the following steps:
firstly, the reset signal is in low level, the output voltage of the operational amplifier starts to be compared with the reference voltage of the analog-digital converter circuit for the first time, and in the first comparison process, the output voltage of the comparator controls the counting of the counter to obtain a first counting result; then, the input voltage of the programmable gain amplifier circuit changes and is reduced to a voltage Vin2 by a voltage Vin1, and the output voltage of the operational amplifier is increased to a voltage VCM + (Vin1-Vin2) (Cs/Cf) by a common-mode voltage VCM, wherein Cf is a feedback capacitor and Cs is a sampling capacitor;
then, the output voltage of the operational amplifier is pre-compared with the reference voltage of the analog-digital converter circuit, and in the pre-comparison process, the output signal of the latch controls the counting of the counter to obtain a second counting result;
then, the output voltage of the operational amplifier is compared with the reference voltage of the analog-digital converter circuit for the second time, and the counter counts for the third time;
and then, according to the results of the first counting, the second counting and the third counting, obtaining an effective analog-to-digital conversion result after logic calculation in the counter.
Optionally, when the gain of the programmable gain amplifier circuit is 2 times, in the pre-comparison process, the reference voltage of the adc circuit is increased from the initial voltage to a voltage VCM + VFS, where VFS is the full-scale input voltage of the adc circuit; when the output voltage VCM + (Vin1-Vin2) (Cs/Cf) of the operational amplifier is less than the reference voltage VCM + VFS of the analog-to-digital converter circuit, the comparator is inverted to control the latch to output the signal to the first switch to be always at the low level, the signal to the second switch to be always at the high level and the signal to the counter to be at the low level, the signal adjusting capacitor is always in short circuit until the reference voltage of the analog-to-digital converter circuit jumps back to the initial voltage by the voltage VCM + VFS to prepare for the second comparison; determining an effective analog-to-digital conversion result according to the results of the first counting and the third counting;
or, when the output voltage VCM + (Vin1-Vin2) (Cs/Cf) of the operational amplifier is greater than the reference voltage VCM + VFS of the analog-to-digital converter circuit and less than VCM +2 VFS, the comparator does not flip, to control the latch to change the signal output to the first switch from low to high, the signal output to the second switch from high to low, and the signal output to the counter to high until the reference voltage of the analog-to-digital converter circuit jumps back to the initial voltage again from the voltage VCM + VFS, and the output voltage of the operational amplifier is dropped from VCM + (Vin 1-2) (Cs/Cf) to + (Vin1-Vin2) (+ Cs/Cf-VFS) to prepare for the second comparison; and determining an effective analog-to-digital conversion result according to the results of the first counting, the second counting and the third counting.
Optionally, when the gain of the programmable gain amplifier circuit is N times and N is an integer not less than 2, the pre-comparison timing repeats N-1 times, the dynamic range of the signal processed by the readout circuit structure is increased by N times, and the number of bits of the digital signal output by the analog-to-digital converter circuit is increased by log2(N) position.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the reading circuit structure of the invention comprises a programmable gain amplifier circuit and an analog-digital converter circuit which are coupled, wherein the programmable gain amplifier circuit comprises a sampling capacitor, a feedback capacitor, an operational amplifier and a reset control switch, the analog-digital converter circuit comprises a comparator and a counter, and the reading circuit structure also comprises: a signal adjusting capacitor, a first switch, a second switch and a latch; wherein, one end of the sampling capacitor is used as the signal input end of the programmable gain amplifier circuit, one input end of the operational amplifier is connected with the other end of the sampling capacitor, one end of the feedback capacitor, one end of the reset control switch, one end of the signal adjusting capacitor and one end of the second switch, the other input end of the operational amplifier is connected with a common mode voltage, the output end of the operational amplifier is connected with the other end of the feedback capacitor, the other end of the reset control switch and one input end of the comparator, the other end of the signal adjusting capacitor is connected with the other end of the second switch and one end of the first switch, the other end of the first switch is connected with a reference voltage, the other input end of the comparator is connected with another reference voltage, the output end of the comparator is connected with the input end of the counter and the input end of the latch, the first output end of the latch is connected with the counter, the second output end of the latch is connected with the control end of the first switch, the third output end of the latch is connected with the control end of the second switch, and the reading circuit is simple in structure, few in added devices, small in occupied area and low in power consumption.
2. The working sequence control method of the reading circuit structure provided by the invention is acted on the reading circuit structure provided by the invention, the output voltage of the operational amplifier is compared with the reference voltage of the analog-digital converter circuit for the first time, pre-compared and compared for the second time, a counter is adopted for counting for the first time, counting for the second time and counting for the third time, and an effective analog-digital conversion result is obtained after logic calculation in the counter according to the results of the counting for the first time, the counting for the second time and the counting for the third time, so that the reading circuit structure can realize signal processing in a high dynamic range under the condition of adding fewer devices, and further the overall performance of a chip is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art readout circuit configuration suitable for use in an image sensor;
FIG. 2 is a timing diagram illustrating the operation of the readout circuit structure of FIG. 1;
FIG. 3 is a diagram of a sensing circuit configuration according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the operation timing (input signal is small) of the sensing circuit configuration shown in FIG. 3;
FIG. 5 is a timing diagram of the operation of the sensing circuit configuration shown in FIG. 3 (input signal is large);
fig. 6 is a schematic diagram of a specific implementation circuit of the sensing circuit structure shown in fig. 3.
Detailed Description
In order to make the objects, advantages and features of the present invention clearer, the following describes the structure of the readout circuit and the method for controlling the operation timing thereof in detail with reference to fig. 3 to 6. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a readout circuit structure, and referring to fig. 3, fig. 3 is a schematic diagram of a readout circuit structure according to an embodiment of the present invention, and as can be seen from fig. 3, the readout circuit structure includes: a programmable gain amplifier circuit PGA and an analog-to-digital converter circuit ADC, which are coupled to each other, wherein the programmable gain amplifier circuit PGA includes a sampling capacitor Cs, a feedback capacitor Cf, an operational amplifier OTA, and a reset control switch PGA _ RST, the analog-to-digital converter circuit ADC includes a comparator COMP and a COUNTER, and the readout circuit structure further includes: a signal conditioning capacitor C1, a first switch S1, a second switch S1N and a LATCH; wherein, one end of the sampling capacitor Cs is used as a signal input end VIN of the programmable gain amplifier circuit PGA, one input end of the operational amplifier OTA is connected to the other end of the sampling capacitor Cs, one end of the feedback capacitor Cf, one end of the reset control switch PGA _ RST, one end of the signal adjusting capacitor C1, and one end of the second switch S1N, the other input end of the operational amplifier OTA is connected to a common mode voltage VCM, the output end of the operational amplifier OTA is connected to the other end of the feedback capacitor Cf, the other end of the reset control switch PGA _ RST, and one input end of the comparator COMP, the other end of the signal adjusting capacitor C1 is connected to the other end of the second switch S1N and one end of the first switch S1, the other end of the first switch S1 is connected to a reference voltage VREF, and the other input end of the comparator COMP is connected to another reference voltage VRAMP, an output end of the comparator COMP is connected to an input end of the COUNTER and an input end of the LATCH, a first output end of the LATCH is connected to the COUNTER, a second output end of the LATCH is connected to a control end of the first switch S1, and a third output end of the LATCH is connected to a control end of the second switch S1N.
The inverting input terminal (-) of the operational amplifier OTA may be connected to the other end of the sampling capacitor Cs, one end of the feedback capacitor Cf, one end of the reset control switch PGA _ RST, one end of the signal conditioning capacitor C1, and one end of the second switch S1N, the common-mode voltage VCM is connected to the forward input terminal (+) of the operational amplifier OTA, the forward input terminal (+) of the comparator COMP is connected to the output terminal of the operational amplifier OTA, and the other reference voltage VRAMP is connected to the inverting input terminal (-) of the comparator COMP. Alternatively, the positions of the positive input terminal (+) and the negative input terminal (-) of the comparator COMP can be interchanged.
The control signal of the second switch S1N is the inverse signal of the control signal of the first switch S1; the other end of the sampling capacitor Cs is connected with an inverting input end (-) of the operational amplifier OTA through a node VN; the other end of the feedback capacitor Cf is connected with a positive input end (+) -of the comparator COMP through a node V _ PGA; the inverting input terminal (-) of the operational amplifier OTA is connected with one end of the reset control switch PGA _ RST through the node VN, and the output terminal of the operational amplifier OTA is connected with the positive input terminal (+) -of the comparator COMP through the node V _ PGA; an output terminal of the comparator COMP is connected to an input terminal of the COUNTER and an input terminal of the LATCH through a node VCOMP; the reset control switch PGA _ RST is connected between the node VN and the node V _ PGA in a bridge mode; the output MSB of the LATCH is connected to the COUNTER for combining out the final digital signal output; the subsequent stage of the COUNTER is the output terminal of the sensing circuit configuration of the present invention.
Compared with the structure of the conventional readout circuit shown in fig. 1, the readout circuit structure of this embodiment adds only one capacitor (i.e., the signal conditioning capacitor C1) and two switches (i.e., the first switch S1 and the second switch S1N) in the analog circuit part, and thus, the number of added devices is small, so that the added area is small; in addition, the circuit configuration of the present embodiment adds some logic circuits that need to be added inside the LATCH and the COUNTER, but since these circuits are usually part of digital circuits, devices with smaller feature sizes are used, so that the total added area and power consumption are smaller. Therefore, the reading circuit of the embodiment has a simple structure and does not occupy too much area and power consumption.
In addition, the sampling capacitor Cs, the feedback capacitor Cf and the signal adjusting capacitor C1 may be MOS capacitors; the reset control switch PGA _ RST, the first switch S1, and the second switch S1N may be MOS switches. The operational amplifier OTA and the comparator COMP can both be a 5-transistor operational amplifier, that is, the operational amplifier OTA can include first to fifth MOS transistors, and the comparator COMP can include sixth to tenth MOS transistors.
Referring to fig. 6, fig. 6 is a schematic diagram of an implementation circuit of the readout circuit structure shown in fig. 3, which shows the detailed structures of the operational amplifier OTA and the comparator COMP (indicated by arrows in fig. 6 for comparison) in the dashed boxes in the readout circuit structure identical to that shown in fig. 3. As can be seen in fig. 6, the operational amplifier OTA includes first to fifth MOS transistors; wherein, the source (with arrow side, the same below) of the first MOS transistor M0 is connected to the first power supply, the drain of the first MOS transistor M0 is connected to the source of the second MOS transistor M1 and the source of the fifth MOS transistor M4, and the gate of the first MOS transistor M0 is connected to a dc bias voltage VBN; the drain of the second MOS transistor M1 is connected to the drain of the third MOS transistor M2 and forms the output terminal VOUT of the operational amplifier OTA, and the gate of the second MOS transistor M1 is connected to an input terminal of the operational amplifier OTA, which may be an inverting input terminal (-) that is connected to the terminal VIN; the source of the third MOS transistor M2 is connected to the source of the fourth MOS transistor M3 and to the second power supply, and the gate of the third MOS transistor M2 is connected to the gate of the fourth MOS transistor M3 and the drain of the fifth MOS transistor M4; the drain electrode of the fourth MOS transistor M3 is connected with the drain electrode of the fifth MOS transistor M4; the gate of the fifth MOS transistor M4 is connected to another input terminal of the operational amplifier OTA, which may be a positive input terminal (+) (i.e., connected to the VIP terminal); a node V1 is arranged between the gate of the third MOS transistor M2 and the gate of the fourth MOS transistor M3, a node V2 is arranged between the drain of the fourth MOS transistor M3 and the drain of the fifth MOS transistor M4, and the node V1 is in short circuit with the node V2.
Or the positions of the source and the drain of the first MOS transistor to the fifth MOS transistor can be interchanged without influencing the normal operation of the readout circuit structure. Specifically, the drain of the first MOS transistor M0 is connected to a first power supply, the source of the first MOS transistor M0 is connected to the drain of the second MOS transistor M1 and the drain of the fifth MOS transistor M4, and the gate of the first MOS transistor M0 is connected to a dc bias voltage VBN; the source of the second MOS transistor M1 is connected to the source of the third MOS transistor M2 and forms the output VOUT of the operational amplifier OTA, and the gate of the second MOS transistor M1 is connected to an input of the operational amplifier OTA, which may be an inverting input (-) i.e. connected to the terminal VIN; the drain of the third MOS transistor M2 is connected to the drain of the fourth MOS transistor M3 and to the second power supply, and the gate of the third MOS transistor M2 is connected to the gate of the fourth MOS transistor M3 and the source of the fifth MOS transistor M4; the source of the fourth MOS transistor M3 is connected with the source of the fifth MOS transistor M4; the gate of the fifth MOS transistor M4 is connected to another input terminal of the operational amplifier OTA, which may be a positive input terminal (+) (i.e., connected to the VIP terminal).
Also, as can be seen from fig. 6, the comparator COMP includes sixth to tenth MOS transistors; wherein, the source (with arrow side, the same below) of the sixth MOS transistor M5 is connected to the first power supply, the drain of the sixth MOS transistor M5 is connected to the source of the seventh MOS transistor M6 and the source of the tenth MOS transistor M9, and the gate of the sixth MOS transistor M5 is connected to a dc bias voltage VBN; the drain of the seventh MOS transistor M6 is connected to the drain of the eighth MOS transistor M7 and forms the output terminal VOUT of the comparator COMP, and the gate of the seventh MOS transistor M6 is connected to an input terminal of the comparator COMP, which may be an inverting input terminal (-) i.e. connected to the terminal VIN; the source of the eighth MOS transistor M7 is connected to the source of the ninth MOS transistor M8 and to the second power supply, and the gate of the eighth MOS transistor M7 is connected to the gate of the ninth MOS transistor M8 and the drain of the tenth MOS transistor M9; the drain of the ninth MOS transistor M8 is connected to the drain of the tenth MOS transistor M9; the gate of the tenth MOS transistor M9 is connected to another input terminal of the comparator COMP, which may be a positive input terminal (+) (i.e., connected to the VIP terminal); a node V3 is arranged between the gate of the eighth MOS transistor M7 and the gate of the ninth MOS transistor M8, a node V4 is arranged between the source of the ninth MOS transistor M8 and the source of the tenth MOS transistor M9, and the node V3 is in short circuit with the node V4.
Alternatively, the positions of the source and the drain of the sixth MOS transistor to the tenth MOS transistor can be interchanged without affecting the normal operation of the readout circuit structure. Specifically, the drain of the sixth MOS transistor M5 is connected to the first power supply, the source of the sixth MOS transistor M5 is connected to the drain of the seventh MOS transistor M6 and the drain of the tenth MOS transistor M9, and the gate of the sixth MOS transistor M5 is connected to the dc bias voltage VBN; the source of the seventh MOS transistor M6 is connected to the source of the eighth MOS transistor M7 and forms the output terminal VOUT of the comparator COMP, and the gate of the seventh MOS transistor M6 is connected to an input terminal of the comparator COMP, which may be an inverting input terminal (-) i.e. connected to the terminal VIN; the drain of the eighth MOS transistor M7 is connected to the drain of the ninth MOS transistor M8 and to the second power supply, and the gate of the eighth MOS transistor M7 is connected to the gate of the ninth MOS transistor M8 and to the source of the tenth MOS transistor M9; the source of the ninth MOS transistor M8 is connected to the source of the tenth MOS transistor M9; the gate of the tenth MOS transistor M9 is connected to another input terminal of the comparator COMP, which may be a positive input terminal (+) (i.e., connected to the VIP terminal).
The first power supply may be a power supply cathode VSS, the second power supply may be a power supply anode VDD, and VSS may refer to ground or a voltage lower than VDD. The circuit structures of the operational amplifier OTA and the comparator COMP may not be limited to the above-mentioned 5-transistor operational amplifier structure, but may be other suitable structures.
In summary, the readout circuit structure provided by the present invention includes: a programmable gain amplifier circuit and an analog-to-digital converter circuit that are coupled, the programmable gain amplifier circuit includes a sampling capacitor, a feedback capacitor, an operational amplifier and a reset control switch, the analog-to-digital converter circuit includes a comparator and a counter, the readout circuit structure further includes: a signal adjusting capacitor, a first switch, a second switch and a latch; wherein, one end of the sampling capacitor is used as the signal input end of the programmable gain amplifier circuit, one input end of the operational amplifier is connected with the other end of the sampling capacitor, one end of the feedback capacitor, one end of the reset control switch, one end of the signal adjusting capacitor and one end of the second switch, the other input end of the operational amplifier is connected with a common mode voltage, the output end of the operational amplifier is connected with the other end of the feedback capacitor, the other end of the reset control switch and one input end of the comparator, the other end of the signal adjusting capacitor is connected with the other end of the second switch and one end of the first switch, the other end of the first switch is connected with a reference voltage, the other input end of the comparator is connected with another reference voltage, the output end of the comparator is connected with the input end of the counter and the input end of the latch, the first output end of the latch is connected with the counter, the second output end of the latch is connected with the control end of the first switch, and the third output end of the latch is connected with the control end of the second switch. The reading circuit has simple structure and small occupied area and power consumption.
An embodiment of the present invention provides a method for controlling an operation timing of the readout circuit structure, referring to fig. 4 and 5, where fig. 4 is a schematic diagram of an operation timing (input signal is small) of the readout circuit structure shown in fig. 3, fig. 5 is a schematic diagram of an operation timing (input signal is large) of the readout circuit structure shown in fig. 3, and as can be seen from fig. 4 and 5, Trow represents a timing cycle, and the method for controlling an operation timing of the readout circuit structure includes:
first, at time t1 to time t3, the reset signal PGA _ RST is at a low level, the output voltage V _ PGA of the operational amplifier OTA starts to be compared with the reference voltage VRAMP of the analog-to-digital converter circuit ADC for the first time, and during the first comparison, the output voltage VCOMP of the comparator COMP controls the counting of the COUNTER to obtain the first counting result. Specifically, at time t0, the timing cycle begins, the reset signal PGA _ RST of the PGA changes to high level, the reset switch PGA _ RST in the PGA in fig. 3 is controlled to be turned on, the PGA is in a reset state, the reset state ends at time t1, the reset signal PGA _ RST of the PGA changes from high level to low level, the input signal VIN remains at the initial voltage VIN1, the reference voltage VRAMP of the ADC remains at the initial voltage VINI, the PGA enters a first set-up state, set-up is completed at time t2, and time t2 to t3 is the 1 st analog-to-digital conversion time of the ADC, at which time, the output voltage V _ PGA of the output node of the PGA remains approximately equal to the common mode voltage VCM, the reference voltage VRAMP begins to rise with a specific slope with time until the reference voltage VRAMP exceeds the output voltage V _ PGA, that is, when VRAMP > VCM, the output VCOMP of the comparator COMP flips, the ADC completes the 1 st analog-to-digital conversion, and the t3 ADC finishes the 1 st analog-to-digital conversion time, the reference voltage VRAMP becomes the initial voltage VINI;
then, the time t3 to t4 is the output setup time of the PGA, the input voltage VIN of the programmable gain amplifier circuit PGA changes and is reduced from the voltage VIN1 to the voltage VIN2, and the output voltage V _ PGA of the operational amplifier OTA is increased from the common-mode voltage VCM to a voltage VCM + (VIN1-VIN2) ((Cs/Cf)), where Cf is the feedback capacitance and Cs is the sampling capacitance.
Then, the output voltage V _ PGA of the operational amplifier OTA is pre-compared with the reference voltage VRAMP of the analog-to-digital converter circuit ADC, and during the pre-comparison, the output signal of the LATCH controls the counting of the COUNTER, so as to obtain the second counting result. Specifically, taking the example that the gain of the programmable gain amplifier circuit PGA is 2 times, referring to fig. 4, when the input signal is small, the reference voltage VRAMP of the analog-to-digital converter circuit ADC jumps from the initial voltage VINI to the voltage VCM + VFS in the time period from t4 to t5, where VFS is the full-scale input voltage of the analog-to-digital converter circuit ADC; for the pre-comparison process in the time period from t5 to t6, since the input voltage is smaller at this time, the value VCM + (Vin1-Vin2) × (Cs/Cf) of the output voltage V _ PGA of the operational amplifier OTA is smaller than the value VCM + VFS of the reference voltage VRAMP of the analog-to-digital converter circuit ADC, the comparator COMP flips, the output voltage VCOMP of the comparator COMP flips to control the LATCH to output the signal to the first switch S1 to be low level, the signal to the second switch S1N to be high level, and the signal MSB to the COUNTER to be low level, the signal adjusting capacitor C1 to be short-circuited all the time without affecting the output of the PGA, until after the time t6, the reference voltage VRAMP of the analog-to-digital converter circuit ADC jumps back to the initial voltage by the voltage + VFS again to prepare the second comparison, i.e. to prepare for the next analog-to-digital conversion, the time from t6 to t7 is the output establishment time of the PGA, and the establishment is completed at the time of t 7;
referring to fig. 5, when the input signal is large, the reference voltage VRAMP of the analog-to-digital converter circuit ADC jumps from the initial voltage VINI to the voltage VCM + VFS during a period from t4 to t5, where VFS is the full-scale input voltage of the analog-to-digital converter circuit ADC; during the pre-comparison process, during the time period from t5 to t6, since the input signal is greater, the value VCM + (Vin1-Vin2) ((Cs/Cf) of the output voltage V _ PGA of the operational amplifier OTA is greater than the value VCM + VFS of the reference voltage VRAMP of the analog-to-digital converter circuit ADC and is less than VCM +2 VFS, that is, (Vin1-Vin2) ((Cs/Cf) is greater than VFS and less than 2 VFS, corresponding to the effective voltage value output by PGA exceeding the full range of ADC, at this time, the comparator COMP does not flip to control the LATCH to change the signal output to the first switch S1 from low level to high level, the signal output to the second switch S1N from high level to low level, and the signal MSB output to the COUNTER to high level, the voltage of the right plate of the signal adjusting capacitor C1 from the voltage of the node (ideally equal to the common mode voltage VN) of the reference voltage VCM, according to the charge transfer principle, after the time t6, the output voltage V _ PGA at the output end of the PGA is decreased (VREF-VCM) C1/Cf, and is decreased from VCM + (Vin1-Vin2) Cs/Cf to VCM + (Vin1-Vin2) Cs/Cf- (VREF-VCM) C1/Cf, and the value of the reference voltage VREF is set to VFS Cf/C1+ VCM, so that (VREF-VCM) C1/Cf is VFS, the output voltage V _ PGA drops to VCM + (Vin1-Vin2) Cs/Cf-VFS, this voltage range is within the ADC full scale range and the reference voltage VRAMP of the analog to digital converter circuit ADC is ramped back to the initial voltage VINI by the voltage VCM + VFS to prepare for the second comparison, preparing for next analog-to-digital conversion, wherein the time from t6 to t7 is the output establishment time of the PGA, and the establishment is completed at the time of t 7;
then, at time t7 to t8, the output voltage V _ PGA of the operational amplifier OTA is compared with the reference voltage VRAMP of the analog-to-digital converter circuit ADC for the second time, and the COUNTER counts for the third time; at time t7, the ADC starts the 2 nd analog-to-digital conversion, the reference voltage VRAMP starts to rise with a specific slope with time, when the reference voltage VRAMP exceeds the output voltage V _ PGA of the output node, i.e., VRAMP > VCM + (Vin1-Vin2) × Cs/Cf-VFS, the output VCOMP of the comparator COMP is inverted, the ADC completes the 2 nd analog-to-digital conversion, and the conversion is ended at time t8, during which the control signal of the first switch S1 is kept at a high level.
And then, according to the results of the first counting, the second counting and the third counting, obtaining an effective analog-to-digital conversion result after logic calculation in the counter. Specifically, when the input signal is small, since the comparator COMP is inverted during the pre-comparison, the MSB of the signal output from the LATCH is controlled to be at a low level, so that when the final digital signal is finally synthesized in the COUNTER, the valid value is determined by two conversion values of the ADC, that is, the valid analog-to-digital conversion result is determined by the results of the first counting and the third counting; when the input signal is larger, because the comparator COMP is not inverted during the pre-comparison, the MSB of the signal output from the LATCH is controlled to be at a high level, and the signal is output to the COUNTER, so as to combine with the values obtained by two times of analog-to-digital conversion to form a final digital signal output, that is, an effective analog-to-digital conversion result is determined according to the results of the first counting, the second counting, and the third counting. It can be seen that when the input signal is larger, the number of finally output data bits is increased by one bit due to the addition of one MSB, and the dynamic range is doubled; in addition, the complexity of subsequent chip system processing cannot be greatly increased by adding one bit to the digital signal, and the method can effectively improve the dynamic range of the chip system.
In the above fig. 4 and fig. 5, the working timing when the gain of the programmable gain amplifier circuit PGA is 2 times is shown, and the theoretical maximum value of the effective output voltage of the PGA is 2 × VFS; if the gain of the PGA is set to be larger, for example, 4 times, the theoretical maximum value of the effective voltage output by the PGA is 4 × VFS, the readout circuit structure proposed in the present invention only needs to make some simple logic function modifications inside the newly added LATCH module and COUNTER, and then control the timing to make some corresponding modifications, and the modified operation timing only needs to repeat the timing from t4 to t7 in fig. 4 and 5 for 2 times, which is 3 times in total, so that the total timing period will be slightly increased, but the dynamic range of the signal can be increased to 4 times. Therefore, when the gain of the programmable gain amplifier circuit PGA is N times and N is an integer not less than 2, the timing of the pre-comparison (i.e., the timing from time t4 to time t 7) is repeated N-1 times, the dynamic range of the signal processed by the readout circuit structure can be increased to N times, and the number of bits of the digital signal output by the ADC is increased by log2(N) bit, log2And (N) is decimal, and the smallest integer larger than the numerical value is taken.
It can be known from the working sequence control method of the readout circuit structure that the invention mainly has the effects of realizing high-precision programmable gain amplification of an analog input voltage signal, then performing high-precision analog-to-digital conversion on the amplified signal, and finally converting the signal into a digital signal, and in the process, when the circuit is set to be high-gain and the input voltage signal is large, the readout circuit still normally works but cannot be saturated, and the finally converted digital signal can realize output range expansion, so that high dynamic range signal readout is obtained; moreover, the dynamic range of signals which can be processed by the whole circuit is effectively enlarged, meanwhile, the time for increasing the time sequence period is less, and the processing speed of the whole circuit cannot be greatly reduced; the structure can support the working time sequence of the existing reading circuit structure, can be switched in a chip system very conveniently when in use, and is flexible to use. Therefore, the reading circuit structure can realize high dynamic range signal reading, has a simple structure, does not occupy much area and power consumption, and is suitable for being integrated in a high dynamic range and low power consumption chip system.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A sensing circuit structure, comprising: a programmable gain amplifier circuit and an analog-to-digital converter circuit that are coupled, the programmable gain amplifier circuit including a sampling capacitor, a feedback capacitor, an operational amplifier and a reset control switch, the analog-to-digital converter circuit including a comparator and a counter, the readout circuit structure further including: a signal adjusting capacitor, a first switch, a second switch and a latch; wherein, one end of the sampling capacitor is used as the signal input end of the programmable gain amplifier circuit, one input end of the operational amplifier is connected with the other end of the sampling capacitor, one end of the feedback capacitor, one end of the reset control switch, one end of the signal adjusting capacitor and one end of the second switch, the other input end of the operational amplifier is connected with a common mode voltage, the output end of the operational amplifier is connected with the other end of the feedback capacitor, the other end of the reset control switch and one input end of the comparator, the other end of the signal adjusting capacitor is connected with the other end of the second switch and one end of the first switch, the other end of the first switch is connected with a reference voltage, the other input end of the comparator is connected with another reference voltage, the output end of the comparator is connected with the input end of the counter and the input end of the latch, the first output end of the latch is connected with the counter, the second output end of the latch is connected with the control end of the first switch, and the third output end of the latch is connected with the control end of the second switch.
2. A sensing circuit arrangement according to claim 1, wherein the inverting input of the operational amplifier is connected to the other terminal of the sampling capacitor, one terminal of the feedback capacitor, one terminal of the reset control switch, one terminal of the signal conditioning capacitor, and one terminal of the second switch, the forward input of the operational amplifier is connected to the common mode voltage, the output of the operational amplifier is connected to the forward input of the comparator, and the inverting input of the comparator is connected to the further reference voltage.
3. A sensing circuit arrangement according to claim 1, wherein the control signal of the second switch is an inverted signal of the control signal of the first switch.
4. A sensing circuit structure of claim 1, wherein the sampling capacitor, the feedback capacitor, and the signal conditioning capacitor are MOS capacitors.
5. A sensing circuit structure of claim 1, wherein the reset control switch, the first switch, and the second switch are MOS switches.
6. A sensing circuit structure of claim 1, wherein the operational amplifier includes first to fifth MOS transistors; the source electrode of the first MOS transistor is connected with a first power supply, the drain electrode of the first MOS transistor is connected with the source electrode of the second MOS transistor and the source electrode of the fifth MOS transistor, and the grid electrode of the first MOS transistor is connected with a direct-current bias voltage; the drain electrode of the second MOS transistor is connected with the drain electrode of the third MOS transistor and forms the output end of the operational amplifier, and the grid electrode of the second MOS transistor is connected with one input end of the operational amplifier; the source electrode of the third MOS transistor is connected with the source electrode of the fourth MOS transistor and is connected with a second power supply, and the grid electrode of the third MOS transistor is connected with the grid electrode of the fourth MOS transistor and the drain electrode of the fifth MOS transistor; the drain electrode of the fourth MOS transistor is connected with the drain electrode of the fifth MOS transistor; the grid electrode of the fifth MOS transistor is connected with the other input end of the operational amplifier;
or the drain electrode of the first MOS transistor is connected with a first power supply, the source electrode of the first MOS transistor is connected with the drain electrode of the second MOS transistor and the drain electrode of the fifth MOS transistor, and the grid electrode of the first MOS transistor is connected with a direct-current bias voltage; the source electrode of the second MOS transistor is connected with the source electrode of the third MOS transistor and forms the output end of the operational amplifier, and the grid electrode of the second MOS transistor is connected with one input end of the operational amplifier; the drain electrode of the third MOS transistor is connected with the drain electrode of the fourth MOS transistor and is connected with a second power supply, and the grid electrode of the third MOS transistor is connected with the grid electrode of the fourth MOS transistor and the source electrode of the fifth MOS transistor; the source electrode of the fourth MOS transistor is connected with the source electrode of the fifth MOS transistor; and the grid electrode of the fifth MOS transistor is connected with the other input end of the operational amplifier.
7. A sensing circuit structure of claim 1, wherein the comparator includes sixth to tenth MOS transistors; the source electrode of the sixth MOS transistor is connected with a first power supply, the drain electrode of the sixth MOS transistor is connected with the source electrode of the seventh MOS transistor and the source electrode of the tenth MOS transistor, and the grid electrode of the sixth MOS transistor is connected with a direct-current bias voltage; the drain electrode of the seventh MOS transistor is connected with the drain electrode of the eighth MOS transistor and forms the output end of the comparator, and the grid electrode of the seventh MOS transistor is connected with one input end of the comparator; the source electrode of the eighth MOS transistor is connected with the source electrode of the ninth MOS transistor and is connected with a second power supply, and the grid electrode of the eighth MOS transistor is connected with the grid electrode of the ninth MOS transistor and the drain electrode of the tenth MOS transistor; the drain electrode of the ninth MOS transistor is connected with the drain electrode of the tenth MOS transistor; the grid electrode of the tenth MOS transistor is connected with the other input end of the comparator;
or the drain electrode of the sixth MOS transistor is connected with the first power supply, the source electrode of the sixth MOS transistor is connected with the drain electrode of the seventh MOS transistor and the drain electrode of the tenth MOS transistor, and the grid electrode of the sixth MOS transistor is connected with a direct-current bias voltage; the source electrode of the seventh MOS transistor is connected with the source electrode of the eighth MOS transistor and forms the output end of the comparator, and the grid electrode of the seventh MOS transistor is connected with one input end of the comparator; the drain electrode of the eighth MOS transistor is connected with the drain electrode of the ninth MOS transistor and is connected with a second power supply, and the gate electrode of the eighth MOS transistor is connected with the gate electrode of the ninth MOS transistor and the source electrode of the tenth MOS transistor; the source electrode of the ninth MOS transistor is connected with the source electrode of the tenth MOS transistor; and the grid electrode of the tenth MOS transistor is connected with the other input end of the comparator.
8. A method of controlling an operation timing of a readout circuit configuration according to any one of claims 1 to 7, the method comprising:
firstly, the reset signal is in low level, the output voltage of the operational amplifier starts to be compared with the reference voltage of the analog-digital converter circuit for the first time, and in the first comparison process, the output voltage of the comparator controls the counting of the counter to obtain a first counting result; then, the input voltage of the programmable gain amplifier circuit changes and is reduced to a voltage Vin2 by a voltage Vin1, and the output voltage of the operational amplifier is increased to a voltage VCM + (Vin1-Vin2) (Cs/Cf) by a common-mode voltage VCM, wherein Cf is a feedback capacitor and Cs is a sampling capacitor;
then, the output voltage of the operational amplifier is pre-compared with the reference voltage of the analog-digital converter circuit, and in the pre-comparison process, the output signal of the latch controls the counting of the counter to obtain a second counting result;
then, the output voltage of the operational amplifier is compared with the reference voltage of the analog-digital converter circuit for the second time, and the counter counts for the third time;
then, when the input signal is small, the comparator is turned over, and the signal output to the counter by the latch is controlled to be low level, so that an effective analog-to-digital conversion result is obtained after logic calculation in the counter according to the results of the first counting and the third counting; when the input signal is larger, the comparator is not turned over, and the signal output to the counter by the latch is controlled to be high level, so that an effective analog-to-digital conversion result is obtained after logic calculation in the counter according to the results of the first counting, the second counting and the third counting.
9. The method of claim 8, wherein when the gain of the programmable gain amplifier circuit is 2 times, the reference voltage of the adc circuit is raised from an initial voltage to a voltage VCM + VFS during the pre-comparison, wherein VFS is a full-scale input voltage of the adc circuit; when the output voltage VCM + (Vin1-Vin2) (Cs/Cf) of the operational amplifier is less than the reference voltage VCM + VFS of the analog-to-digital converter circuit, the comparator is inverted to control the latch to output the signal to the first switch to be always at the low level, the signal to the second switch to be always at the high level and the signal to the counter to be at the low level, the signal adjusting capacitor is always in short circuit until the reference voltage of the analog-to-digital converter circuit jumps back to the initial voltage by the voltage VCM + VFS to prepare for the second comparison; determining an effective analog-to-digital conversion result according to the results of the first counting and the third counting;
or, when the output voltage VCM + (Vin1-Vin2) (Cs/Cf) of the operational amplifier is greater than the reference voltage VCM + VFS of the analog-to-digital converter circuit and less than VCM +2 VFS, the comparator does not flip, to control the latch to change the signal output to the first switch from low to high, the signal output to the second switch from high to low, and the signal output to the counter to high until the reference voltage of the analog-to-digital converter circuit jumps back to the initial voltage again from the voltage VCM + VFS, and the output voltage of the operational amplifier is dropped from VCM + (Vin 1-2) (Cs/Cf) to + (Vin1-Vin2) (+ Cs/Cf-VFS) to prepare for the second comparison; and determining an effective analog-to-digital conversion result according to the results of the first counting, the second counting and the third counting.
10. The method for controlling the operation timing of a readout circuit configuration according to claim 8, wherein when the gain of the programmable gain amplifier circuit is N times and N is an integer not less than 2, the timing of the pre-comparison is repeated N-1 times, the dynamic range of the signal processed by the readout circuit configuration is increased N times, and the number of bits of the digital signal output from the analog-to-digital converter circuit is increased by log2(N) position.
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