CN116865754A - Comparator and processing method for high-speed column parallel single-inclined analog-to-digital converter - Google Patents
Comparator and processing method for high-speed column parallel single-inclined analog-to-digital converter Download PDFInfo
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The invention relates to a comparator and a processing method for a high-speed column parallel monoclinic analog-to-digital converter, which are based on CDS technology, can effectively reduce noise characteristics of SSADC, non-ideal characteristics such as comparator delay, slope delay and counter deviation and the like, and improve image quality. The invention integrates two times of quantization of the digital CDS technology on the same slope, reduces the time required by the additionally added slope and the time required by corresponding signal establishment and reset, greatly reduces the quantization time of the SSADC and improves the reading speed. In addition, the capacitive coupling mode provided by the invention can effectively avoid the condition that one end of the capacitor floats after a capacitive coupling signal, reduces the interference of other signals on the capacitor, and ensures that the quantization result is more accurate.
Description
Technical Field
The invention belongs to the technical field of CMOS image sensors, and particularly relates to a comparator for a high-speed column parallel monoclinic analog-to-digital converter and a processing method thereof.
Background
An analog-to-digital converter (Analog to Digital Converter, ADC) is one of the core blocks of a CMOS image sensor. Currently, there are three main ADC architectures used in CMOS image sensors: pixel-level ADC, chip-level ADC, column-parallel ADC. Chip-scale ADCs require extremely high speed ADCs to achieve high frame rates. Pixel level ADCs sacrifice part of layout area and power consumption to increase the frame rate of the ADC. Column parallel ADCs can achieve a good tradeoff between frame rate, fill factor, silicon area, and power consumption.
There are three main column-parallel ADC architectures: monoclinic ADC (SS ADC), successive approximation ADC (SARADC), cyclic ADC (CyclicADC). SARADC has high conversion speed, but more digital-to-analog converters are needed in the column array, which causes waste of layout space and larger power consumption. The a/D conversion speed of the Cyclic ADC is also fast, but the same will generate larger power consumption, and the circuit design is difficult. The SSADC can generate a high-precision and high-linearity ramp signal, has the characteristics of simple circuit structure, small area and low power consumption, and is widely applied to column-level ADC architectures. Particularly, in the readout circuits of large-array CMOS image sensors, extremely high demands are put forward on areas, layout drawing areas, column consistency levels, and the like. Therefore, the circuit structure is simple, and the SSADC with smaller on-chip area is widely applied to the CMOS image sensor.
In the present-day SSADC application process, a correlated double sampling technique (Corretated Double Sampling, CDS) is generally used to reduce noise, i.e. to sample a target signal twice in a correlated manner, and then the results of the two samples are subjected to a difference, so that the noise characteristics and errors of the comparator, such as clock offset, ramp delay, etc., can be effectively reduced. CDS in the digital domain can be implemented by two opposite counts in the readout circuit, but the use of digital CDS requires an additional ramp to quantize the reset signal and a reset signal input comparator to quantize the reset signal and a pixel signal input comparator to quantize the pixel signal, resulting in the readout of the comparator being limited by the pixel exposure time, i.e., the quantization time of SSADC is limited by the row readout time. The existing improvement mode is as follows: a stage CDS stage may be added to the pre-stage circuit, that is, the reset signal and the pixel signal are correlated double sampled in advance and combined into one signal, and the digital CDS eliminates the non-ideal characteristics of the comparator. The read-out of the comparator is therefore no longer limited by the row read-out time, and the improved comparator structure is shown in fig. 2, but in the read-out process described above, more time is required for quantization and additional time for signal set-up, reset due to the addition of the extra ramp. Meanwhile, the CDS circuit samples the pixel module, the comparator samples the CDS module, after signal coupling is caused, capacitors C2 and C3 of the comparator generate a floating state, no signal is connected to the left end of the capacitor, and large interference is caused to the quantization process of the signal.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a comparator and a processing method for a high-speed column parallel single-slope analog-to-digital converter, which can integrate two slopes of a digital CDS technology into one slope, effectively reduce the reading time, avoid the generation of a floating state in an original structure by optimizing a capacitor and a switch structure, reduce the influence of parasitic effects and improve the accuracy of quantification.
The invention solves the technical problems by adopting the following technical scheme:
the comparator comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a four-input comparator A, a switch S1, a switch S2 and a switch Srst, wherein the input signal of the comparator is a single-ended input signal, one end of the capacitor C1 is connected with a ramp signal Vramp1 through the switch S1, the other end of the capacitor C1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is respectively connected with the positive output of the four-input comparator A and the four-input comparator A, a reference voltage Vref is connected with one end of the capacitor C3, the other end of the capacitor C3 is respectively connected with the four-input comparator A and the other end of the capacitor C2 through the switch Srst, one side of the capacitor C4 is connected with the ramp signal Vramp2, the other end of the capacitor C4 is respectively connected with the negative output end of the four-input comparator A through the switch S2, the other end of the capacitor C5 is respectively connected with one end of the capacitor C6, and the other end of the capacitor C6 is respectively connected with the four-input comparator A through the switch Srst 5.
A method of processing a comparator for a high-speed column-parallel monoclinic analog-to-digital converter, comprising the steps of: the ramp signal Vramp1 is coupled into the four-input comparator A through the capacitor C1 and the capacitor C2, the Vramp2 is coupled into the four-input comparator A through the capacitor C4 and the capacitor C5, the ramp signal is reset to a fixed level, then jumps upwards, then starts to fall after the signal is built to be stable, when the ramp falls to the same level as the reset level, the four-input comparator A turns over and controls the counter to start counting, the signal Vin is coupled in through the capacitor C5, the four-input comparator A starts to compare a ramp signal jump variable with a pixel signal jump variable, when the ramp jump variable is coupled to be equal to the pixel signal jump variable, the four-input comparator A turns over again, the counter is controlled to stop counting, and the digital CDS operation is completed.
The comparator comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a four-input comparator A, a switch S1, a switch S2 and a switch Srst, wherein the input signals of the comparator are differential input signals, one end of the capacitor C1 is connected with a ramp signal Vramp1+ through the switch S1, the other end of the capacitor C1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is respectively connected with the positive output of the four-input comparator A and the four-input comparator A, one end of the capacitor C3 is connected with one end of the ramp signal Vramp 1-through the switch S1, the other end of the capacitor C3 is respectively connected with the other end of the four-input comparator A and the capacitor C2, one end of the other end of the capacitor C5 is respectively connected with one end of the ramp signal Vramp2-, the other end of the capacitor C5 is respectively connected with one end of the capacitor C6 through the switch S2, the other end of the capacitor C6 is respectively connected with one end of the capacitor C8 and the other end of the capacitor C8 is connected with one end of the capacitor C8+ through the other end of the ramp signal Vramp2, and the other end of the capacitor C8 is respectively connected with the other end of the capacitor C8 and the other end of the capacitor C8 is connected with the other end of the capacitor C2.
A method of processing a comparator for a high-speed column-parallel monoclinic analog-to-digital converter, comprising the steps of: the ramp signal Vramp1+ and the ramp signal Vramp 1-are respectively coupled into a first differential pair of the four-input comparator A through a capacitor C1 and a capacitor C2, a capacitor C3 and a capacitor C4, the switch S1 is controlled, after the first differential pair finishes quantifying the non-ideal characteristic, the switch S1 is disconnected, the first differential pair is in a non-working state, vramp2+ and Vramp2+ are coupled in through a capacitor C5 and a capacitor C6, a capacitor C7 and a capacitor C8, the input signal is respectively coupled in through a capacitor C6 and a capacitor C8 by a signal Vin-and a signal vin+ and is controlled by the switch S2, and after the signal coupling, the switch S2 is disconnected to lighten the load of a front stage.
The invention has the advantages and positive effects that:
the invention is based on CDS technology, can effectively reduce noise characteristic of SSADC and nonideal characteristics such as comparator delay, slope delay and counter deviation, etc., and improves image quality. The invention integrates two times of quantization of the digital CDS technology on the same slope, reduces the time required by the additionally added slope and the time required by corresponding signal establishment and reset, greatly reduces the quantization time of the SSADC and improves the reading speed. In addition, the capacitive coupling mode provided by the invention can effectively avoid the condition that one end of the capacitor floats after a capacitive coupling signal, reduces the interference of other signals on the capacitor, and ensures that the quantization result is more accurate.
Drawings
Fig. 1 is a block diagram of a conventional SSADC.
Fig. 2 is a block diagram of a comparator with CDS circuit adapted to the previous stage.
Fig. 3 is a diagram of a comparator structure under a single-ended input signal of the present invention.
Fig. 4 is a diagram of a comparator structure under differential input signals of the present invention.
Fig. 5 is a timing diagram of the comparator of the present invention.
Fig. 6 is a ramp waveform diagram for the case of two input signals of the present invention.
Fig. 7 is a circuit diagram of a first stage comparator according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
A comparator for a high speed column-parallel monoclinic analog-to-digital converter includes a comparator under a single ended input signal and a comparator under a differential input signal.
As shown in fig. 3, the comparator under the single-ended input signal includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a four-input comparator a, a switch S1, a switch S2 and a switch Srst, wherein one end of the capacitor C1 is connected with the ramp signal Vramp1 through the switch S1, the other end of the capacitor C1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is respectively connected with the four-input comparator a and the positive output of the four-input comparator a, the reference voltage Vref is connected with one end of the capacitor C3, the other end of the capacitor C3 is respectively connected with the four-input comparator a and the other end of the capacitor C2 through the switch Srst, one side of the capacitor C4 is connected with the ramp signal Vramp2, the other end of the capacitor C4 is respectively connected with one end of the capacitor C5 through the switch S2, the other end of the capacitor C5 is respectively connected with the four-input comparator a and the negative output end of the four-input comparator a, the reference voltage Vref is connected with one end of the capacitor C6, and the other end of the capacitor C6 is respectively connected with the other end of the capacitor C5 through the switch Srst.
The processing method of the comparator under the single-ended input signal comprises the following steps: the ramp signal Vramp1 is coupled into the four-input comparator A through the capacitor C1 and the capacitor C2, the Vramp2 is coupled into the four-input comparator A through the capacitor C4 and the capacitor C5, the ramp signal is reset to a fixed level, then jumps upwards, then starts to fall after the signal is established stably, the ramp reset level has non-ideal characteristic information including offset, clock offset, ramp delay, error of a counter and the like of the comparator, then when the ramp falls to the same level as the reset level, the four-input comparator A turns over and controls the counter to start counting, the signal Vin is coupled in through the capacitor C5, the capacitor node in front of the C4 is driven by the ramp generator, interference is avoided, quantization is not affected, the four-input comparator A starts to compare a ramp signal jump variable with a pixel signal jump variable, when the ramp jump variable is coupled to be equal to the pixel signal jump amount, the four-input comparator A turns over again, the counter is controlled to stop counting, and digital CDS operation is completed. Wherein the C1 capacitance acts to ensure that the coupling characteristics of the two differential pairs of the comparator with respect to the ramp signal are the same.
As shown in fig. 4, the comparator under the differential input signal includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a four-input comparator a, a switch S1, a switch S2 and a switch Srst, wherein one end of the capacitor C1 is connected to the ramp signal Vramp1+ through the switch S1, the other end of the capacitor C1 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the four-input comparator a and the positive output of the four-input comparator a, one end of the capacitor C3 is connected to the ramp signal Vramp1 through the switch S1-, the other end of the capacitor C3 is connected to one end of the capacitor C4, the other end of the capacitor C4 is connected to the other end of the four-input comparator a and the other end of the capacitor C2, one end of the capacitor C5 is connected to one end of the capacitor C6 and the other end of the ramp signal Vin-through the switch S2, the other end of the capacitor C6 is connected to the other end of the four-input comparator a and the other end of the capacitor C8, and the one end of the capacitor C7 is connected to the other end of the four-input comparator and the negative input signal Vramp 8+ through the switch C8, respectively.
The method of processing the comparator under the differential input signal is the same as the method of processing the comparator under the single-ended input signal: the ramp signal Vramp1+ and the ramp signal Vramp 1-are respectively coupled into a first differential pair of the four-input comparator A through a capacitor C1 and a capacitor C2, a capacitor C3 and a capacitor C4, the switch S1 is controlled, after the first differential pair finishes quantifying the non-ideal characteristic, the switch S1 is disconnected, the first differential pair is in a non-working state, vramp2+ and Vramp2+ are coupled in through a capacitor C5 and a capacitor C6, a capacitor C7 and a capacitor C8, the input signal is respectively coupled in through a capacitor C6 and a capacitor C8 by a signal Vin-and a signal vin+ and is controlled by the switch S2, and after the signal coupling, the switch S2 is disconnected to lighten the load of a front stage.
Fig. 5 is a timing diagram of the comparator under a single-ended input signal according to the present invention.
The overall timing sequence is as follows: during the phase A, the switch S1 is closed, the ramp signal Vramp1 is connected to the left side of the C1, the ramp signal Vramp2 is connected to the left side of the capacitor C4, the reference voltage Vref is connected to the left sides of the capacitor C3 and the capacitor C6, the switch S2 is closed, the signal Vin is connected to the left side of the C5, the switch Srst is closed at the moment, the four-input comparator A is controlled to carry out common mode reset, at the moment, both the positive input end and the negative input end of the two differential pairs are reset to a fixed level, at the moment, the counter does not start working, and the pre-stage CDS circuit is in a sampling state.
And in the stage B, the slope jumps upwards, the jump quantity is coupled with the capacitor C2 through the capacitor C1 and enters the four-input comparator A, at the moment, the differential voltage of the first differential pair is positive, the positive and negative input ends of the second differential pair are both reset voltages, at the moment, the second differential pair does not work, so that the four-input comparator A outputs a low level, and the counter does not work.
When the phase C starts, the switch S1 is switched off, and both ends of the differential pair are at fixed reset level, so that the first differential pair stops working, a signal Vin is coupled into the input of the comparator through the capacitor C5, the differential voltage of the second differential pair is negative, the comparator is turned over, a high level is output, the counter is controlled to start counting, and the quantification of non-ideal characteristics is completed. After the signal Vin completes coupling, i.e., the switch S2 is turned off, the load of the front stage CDS circuit is reduced.
And in the D stage, the ramp jump quantity is equal to the pixel voltage jump quantity, namely Vrst-Vsig, at the moment, the four-input comparator A turns over again, outputs a low level, controls the counter to stop counting, completes the quantization of the pixel voltage, simultaneously completes the operation of digital correlated double sampling, and realizes the elimination of non-ideal characteristics. And then finishing resetting when the ramp voltage continuously drops to the set voltage, and quantifying the next period. Meanwhile, in the middle section of the D stage, the CDS of the front-stage circuit starts to sample the next signal, so that the sampling of the SSADC to the CDS circuit is realized, and the CDS sampling pixel signals is not limited by the quantization of the SSADC reading circuit.
The timing of the comparator under differential input signal is substantially the same as the timing of the comparator under single-ended input signal, as shown in fig. 5, and the comparator structure in the case of full differential is shown in fig. 4. The in-phase end of the first differential pair of the four-input comparator A is connected in series with a capacitor C1, the left side of the capacitor C1 is connected with a switch S1, the left side of the switch S1 is connected with a ramp voltage Vramp1+, the reverse side of the switch S1 is connected with a capacitor C3 and a capacitor C4, the left side of the capacitor C3 is connected with a ramp voltage Vramp1-, the in-phase end is connected with a reverse side and a positive output end through Srst, the in-phase end of the second differential pair is connected with a capacitor C5 and a capacitor C6, the left side of the capacitor C6 is connected with Vramp2+, the right side of the switch S2 is connected to the middle of the C5 and the C6, the left side of the switch S2 is connected with an output signal vin+ of a front CDS circuit, the reverse side and the negative output end through a switch Srst, and the left side of the switch S7 is connected with the middle of the capacitor C8.
Fig. 6 is a ramp waveform diagram for the case of two input signals.
Based on the quantization characteristic of the SSADC and the requirement of the SSADC on the gain and the speed of the comparator, a two-stage comparator structure is adopted in the practical application process, the comparator A in the invention is used as a first stage, the circuit structure is shown in fig. 7, two differential pairs are respectively used as input pair tubes of two comparison stages, two constant current source transistors respectively provide current, the transistors of a cross coupling structure are used as load tubes, larger gain can be provided, the structure has stronger stability, and the second-stage structure is a single differential pair comparator of the same structure so as to improve the gain.
It should be emphasized that the examples described herein are illustrative rather than limiting, and therefore the invention includes, but is not limited to, the examples described in the detailed description, as other embodiments derived from the technical solutions of the invention by a person skilled in the art are equally within the scope of the invention.
Claims (4)
1. A comparator for a high-speed column-parallel monoclinic analog-to-digital converter, characterized by: the capacitor comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a four-input comparator A, a switch S1, a switch S2 and a switch Srst, wherein the input signals of the comparators are single-ended input signals, one end of the capacitor C1 is connected with a ramp signal Vramp1 through the switch S1, the other end of the capacitor C1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is respectively connected with the four-input comparator A and the positive output of the four-input comparator A, a reference voltage Vref is connected with one end of the capacitor C3, the other end of the capacitor C3 is respectively connected with the four-input comparator A and the other end of the capacitor C2 through the switch Srst, one side of the capacitor C4 is connected with a ramp signal Vramp2, the other end of the capacitor C4 is respectively connected with the negative output end of the four-input comparator A and the four-input comparator A through the switch S2, the other end of the capacitor C6 is connected with one end of the reference voltage Vref, and the other end of the capacitor C6 is respectively connected with the four-input comparator A and the other end of the capacitor C5 through the switch Srst.
2. A method of processing a comparator for a high speed column-parallel monoclinic analog-to-digital converter as claimed in claim 1, characterized by: the method comprises the following steps: the ramp signal Vramp1 is coupled into the four-input comparator A through the capacitor C1 and the capacitor C2, the Vramp2 is coupled into the four-input comparator A through the capacitor C4 and the capacitor C5, the ramp signal is reset to a fixed level, then jumps upwards, then starts to fall after the signal is built to be stable, when the ramp falls to the same level as the reset level, the four-input comparator A turns over and controls the counter to start counting, the signal Vin is coupled in through the capacitor C5, the four-input comparator A starts to compare a ramp signal jump variable with a pixel signal jump variable, when the ramp jump variable is coupled to be equal to the pixel signal jump variable, the four-input comparator A turns over again, the counter is controlled to stop counting, and the digital CDS operation is completed.
3. A comparator for a high-speed column-parallel monoclinic analog-to-digital converter, characterized by: the capacitor comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a four-input comparator A, a switch S1, a switch S2 and a switch Srst, wherein the input signals of the comparators are differential input signals, one end of the capacitor C1 is connected with a ramp signal Vramp1+ through the switch S1, the other end of the capacitor C1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is respectively connected with the four-input comparator A and the positive output of the four-input comparator A, one end of the capacitor C3 is connected with the ramp signal Vramp 1-through the switch S1, the other end of the capacitor C3 is connected with one end of the capacitor C4, the other end of the capacitor C4 is respectively connected with the other end of the four-input comparator A and the capacitor C2, one end of the other end of the capacitor C5 is respectively connected with one end of the capacitor C6 through the switch S2, the other end of the capacitor C6 is respectively connected with the other end of the four-input comparator A and the other end of the capacitor C8, one end of the other end of the capacitor C7 is respectively connected with the ramp signal Vramp2+ and the other end of the capacitor C8 is connected with the other end of the four-input comparator C8 through the switch S2 and the negative end of the capacitor C8.
4. A method of processing a comparator for a high speed column-parallel monoclinic analog-to-digital converter as claimed in claim 3, characterized in that: the method comprises the following steps: the ramp signal Vramp1+ and the ramp signal Vramp 1-are respectively coupled into a first differential pair of the four-input comparator A through a capacitor C1 and a capacitor C2, a capacitor C3 and a capacitor C4, the switch S1 is controlled, after the first differential pair finishes quantifying the non-ideal characteristic, the switch S1 is disconnected, the first differential pair is in a non-working state, vramp2+ and Vramp2+ are coupled in through a capacitor C5 and a capacitor C6, a capacitor C7 and a capacitor C8, the input signal is respectively coupled in through a capacitor C6 and a capacitor C8 by a signal Vin-and a signal vin+ and is controlled by the switch S2, and after the signal coupling, the switch S2 is disconnected to lighten the load of a front stage.
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