CN110190852B

CN110190852B - High-speed comparator and analog-to-digital converter and reading circuit formed by same

Info

Publication number: CN110190852B
Application number: CN201910504274.7A
Authority: CN
Inventors: 蔡化; 王勇; 张风体; 陈正; 高菊
Original assignee: Chengdu Light Collector Technology Co Ltd
Current assignee: Chengdu Light Collector Technology Co Ltd
Priority date: 2019-06-12
Filing date: 2019-06-12
Publication date: 2021-06-15
Anticipated expiration: 2039-06-12
Also published as: CN110190852A

Abstract

The invention discloses a high-speed comparator which comprises a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a clamping MOS tube, a first capacitor, a second capacitor and a third capacitor, wherein the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the clamping MOS tube, the first capacitor, the; according to the invention, the clamp MOS tube is additionally arranged between the node A and the node B, so that when the output signal of the comparator jumps, the voltage difference between the node A and the node B does not exceed the gate-source conduction voltage drop of the clamp MOS tube, the drain terminal of the first MOS tube connected with the ramp signal does not jump greatly, and the effect of stabilizing the ramp signal is achieved.

Description

High-speed comparator and analog-to-digital converter and reading circuit formed by same

Technical Field

The invention relates to the field of integrated circuits, in particular to a high-speed comparator and an analog-to-digital converter and a reading circuit formed by the high-speed comparator.

Background

CMOS image sensors have been widely used in the imaging fields of video, surveillance, industrial manufacturing, automobiles, home appliances, and the like. The readout circuit of the CMOS image sensor is a readout circuit mainly based on a column-level single-slope analog-to-digital converter (SS-ADC), wherein the SS-ADC has the function of comparing a signal to be quantized with a ramp reference signal, and the compared result is finally quantized through a counter to obtain a binary digital quantity of N bits. One of the most core circuits in the SS-ADC is a comparator, which is used to determine the magnitudes of the ramp signal voltage and the signal voltage to be quantized, and output a "1" or "0" signal as the basis for the quantization of the subsequent counter.

When the output circuit of the image sensor works, the output signal of the comparator jumps from high to low, the jump amplitude is large due to the large gain of the comparator, the jump signal can be fed back to the input end of the comparator through the parasitic capacitor of the comparator, so that the ramp signal shakes from high to low, the ramp signal is deviated, and finally the outputs of other rows of comparators are deviated, so that the output of the monocline analog-to-digital converter is wrong. For example, when the signal potential of some columns is high, the comparators of these columns are turned over first, and the ramp signal is deviated, so that when the comparators of some columns with low signal potential are turned over later, the output result of the comparator is also deviated due to the deviation of the ramp, and the conversion result of the ADC of these columns which are turned over later is erroneous.

Disclosure of Invention

The invention aims to provide a high-speed comparator, which is added with a clamping MOS tube, thereby reducing the influence of large signal jump output by the comparator on a ramp signal and ensuring the output precision of an image sensor circuit.

In order to achieve the purpose, the invention adopts the following technical scheme: a high-speed comparator comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a clamping MOS tube, a first capacitor, a second capacitor and a third capacitor;

the gate of the first MOS transistor is connected to the second plate of the first capacitor, the first plate of the first capacitor is connected to a RAMP signal RAMP, the source of the first MOS transistor is simultaneously connected to the drain of the third MOS transistor and the source of the second MOS transistor, the drain of the first MOS transistor is connected to a node a, the node a is further connected to the gate of the clamp MOS transistor, the drain of the clamp MOS transistor, one end of a first switch, the drain of a fourth MOS transistor, the gate of the fourth MOS transistor and the gate of a fifth MOS transistor, the gate of the third MOS transistor is connected to a comparator voltage bias signal VBN _ CMP, the other end of the first switch is connected to the gate of the first MOS transistor, the gate of the second MOS transistor is connected to the second plate of the second capacitor, the first plate of the second capacitor is connected to a pixel array output signal PIX _ OUT, the drain of the second MOS transistor is connected to a node B, the node B is further connected to the source of the clamp MOS transistor, One end of a second switch, a drain electrode of a fifth MOS tube and a grid electrode of a sixth MOS tube, wherein the other end of the second switch is connected with the grid electrode of the second MOS tube, the grid electrode of a seventh MOS tube is connected with one end of a third switch, and the other end of the third switch is connected with a first polar plate of the third capacitor;

the first switch and the second switch are controlled by a comparator low reset signal RSTN _ CMP, the third switch is controlled by a comparator high reset signal RST _ CMP, and the comparator low reset signal RSTN _ CMP and the comparator high reset signal RST _ CMP are reverse signals;

the source electrodes of the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are connected with a power supply, the source electrode of the third MOS tube, the source electrode of the seventh MOS tube and the second plate of the third capacitor are grounded, and the drain electrodes of the sixth MOS tube and the seventh MOS tube are connected with an output signal of the high-speed comparator.

Further, the source and drain of the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the clamping MOS transistor may be interchanged.

Further, the first switch, the second switch and the third switch are all MOS transistors, wherein gates of the first switch and the second switch are connected to a comparator low reset signal RSTN _ CMP, a gate of the third switch is connected to a comparator high reset signal RST _ CMP, a source of the first switch is connected to a node a, a drain of the first switch is connected to a gate of the first MOS transistor, a source of the second switch is connected to a node B, a drain of the second switch is connected to a gate of the second MOS transistor, a source of the third switch is connected to a first plate of a third capacitor, and a drain of the third switch is connected to a gate of a seventh MOS transistor.

Further, the sources and drains of the first, second and third switches may be interchanged.

An analog-to-digital converter comprises the high-speed comparator and a counter, wherein the output end of the high-speed comparator is connected with the input end of the counter.

An image sensor reading circuit comprises the high-speed comparator, a pixel array, a row selection driving unit, a ramp generator, a counter, a time sequence control unit and an output signal processing unit,

the row selection driving unit is connected with the pixel array, the pixel array comprises N rows of pixel units, the output end of each pixel unit in one row of pixel units is connected with the same high-speed comparator, the ramp generator is simultaneously connected with the N high-speed comparators, the timing sequence control unit is connected with the ramp generator, the high-speed comparators, the counter, the row selection driving unit and the output signal processing unit and used for controlling the timing sequence of the reading circuit, the output end of the comparator is connected with the input end of the counter, and the output end of the counter is connected with the output signal processing unit.

Further, the pixel unit is a four-tube pixel unit.

Further, the RAMP generator sends out a RAMP signal RAMP, which is connected to a first plate of a first capacitor in the high-speed comparator; the pixel array output signal PIX _ OUT is connected to a first plate of a second capacitor in a high-speed comparator, and an output end of the high-speed comparator outputs a signal CMP _ OUT which is connected to the counter.

The invention has the beneficial effects that: according to the invention, the clamp MOS tube is additionally arranged between the node A and the node B, so that when the output signal of the comparator jumps, the voltage difference between the node A and the node B does not exceed the gate-source conduction voltage drop of the clamp MOS tube, the drain terminal of the first MOS tube connected with the ramp signal does not jump greatly, and the effect of stabilizing the ramp signal is achieved.

Drawings

Fig. 1 is a circuit structure diagram of a standard four-tube pixel unit.

Fig. 2 is a timing diagram of the operation of a standard four-tube pixel cell.

Fig. 3 is a circuit structure diagram of the high-speed comparator according to the present invention.

Fig. 4 is a schematic structural diagram of an image sensor provided by the present invention.

Fig. 5 is a timing diagram illustrating the operation of the image sensor according to the present invention.

Fig. 6 is a circuit configuration diagram of a comparator in the prior art.

Fig. 7 is a timing diagram of the operation of the high speed comparator of the present invention and the comparator of the prior art in the readout circuit of the image sensor.

Fig. 8 is a schematic diagram of the integrated nonlinear error of an analog-to-digital converter formed using a comparator in the prior art.

Fig. 9 is a schematic diagram of the integrated nonlinear error of an analog-to-digital converter formed using the high-speed comparator of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

To facilitate understanding of the principle of the comparator, we first introduce an exposure system of the image sensor, as shown in fig. 1, which is a circuit structure of a standard four-transistor pixel unit in the image sensor, and the structure is generally applied to the image sensor in a row exposure mode, where the four-transistor pixel unit is composed of a photodiode PD, a charge transfer transistor Mtg, a reset transistor Mrst, an amplifying transistor Msf, and a row gate transistor Msel. The photodiode PD senses light and generates photoelectrons proportional to the intensity of light. The charge transfer tube Mtg is used to transfer photoelectrons in the PD, and when the control signal TX is high, the charge transfer tube Mtg is turned on to transfer photoelectrons in the photodiode PD to the floating node FD. The reset tube Mrst is used to reset the node FD when the reset signal RX is at a high potential. When the row selection signal SEL is at a high potential and the row selection tube Msel is turned on, the amplifying tube Msf, the row selection tube Msel and the current source to the ground form a path, and at this time, the amplifying tube Msf is essentially a source follower, follows the potential change of the node FD and is finally output from the P _ OUT in fig. 1 to form a pixel array output signal PIX _ OUT.

Fig. 2 is an operation timing sequence of the four-tube pixel unit, which is divided into reset Rst, exposure Exp, and signal Read. In the reset Rst stage, the control signal TX and the reset signal RX are at high levels, the charge transfer transistor Mtg and the reset transistor Mrst are both turned on, the node FD is reset, and the potential thereof is pulled up to VDD. Then, the reset signal RX and the control signal TX are at low levels, and the exposure Exp stage is entered, and the photodiode PD senses light and accumulates electrons. Entering a Read stage, the row selection signal SEL is at a high level, the reset signal RX is at a high level to reset the node FD, the reset signal RX is at a low level, and the control signal TX is kept at a low levelThe time-amplifying transistor Msf is controlled by the FD potential and outputs a reset potential V1 through P _ OUT. Then, the control signal TX is high to transfer electrons on the photodiode PD to FD, and the amplifying transistor Msf is controlled by FD potential and outputs a reset potential V2 through P _ OUT. The potentials of V1 and V2 are converted into digital quantities by a subsequent reading analog-to-digital converter circuit and are subjected to subtraction operation, so that digital quantities actually corresponding to photoelectrons on the photodiode PD are obtained. If the ADC is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT (V2-V1) × 2¹²/VREF。

Fig. 3 is a circuit diagram of a comparator according to the present invention, which includes a first MOS transistor N1, a second MOS transistor N2, a third MOS transistor N3, a fourth MOS transistor N4, a fifth MOS transistor N5, a sixth MOS transistor N6, a seventh MOS transistor N7, a first capacitor C1, a second capacitor C2, and a third capacitor C3; the grid of the first MOS tube N1 is connected with the second plate of the first capacitor C1, the first plate of the first capacitor C1 is connected with RAMP signal RAMP, the source of the first MOS tube N1 is simultaneously connected with the drain of the third MOS tube N3 and the source of the second MOS tube N2, the drain of the first MOS tube N1 is connected with a node A, the node A is also connected with the grid of the clamp MOS tube NC1, the drain of the clamp MOS tube NC1, one end of a first switch NS1, the drain of the fourth MOS tube N4, the grid of the fourth MOS tube N4 and the grid of the fifth MOS tube N5, the grid of the third MOS tube N3 is connected with comparator voltage bias signal VBN _ CMP, the other end of the first switch 1 is connected with the grid of the first MOS tube N1, the grid of the second MOS tube N2 is connected with the second plate of the second capacitor C2, the first plate of the second capacitor C2 is connected with pixel array output signal PINS _ OUT, the drain of the second clamp MOS tube N1 is connected with node NC 2, and the drain of the node NC 67 2 6, One end of a second switch NS2, a drain electrode of a fifth MOS tube N5 and a gate electrode of a sixth MOS tube N6, the other end of the second switch NS2 is connected with the gate electrode of the second MOS tube N2, the gate electrode of a seventh MOS tube N7 is connected with one end of a third switch NS3, and the other end of the third switch NS3 is connected with a first polar plate of a third capacitor C3; the sources of the fourth MOS transistor N4, the fifth MOS transistor N5 and the sixth MOS transistor N6 are connected with a power supply, the source of the third MOS transistor N3, the source of the seventh MOS transistor N7 and the second plate of the third capacitor C3 are grounded, and the drains of the sixth MOS transistor N6 and the seventh MOS transistor N7 are connected with an output signal of the high-speed comparator. The first switch NS1 and the second switch NS2 are controlled by a comparator low reset signal RSTN _ CMP, the third switch NS3 is controlled by a comparator high reset signal RST _ CMP, and the comparator low reset signal RSTN _ CMP and the comparator high reset signal RST _ CMP are inverted signals; in the attached drawing 3, the first switch, the second switch and the third switch are MOS transistors, and the specific connection mode is as follows: the gates of the first switch NS1 and the second switch NS2 are connected with a comparator low reset signal RSTN _ CMP, the gate of the third switch NS3 is connected with a comparator high reset signal RST _ CMP, the source of the first switch NS1 is connected with a node a, the drain of the first switch NS1 is connected with the gate of the first MOS transistor, the source of the second switch NS2 is connected with a node B, the drain of the second switch NS2 is connected with the gate of the second MOS transistor, the source of the third switch NS3 is connected with the first plate of the third capacitor C3, and the drain of the third switch NS3 is connected with the gate of the seventh MOS transistor N7; of course, the switch may be other switches in the prior art.

As can be seen in fig. 3: the first capacitor C1 and the second capacitor C2 are DC blocking capacitors. The first stage amplifying circuit of the high-speed comparator is composed of a first MOS transistor N1, a second MOS transistor N2, a third MOS transistor N3, a fourth MOS transistor N4 and a fifth MOS transistor N5, wherein the third MOS transistor N3 is a current source transistor and provides a fixed bias current Ib for the first stage, the first MOS transistor N1 and the second MOS transistor N2 are input amplifying pair transistors, and the fourth MOS transistor N4 and the fifth MOS transistor N5 are active load transistors. The sixth MOS transistor N6 and the seventh MOS transistor N7 form a second-stage amplification circuit of the comparator, the sixth MOS transistor N6 is a common-source amplification transistor, and the seventh MOS transistor N7 is a self-biased transistor.

Referring to fig. 4, an image sensor readout circuit formed by a comparator used in an image sensor in the present invention includes a pixel array, a row selection driving unit, a ramp generator, a counter, a timing control unit and an output signal processing unit, where the row selection driving unit is connected to the pixel array, the pixel array includes N rows of pixel units, an output terminal of each pixel unit in a row of pixel units is connected to a same high-speed comparator, the ramp generator is simultaneously connected to N high-speed comparators, the timing control unit is connected to the ramp generator, the high-speed comparator, the counter, the row selection driving unit and the output signal processing unit and is used to control a timing of a readout circuit, an output terminal of the comparator is connected to an input terminal of the counter, and an output terminal of the counter is connected to the output signal processing unit. The RAMP generator sends a RAMP signal RAMP which is connected to a first polar plate of a first capacitor in the high-speed comparator; the pixel array output signal PIX _ OUT is connected to a first pole plate of a second capacitor in the high-speed comparator, the output end of the high-speed comparator outputs a signal CMP _ OUT, the signal CMP _ OUT is connected to the counter, and the output result of the counter is transmitted to the output signal processing unit. Wherein the high speed comparator and the technique together form an analog to digital converter.

With continued reference to fig. 4, the pixel array is composed of a plurality of pixel units P as described in fig. 1. The pixel array is read OUT in a ROW-by-ROW manner, specifically, ROW [0], ROW [1], … … ROW [ N-1] and ROW [ N ] in sequence, and each column of the pixel array has an output bus, which is PIX _ OUT [0], PIX _ OUT [1], … PIX _ OUT [ N-1] and PIX _ OUT [ N ]. The PIX _ OUT output is connected to a high speed comparator in the analog to digital converter. The analog-to-digital converter is composed of the high-speed comparator and the counter, the high-speed comparator compares the pixel output with the RAMP signal RAMP, and the comparison result determines the count value of the counter. The analog-to-digital converter respectively judges the V1 and V2 electric potentials, converts the V2-V1 difference into digital quantity and outputs the digital quantity to a system.

Referring to fig. 5, the operation timing of the analog-to-digital converter in the image sensor circuit corresponds to the readout stage in fig. 3: after the Read stage, the row selection signal SEL is at a high level, and the reset signal RX is at a high level, so that the pixel unit is reset. RST _ CMP is a comparator reset control signal, and RST _ CMP is also high to put all comparators into a reset state. The reset signal RX and the comparator reset control comparator high reset signal RST _ CMP are changed from high level to low level, and the analog-digital converter enters a normal working state. The working process of the analog-digital converter comprises two processes of comparison and counting, wherein firstly, when the RAMP starts to descend, the counter CNT starts to count until the comparator signal overturns from low level to high level, the counter CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the analog-to-digital converter needs to perform the above operations twice, the ramp signal is generated twice as a reference of the analog-to-digital converter, the first ramp stage (i.e. the "VR" stage in fig. 5) is that the analog-to-digital converter determines and stores the reset potential V1, and the counter CNT counts and stores the count value CN1 corresponding to the time period t1 during the time period t 1; during the second ramp phase (i.e. during the "VS" phase of fig. 5), the adc will determine and store the reset potential V2, and the counter CNT will count and store the count value CN2 corresponding to the time period t2 within the time period t 2. The final counter CNT outputs the count difference Δ CN equal to CN2-CN1 corresponding to the difference between V2-V1.

With reference to fig. 6, fig. 6 is a circuit diagram of a comparator in the prior art, which includes a first MOS transistor N1 ', a second MOS transistor N2', a third MOS transistor N3 ', a fourth MOS transistor N4', a fifth MOS transistor N5 ', a sixth MOS transistor N6', a seventh MOS transistor N7 ', a first capacitor C1', a second capacitor C2 ', and a third capacitor C3';

it can be seen that there is no clamp MOS transistor in the existing comparator, i.e. node a 'and node B' are directly connected. We set the voltage at node B' to be the signal CM1_ OUT, referring to fig. 7, when the RAMP signal RAMP is higher than the pixel array output signal PIX _ OUT, CM1_ OUT is high and CMP _ OUT is low; otherwise, CM1_ OUT is low and the comparator output signal CMP _ OUT is high. When the comparator high reset signal RST _ CMP and the comparator low reset signal RSTN _ CMP are inverted signals, the comparator high reset signal RST _ CMP is at a high level, and the comparator low reset signal RSTN _ CMP is at a low level, the first switch NS1 ', the second switch NS2 ', and the third switch NS3 ' are turned on, and the comparator is reset. In contrast to the comparator, the RAMP signal RAMP is higher than the pixel array output signal PIX _ OUT first and then lower than the pixel array output signal PIX _ OUT. Therefore, in the comparison process of "VR" and "VS" in fig. 7, a jump from a high level to a low level occurs in CM1_ OUT of the comparator, and since the gain of the first stage of the comparator is generally large (40-60 dB), the amplitude of the jump is large. The large amplitude jump is transferred to the RAMP signal RAMP through the parasitic capacitors Cgd1 and Cgd5 between the CM1_ OUT and the first MOS transistor N1 'and the fifth MOS transistor N5', so that the RAMP signal RAMP is jittered from high to low, and because the charges on the first capacitor C1 'are conserved and the potential changes at the two ends of the first capacitor C1' follow each other, after the RAMP signal RAMP is jittered, the actual RAMP wave deviates from the ideal RAMP wave, and "RAMP _ R" shown in fig. 7 is the RAMP after being affected.

Particularly for column-level analog-to-digital converters, the first comparison "VR" stage of each column is relatively consistent in occurrence position (because the reset values are compared, the reset values are relatively consistent in each column), while the second comparison "VS" stage is relatively different in occurrence position, some columns with small pixel signals are firstly inverted by the comparator, and columns with large signals are then inverted. Thus, the first column that is flipped affects the RAMP signal RAMP to cause it to shift, and the second count value of the column that is flipped later is smaller than the actual value (as shown in fig. 7, the ideal flipping point of the CMP _ OUT output is tp2, the actual flipping point is tp2x, the ideal count value of the counter CNT is CN2, and the actual count value is CN2X), which finally results in an error in the outputs of these column-level analog-to-digital converters with larger signals. Referring to FIG. 7, VSL [0] and VSL [1] are the pixel array output signal PIX _ OUT [0] of the 0 th row of pixel units and the pixel array output signal PIX _ OUT [1] of the 1 st row of pixel units, respectively.

Referring to fig. 3 and 7, the difference between the present invention and the comparator in the prior art is that a clamp MOS transistor NC1 is added, the clamp MOS transistor NC1 is bridged between the CM1_ OUT and the drain terminal of the first MOS transistor N1, and plays a role of diode clamping, so that when the CM1_ OUT jumps, the voltage difference between the node a and the node B does not exceed the gate-source conduction voltage drop of the clamp MOS transistor NC1, and the drain terminal of the first MOS transistor N1 does not jump greatly, thereby achieving the function of stabilizing the RAMP signal RAMP. If the comparator provided in the present invention in fig. 3 is used, the RAMP signal RAMP will not be shifted, and the actual RAMP is "RAMP _ I" in fig. 5.

The analog-to-digital converter provided by the invention comprises the high-speed comparator and the counter, the output end of the high-speed comparator is connected with the input end of the counter, fig. 8 shows the integral nonlinear error of the analog-to-digital converter formed by adopting the high-speed comparator in fig. 6, and fig. 9 shows the integral nonlinear error of the analog-to-digital converter formed by adopting the high-speed comparator in fig. 3.

The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.

Claims

1. A high-speed comparator is characterized by comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a clamping MOS tube, a first capacitor, a second capacitor and a third capacitor;

the gate of the first MOS tube is connected with the second polar plate of the first capacitor, the first polar plate of the first capacitor is connected with a RAMP signal RAMP, the source of the first MOS tube is simultaneously connected with the drain of the third MOS tube and the source of the second MOS tube, the drain of the first MOS tube is connected with a node A, the node A is further connected with the gate of the clamping MOS tube, the drain of the clamping MOS tube, one end of a first switch, the drain of a fourth MOS tube, the gate of the fourth MOS tube and the gate of a fifth MOS tube, the gate of the third MOS tube is connected with a comparator voltage bias signal VBN _ CMP, the other end of the first switch is connected with the gate of the first MOS tube, the gate of the second MOS tube is connected with the second polar plate of the second capacitor, the first polar plate of the second capacitor is connected with a pixel array output signal PIX _ OUT, the drain of the second MOS tube is connected with a node B, and the node B is further connected with the source of the clamping MOS tube, One end of a second switch, a drain electrode of a fifth MOS tube and a grid electrode of a sixth MOS tube, wherein the other end of the second switch is connected with the grid electrode of the second MOS tube, the grid electrode of a seventh MOS tube is connected with one end of a third switch, and the other end of the third switch is connected with a first polar plate of the third capacitor;

2. The high speed comparator according to claim 1, wherein the source and drain of the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the clamp MOS transistor are interchangeable.

3. The high-speed comparator according to claim 1, wherein the first switch, the second switch and the third switch are MOS transistors, wherein gates of the first switch and the second switch are connected to a comparator low reset signal RSTN _ CMP, a gate of the third switch is connected to a comparator high reset signal RST _ CMP, a source of the first switch is connected to a node a, a drain of the first switch is connected to a gate of the first MOS transistor, a source of the second switch is connected to a node B, a drain of the second switch is connected to a gate of the second MOS transistor, a source of the third switch is connected to a first plate of the third capacitor, and a drain of the third switch is connected to a gate of the seventh MOS transistor.

4. A high speed comparator as claimed in claim 3, wherein the sources and drains of the first, second and third switches are interchangeable.

5. An analog-to-digital converter comprising the high-speed comparator of claim 1 and a counter, wherein an output of the high-speed comparator is connected to an input of the counter.

6. An image sensor readout circuit comprising the high speed comparator of claim 1, further comprising a pixel array, a row selection driving unit, a ramp generator, a counter, a timing control unit, and an output signal processing unit,

7. An image sensor readout circuit according to claim 6, wherein the pixel cell is a four-tube pixel cell.

8. An image sensor readout circuit according to claim 6, wherein the RAMP generator generates a RAMP signal RAMP, which is connected to the first plate of the first capacitor in the high speed comparator; the pixel array output signal PIX _ OUT is connected to a first plate of a second capacitor in a high-speed comparator, and an output end of the high-speed comparator outputs a signal CMP _ OUT which is connected to the counter.