JP2009118035A - Solid-state imaging apparatus and electronic device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus for preventing power supply noise based on a transient current during A/D conversion and preventing an S/N decline even when a number of pixel signals are uniform. <P>SOLUTION: The solid-state imaging apparatus includes three comparison parts 4, a ramp waveform generation circuit 5, three latch circuits 6 and a counter 7, etc., in order to A/D convert output signals from the pixel 1 of a pixel array 2 to digital signals using ramp waves and output them. The comparison parts 4 include a comparator, respectively, and different bias currents are respectively set to the plurality of comparators as offsets for differentiating the timing of AD conversion by the comparators. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an electronic apparatus using the same.

2. Description of the Related Art Conventionally, as a solid-state imaging device, a device having a pixel array in which pixels as photoelectric conversion elements are arranged in a matrix and an AD converter is arranged for each readout column of the pixel array is known (for example, a patent) Reference 1).
In the solid-state imaging device having such a configuration (hereinafter referred to as a conventional device), since the AD converter immediately converts the pixel signal from AD, it is not necessary to draw an analog signal and the SN ratio is improved. Further, since an AD converter is arranged for each readout column of the pixel array and signals are processed in parallel, the band per AD converter is low and the SN ratio of the AD converter itself is improved.

By the way, in a conventional apparatus, in order to perform AD conversion, a ramp waveform comparison type capable of high-precision AD conversion with a small area may be used (see, for example, Patent Document 2). In this case, the pixel signal and the ramp waveform are compared by a comparator, and the counter value of the counter when the two signals have the same voltage value is used as the AD conversion result.
For example, when a dark state is photographed uniformly with a conventional lamp waveform comparison type device, many of the pixel signals have the same low level. When many pixel signals in such a state are AD-converted, in many comparators, the timing at which the ramp waveform and the pixel signal become the same voltage is the same. For this reason, in many comparators, the output is simultaneously inverted. When the output of the comparator is inverted, a large amount of current flows transiently and a large power supply noise is generated. This power supply noise causes a decrease in the S / N ratio. In addition, since a uniformly dark image is easily noticeable by human eyes, a decrease in the S / N ratio in such a situation must be avoided.
JP-A-9-238286 JP 2005-347931 A

Therefore, in view of the above points, an object of the present invention is to prevent power supply noise based on a transient current during A / D conversion even when a large number of pixel signals are uniform, and to prevent a decrease in S / N. It is an object of the present invention to provide a solid-state imaging device.
Another object of the present invention is to provide an electronic apparatus that can utilize the solid-state imaging device.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
The first invention includes a plurality of photoelectric conversion elements and a plurality of AD conversion means for comparing the output signals of the plurality of photoelectric conversion elements with a ramp waveform to convert them into digital signals. The predetermined AD conversion means among the means is provided with a predetermined offset so that the AD conversion timing is different.
According to a second invention, in the first invention, each of the plurality of AD conversion means includes a comparator, and the predetermined comparators of the plurality of comparators operate with different bias currents.

In a third aspect based on the first aspect, each of the plurality of AD conversion means includes a comparator, and the power supply voltages of the plurality of comparators are made different depending on the resistance of the power supply wiring.
In a fourth aspect based on the first to third aspects, the AD converter converts a noise component immediately after resetting the photoelectric conversion element into a digital signal, and a pixel signal component after light reception by the photoelectric conversion element Is converted into a digital signal, and the difference between the noise component converted into the digital signal and the pixel signal is used as an image signal.

The fifth invention is a plurality of photoelectric conversion elements, a plurality of storage means for storing output signals of the plurality of photoelectric conversion elements, a plurality of buffer circuits for inputting output signals from the plurality of storage means, A plurality of AD converters for comparing the output signals of the plurality of buffer circuits with a ramp waveform to convert them into digital signals, and a predetermined buffer circuit of the plurality of buffer circuits includes the predetermined buffer circuit; A predetermined offset is provided so that the AD conversion timing of the corresponding AD conversion means is different.
According to a sixth aspect, in the fifth aspect, the plurality of buffer circuits are source follower circuits each composed of a MOS transistor, and the gate length of the MOS transistor is minimized.

7th invention is an electronic device provided with the solid-state imaging device, Comprising: The said solid-state imaging device consists of a solid-state imaging device in any one of the 1st-6th invention.
According to the solid-state imaging device of the present invention having such a configuration, even when a large number of pixel signals are uniform, power supply noise based on a transient current at the time of A / D conversion can be prevented, thereby preventing a decrease in S / N. can do.
Further, according to the electronic apparatus of the present invention, a solid-state imaging device with improved S / N can be used.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First Embodiment of Solid-State Imaging Device)
FIG. 1 shows a configuration of a first embodiment of a solid-state imaging device of the present invention.
As shown in FIG. 1, the first embodiment of the solid-state imaging device includes a pixel array 2 in which pixels 1 that are photoelectric conversion elements have 3 rows × 3 columns. As the pixel 1, a photodiode or the like is used.

In the first embodiment, the output signal from the pixel 1 of the pixel array 2 is A / D converted into a digital signal using a ramp wave and output, so that the vertical scanning circuit 3 and the three comparison units 4 are output. A ramp waveform generation circuit 5, three latch circuits 6, a counter 7, and a horizontal scanning circuit 8.
The vertical scanning circuit 3 selects one of the three rows of the pixel array 2 in order to simultaneously read out the output signals of the three pixels 1 in one row. The output signal of the pixel 1 in the row selected by the vertical scanning circuit 3 appears on the vertical signal line 9 to which the pixel 1 in each column is commonly connected, and is stored in the capacitor C1 or the capacitor C2 in the comparison unit 4. (See FIG. 2).

The comparison unit 4 is configured as shown in FIG. 2, and includes capacitors C1 and C2, switches SW11, SW12, W21, and SW22, a buffer circuit 41, and a comparator 42.
The capacitor C1 stores a noise component immediately after the pixel 1 is reset. The switch SW11 is turned on to accumulate the noise component in the capacitor C1, and the switch SW21 is turned on to supply the accumulated charge to the buffer circuit 41.

The capacitor C2 accumulates a pixel signal component after light reception by the pixel 1. The switch SW12 is turned on to store the pixel signal component in the capacitor C1, and the switch SW22 is turned on to supply the stored charge to the buffer circuit 41.
The buffer circuit 41 selectively receives each charge from the capacitor C1 or the capacitor C2, and outputs a voltage corresponding to the received charge to the input terminal IN− of the comparator 42.

The comparator 42 compares the ramp waveform generated by the ramp waveform generation circuit 5 with the noise component from the capacitor C1, and outputs an inverted output indicating that to the latch circuit 6 when they have the same value. Based on the inverted output, the latch circuit 6 latches (stores) the count value (count value) of the counter 7 at that time as a digital value.
Further, the comparator 42 compares the ramp waveform and the pixel signal from the capacitor C2, and when they have the same value, outputs an inverted output indicating that to the latch circuit 6. Based on the inverted output, the latch circuit 6 stores the count value of the counter 7 at that time as a digital value.

  The horizontal scanning circuit 8 sequentially selects the digital signals latched by the latch circuit 6 and sends them to a subtraction circuit (not shown). The subtraction circuit obtains an image signal by obtaining a difference between the transmitted digital noise component and pixel signal component. The image signal thus obtained is obtained by removing the noise component of the pixel 1 and removing the offset component of the AD converter added as described later.

Next, a specific configuration of the comparator 42 will be described with reference to FIGS.
As shown in FIG. 2, the comparator 42 includes two stages of a differential amplifier circuit 422 and an inverter 424. The comparators 42 included in the plurality of comparison units 4 (three in the example of FIG. 1) are offset so that the timing of A / D conversion differs.
This offset is provided by configuring the differential amplifier circuit 422 constituting the comparator 42 as shown in FIG.

The differential amplifier circuit 422 includes N-type MOS transistors M2 and M3 that constitute a differential input pair, P-type MOS transistors M4 and M5 that are formed of current mirrors and function as active loads, and N-type that functions as a current source. MOS transistor M1.
A desired bias voltage Vb is supplied to the gate of the MOS transistor M1, and a desired bias current I is set.
Now, assuming that the capacitance value of a capacitor (not shown) connected to the output terminal OUT1 of the differential amplifier circuit 422 is C3, the slew rate SR that determines the response speed of the comparator 42 is expressed by the following equation.

  SR = I / 2 / C3 (1)

  According to the equation (1), the response speed of the comparator 42 can be changed by changing the bias current I flowing through the MOS transistor M1. The bias current I is expressed by the following equation assuming that there is no channel length modulation.

I = ½ μCox W / L (Vgs−Vth) ²
= 1/2 μCox W / L (Vb−GND−Vth) ² (2)

Here, μ is the carrier mobility, Cox is the gate capacitance, W / L is the transistor size (channel width / channel length), and Vgs is the gate-source voltage. Vth is a threshold voltage, Vb is a bias voltage applied to the gate, and GND is a ground potential.
According to the equation (2), the bias current I can be adjusted by the bias voltage Vb supplied to the gate of the MOS transistor M1, so that the response speed of the comparator 42 can be adjusted by the adjustment. The response speed of the comparator 42 determines the timing when the comparator 42 A / D converts the pixel signal (output signal) Vs from the pixel 1 in cooperation with the latch circuit 6 and the counter 7. Therefore, the bias voltage Vb supplied to the gate of the MOS transistor M1 determines the timing for A / D conversion.

Therefore, the comparators 41 of the plurality of comparison units 4 shown in FIG. 1 set the bias currents I to be different by setting the bias voltages Vb to be different. Depending on the setting, the comparator 41 has an offset for different A / D conversion timings.
Here, since there is no problem even if the comparator 42 has an offset, in the differential amplifier circuit 422 of FIG. 3, the degree of freedom of parameters of each transistor is expanded. This is the same for each embodiment described later.
For example, in general, the gate length is set longer than the minimum gate length in order to suppress variations in the manufacturing process of MOS transistors. However, in the present invention, even if there are variations in the characteristics of the comparators, they are canceled by performing the difference processing between the noise component and the signal component after AD conversion as will be described later. Small area).

Next, as an example of the AD conversion operation of the first embodiment having such a configuration, the case of 8-bit AD conversion will be described with reference to the timing chart of FIG.
In the period T1 in FIG. 4, light is emitted to the pixels 1 of the pixel array 2, and charges generated by this irradiation are accumulated in the pixels 1.
In the period T2, a signal immediately after the reset of the pixel 1, that is, a noise component is read from the pixel 1. At this time, the switch SW11 of the comparison unit 4 is turned on, and the noise component is accumulated in the capacitor C1. When the accumulation ends, the switch SW11 is turned off.

In the period T3, the pixel signal accumulated according to the amount of light is read from the pixel 1. At this time, the switch SW12 is turned on, and the pixel signal is accumulated in the capacitor C2. The pixel signal includes a signal component depending on the amount of light and a noise component of the pixel 1. When the accumulation ends, the switch SW12 is turned off.
In the period T4, the noise component accumulated in the capacitor C1 in the period T2 is AD converted. At this time, the switch SW21 is turned on, and a noise component is given to the inverting input terminal IN− of the comparator 42 via the buffer circuit 41.

In the case where previously read signal charges remain in the parasitic capacitance (not shown) at the input terminal of the buffer circuit 41 and affect the accuracy of AD conversion, before the switch SW21 is turned on. Means are provided for discharging charges due to parasitic capacitance.
When the voltage value of the inverting input terminal IN− is stabilized after the switch SW21 is turned on, the ramp waveform from the ramp waveform generation circuit 5 is given to the non-inverting input terminal IN + of the comparator 42, and at the same time the counter 7 counts. The numerical value is counted up from “0”. As a result, the output OUT1 of the differential amplifier circuit 422 changes as shown in FIG.

  When the value of the noise component supplied to the inverting input terminal IN− of the comparator 42 becomes equal to the value of the ramp waveform supplied to the non-inverting input terminal IN +, the output OUT2 of the comparator 42 is as shown in FIG. Invert. When there is the inverted output, the latch circuit 6 stores the count value of the counter 7 at that time as a digital value of the noise component. Thereby, AD conversion of the noise component is completed.

  Since this operation example is 8-bit AD conversion, the counter 7 can count from “0” to “255”, but the value of the noise component immediately after the pixel reset is approximately determined and counts up to “255”. There is no need. Here, 6 bits = 63 counts. By reducing the count in this way, the AD conversion time can be shortened and the number of bits of the latch circuit can be reduced.

  As shown in FIG. 2, the comparator 42 has a two-stage configuration including a differential amplifier circuit 422 and an inverter 424. Then, by arbitrarily setting the bias current of the differential amplifier circuit 422 as described above, the waveforms of the output OUT1 of the differential amplifier circuit 422 and the output OUT2 of the inverter 424 are solid lines as shown in FIG. It can be changed in the case of a broken line. That is, the comparator 42 can change the timing when AD conversion is performed by changing the bias current.

  According to the waveforms of the output OUT1 of the differential amplifier circuit 422 and the output OUT2 of the inverter 424 shown in FIG. 4, the response speed is slower in the case of the waveform indicated by the solid line than the waveform indicated by the broken line. For this reason, the counter value of the counter 7 stored in the latch circuit 6 after waveform shaping by the inverter 424 is different. In the case of the waveform indicated by the broken line, the counter value of the counter 7 stored in the latch circuit 6 is “2”, and in the case of the solid line, the counter value is “5”. That is, the offset difference is 3LSB.

  Since each of the three comparison units 4 shown in FIG. 1 includes a comparator 42 as shown in FIG. 2, the bias currents of the comparators 42 are set to be different from each other. For this reason, the response speed of each comparator 42 is changed, and the output OUT2 can be prevented from being inverted simultaneously. In other words, the comparators 42 included in the three comparison units 4 can perform AD conversion at different timings.

Here, a large current flows through the inverter 424 constituting the comparator 42 when the output OUT2 is in a transient state, but the timing at which the output OUT2 is inverted differs among the three comparators 42. The value is lowered and the SN ratio is avoided. The noise component of the pixel is particularly effective because every pixel has the same value.
In the period T5, the pixel signal accumulated in the capacitor C2 in the period T3 is AD converted. The pixel signal includes the noise component of the pixel 1 in the signal component depending on the light amount. At this time, the switch SW22 is turned on, and a pixel signal is given to the inverting input terminal IN− of the comparator 42 via the buffer circuit 41.

When the voltage value of the inverting input terminal IN− is stabilized after the switch SW22 is turned on, the ramp waveform from the ramp waveform generating circuit 5 is given to the non-inverting input terminal IN + of the comparator 42. At the same time, the count value of the counter 7 is counted up from “0”.
When the value of the pixel signal supplied to the inverting input terminal IN− of the comparator 42 is equal to the value of the ramp waveform supplied to the non-inverting input terminal IN +, the output OUT2 of the comparator 42 is as shown in FIG. Invert. When there is an inverted output, the latch circuit 6 stores the count value of the counter 7 at that time as a digital value of the pixel signal. Thereby, the AD conversion of (signal component + noise component) is completed. In this case, since the signal component depending on the amount of light output from the pixel is AD-converted, the counter 7 counts from “0” to “255”.

  In the AD conversion operation in the period T5, similarly to the AD conversion operation in the period T4, the waveforms of the output OUT1 of the differential amplifier circuit 422 and the output OUT2 of the inverter 424 are solid lines and broken lines as shown in FIG. Case. In other words, even when AD conversion is performed on the same pixel signal, the timing of the count value of the counter 7 stored in the latch circuit 6 is different as indicated by the broken line and the solid line. In this example, the count values are “180” and “183”, which is an offset difference of 3LSB as in the case of the noise component.

  Normally, the signal component depending on the amount of light has a different signal level for each pixel, but when photographing a dark image uniformly, the signal components of many pixels have the same value. When the signal component having the same value is AD-converted in the period T5, as in the case where the noise component is AD-converted in the period T4, it is possible to avoid the majority of comparators from operating at the same time. A reduction in the ratio can be prevented.

  Further, after AD conversion of the noise component in period T4 and (signal component + noise component) in period T5, the horizontal scanning circuit 8 outputs the AD conversion result of the noise component and (signal component + noise component) from the latch circuit 6. Output sequentially. Then, a subtraction circuit (not shown) obtains the difference between the two signals output from the latch circuit 6. In the case of the broken line waveform shown in FIG. 4, the difference is 180-2 = 178, and in the case of the solid line waveform, the difference is 183-5 = 178. A high-quality image with the offset component canceled is output.

As described above, in the first embodiment, different bias currents are set in the plurality of comparators 42 as an offset for differentiating the timing when the comparator 42 performs AD conversion. For this reason, even when the pixel signals of a plurality of pixels are uniform, power supply noise based on a transient current at the time of AD conversion can be prevented, and a decrease in S / N can be prevented.
In the first embodiment, since the difference between the noise component of the pixel signal and the pixel signal component is obtained for each AD conversion, the offset given to the comparator for shifting the AD conversion timing is set for each AD conversion. Can be canceled.

In the first embodiment, different bias currents are set in the plurality of comparators 42 in order to change the timing when the comparator 42 performs AD conversion. However, different bias currents may be set for the predetermined comparators.
That is, it is not necessary for all the comparators constituting the AD converter to have different offsets, and there is no problem if there are several types of offsets, and the majority of comparators constituting the AD converter operate simultaneously. I just want to avoid doing that. This concept is the same in each embodiment described later.

(Second Embodiment of Solid-State Imaging Device)
As in the configuration of the first embodiment shown in FIG. 1, the second embodiment of the solid-state imaging device of the present invention has different timings when AD conversion is performed by the comparators 42 included in the plurality of comparison units 4. Each of the comparators 42 has an offset. In the second embodiment, the power supply voltage applied to the plurality of comparators 42 is changed as the offset.
In addition, since the structure of the other part of this 2nd Embodiment is the same as the structure of 1st Embodiment shown in FIG. 1, the description is abbreviate | omitted.

Next, a specific configuration for providing the comparator 42 with the above-described offset will be described with reference to FIG.
Since the comparators 42 included in the comparison unit 4 are arranged in each column of the pixels 1 of the pixel array 2 (see FIG. 1), they are common in the row direction (lateral direction in FIG. 1), and are on the side of the power supply voltage VDD The power supply line 51 and the ground-side power supply line 52 are respectively connected. For example, assuming a solid-state imaging device having a VGA number of pixels, 640 comparators 42 are connected to the same power supply lines 51 and 52 in at least the row direction. Here, one end of the power supply line 51 is connected to the VDD pad 53, and one end of the power supply line 52 is connected to the GND pad 54.

  Since the power supply lines 51 and 52 have resistance as shown in FIG. 5A, a voltage drop occurs due to the current from the 640 comparators 42. For this reason, the potential of the power supply line 52 on the ground side increases as the distance from the ground pad 54 increases as shown in FIG. The bias voltage Vb supplied to the comparator 42 has the same potential in any comparator 42 because the MOS transistor has a high impedance.

For this reason, according to the equation (2), the bias current I decreases as the ground potential GND increases as the ground-side power line 52 moves away from the ground pad 54, that is, as the comparator 42 is further away from the ground pad 54. Become. Therefore, the offset can be added by changing the slew rate of the comparator 42 without applying any special offset means to the comparator 42.
As described above, in the second embodiment, the values of the power supply voltages applied to the plurality of comparators 42 are made different as offsets for making the timing at which the comparator 42 performs AD conversion differ. The power line resistance was used. For this reason, the effect similar to 1st Embodiment is realizable.

(Third embodiment of solid-state imaging device)
As in the configuration of the first embodiment shown in FIG. 1, the third embodiment of the solid-state imaging device of the present invention has different timings when AD conversion is performed by the comparators 42 included in the plurality of comparison units 4. The offset circuit 41 arranged on the input side of the comparator 42 has an offset. In the third embodiment, as the offset, the threshold voltages of the MOS transistors constituting the plurality of offset circuits 41 are made different.
In addition, since the structure of the other part of this 3rd Embodiment is the same as the structure of 1st Embodiment shown in FIG. 1, the description is abbreviate | omitted.

Next, a specific configuration of the buffer circuit 41 included in the comparison unit 4 will be described with reference to FIG.
As shown in FIG. 6, the buffer circuit 41 is composed of a source follower circuit including MOS transistors M6 and M7. The input voltage Vin is inputted to the gate of the MOS transistor M6, and the output voltage Vo is taken out from the common connection part of the MOS transistors M6 and M7. A predetermined bias voltage Vb is applied to the gate of the MOS transistor M7.
Further, the MOS transistors M6 and M7 are offset so that the threshold voltage Vth becomes a different value.
In the source follower circuit, assuming that there is no substrate bias effect and channel length modulation, the circuit current I is expressed by the following equation.

I = 1/2 μCox W / L (Vgs−Vth) ² (3)

Here, Vgs = Vg−Vs, Vg = Vin, and Vs = Vo.
MOS transistors have a variation in threshold voltage Vth of about 10 [mV] due to variations in manufacturing processes. For this reason, an offset variation of about 10 [mV] occurs in the buffer circuit 41, and it is possible to avoid the majority of comparators from operating simultaneously even when AD conversion is performed on an image with uniform brightness.
When the MOS transistor is used in an analog manner, the gate length is increased in order to reduce the variation in the threshold voltage Vth. In the third embodiment, in order to positively utilize the variation, The gate length may be minimal.
Assuming that there is no substrate bias effect, the voltage gain G of the source follower circuit is expressed by the following equation.

  G = Vo / Vin = 1 / (1 + 1 / (gm · rd)) (4)

Here, gm is transconductance, gm = √ (2 μCoxW / L · I), and rd is a drain resistance, which is a value inversely proportional to the gate length.
If gm · rd is sufficiently large, the voltage gain is unity. If the gate length L is reduced, rd becomes small and the voltage gain cannot be approximated to 1, and variations in gm and rd may appear in the voltage gain. That is, the linearity of the AD conversion result varies for each AD converter. In order to avoid such a situation, gm may be increased so that the voltage gain can be approximated to 1 even when the gate width W is increased and rd is decreased.

Next, the third embodiment configured as described above is the same as the configuration of the first embodiment except that the buffer circuit 41 of the first embodiment is configured as shown in FIG.
For this reason, the waveform of each part at the time of operation | movement of 3rd Embodiment (refer FIG. 1) becomes like the timing chart shown in FIG. FIG. 7 differs from FIG. 4 that shows the waveforms of the respective parts during the operation of the first embodiment, in that the output voltage of the buffer circuit 41, that is, the voltage of the inverting input terminal IN− of the comparator 41 is as shown by a solid line or a broken line. It is a changing point. This is because of the difference in threshold voltage Vth of the MOS transistors constituting the buffer circuit 41.
As described above, in the third embodiment, the threshold value of the MOS transistor constituting the buffer circuit arranged on the input side of the comparator 42 is used as an offset for changing the timing when the comparator 42 performs AD conversion. A difference is provided in the voltage Vth. For this reason, the effect similar to 1st Embodiment is realizable.

(Other Embodiments of Solid-State Imaging Device)
In the above embodiment, as an offset for differentiating the timing when the comparator 42 performs AD conversion, the bias current of the comparator 42 is changed, the power supply voltage of the comparator 42 is changed, or the comparison is performed. The threshold voltage Vth of the MOS transistor constituting the buffer circuit arranged on the input side of the unit 42 is changed.
However, the present invention may be realized by appropriately combining two or three of the above as an offset for differentiating the timing when the comparator 42 performs AD conversion.

(Embodiment of electronic device)
Next, an embodiment of the electronic device of the present invention will be described.
The embodiment of the electronic apparatus is an application of the embodiment of the solid-state imaging device. That is, in this embodiment, any one of the above-described solid-state imaging devices is applied to, for example, a video camera, an electronic still camera, or the like.
According to the embodiment of the electronic device having such a configuration, by using the solid-state imaging device, an image from which power supply noise based on a transient current at the time of AD conversion is eliminated can be acquired, and subsequent image processing is easy. become.

1 is a block diagram illustrating a configuration of a first embodiment of a solid-state imaging device of the present invention. It is a block diagram which shows the specific example of the comparison part of FIG. FIG. 3 is a circuit diagram showing a specific example of the differential amplifier circuit of FIG. 2. It is a wave form chart of each part explaining operation of a 1st embodiment. (A) is a figure which shows the structure of the comparator which concerns on 2nd Embodiment of the solid-state imaging device of this invention, (B) is a figure which shows the electric potential distribution in the comparator. It is a figure which shows the structure of the buffer circuit which concerns on 3rd Embodiment of the solid-state imaging device of this invention. It is a wave form chart of each part explaining operation of a 3rd embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel, 2 ... Pixel array, 3 ... Vertical scanning circuit, 4 ... Comparison part, 5 ... Clamp waveform generation circuit, 6 ... Latch circuit, 7 ... Counter, 8 ... Horizontal scanning circuit, 41 ... Buffer circuit, 42 ... Comparator, 51, 52 ... Power supply line, 422 ... Differential amplification circuit, 424 ... Inverter

Claims (7)

A plurality of photoelectric conversion elements;
A plurality of AD conversion means for comparing respective output signals of the plurality of photoelectric conversion elements with a ramp waveform and converting them into digital signals;
2. A solid-state imaging apparatus according to claim 1, wherein predetermined AD conversion means among the plurality of AD conversion means is provided with predetermined offsets so that AD conversion timings are different from each other.   2. The solid-state imaging according to claim 1, wherein each of the plurality of AD conversion units includes a comparator, and a predetermined comparator of the plurality of comparators is operated with a different bias current. apparatus.   2. The solid-state imaging device according to claim 1, wherein each of the plurality of AD conversion units includes a comparator, and a power supply voltage of each of the plurality of comparators is different depending on a resistance of a power supply wiring. The AD conversion means includes
The noise component immediately after resetting the photoelectric conversion element is converted into a digital signal,
The pixel signal component after receiving light of the photoelectric conversion element is converted into a digital signal,
4. The solid-state imaging device according to claim 1, wherein the difference between the noise component converted into a digital signal and the pixel signal is an image signal. A plurality of photoelectric conversion elements;
A plurality of storage means for storing the output signals of the plurality of photoelectric conversion elements;
A plurality of buffer circuits each for inputting output signals from the plurality of storage means;
A plurality of AD conversion means for comparing the output signals of the plurality of buffer circuits with a ramp waveform and converting them into digital signals;
The predetermined buffer circuit of the plurality of buffer circuits is provided with a predetermined offset so that the AD conversion timing of the AD conversion means corresponding to the predetermined buffer circuit is different from each other. Solid-state imaging device.   6. The solid-state imaging device according to claim 5, wherein each of the plurality of buffer circuits is a source follower circuit including a MOS transistor, and a gate length of the MOS transistor is minimized. An electronic device including a solid-state imaging device,
An electronic apparatus comprising the solid-state imaging device according to any one of claims 1 to 6.

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